JP4947416B2 - Electronic device and manufacturing method thereof - Google Patents

Description

  The present invention relates to an electronic device and a manufacturing method thereof, and more particularly to an electronic device in which a conductor pattern is incorporated in an insulating material and a manufacturing method thereof.

  In recent years, small portable devices such as mobile phones and notebook personal computers are rapidly spreading. In order to make these devices more compact, thinner and higher performance, inductors and transformers used in these devices and electronic components such as printed wiring boards on which they are mounted are also made smaller and thinner. Has become an important issue.

In order to meet such a demand, for example, Patent Document 1 discloses an insulating plate in which a conductor pattern is embedded on at least one surface of an insulating plate so that the surface is substantially smooth, and the conductive pattern is embedded with an adhesive sheet (insulating material) interposed therebetween. There has been proposed a manufacturing technique intended to realize both miniaturization and thinning of electronic elements by stacking and integrating each other.
JP 2004-214633 A

  However, in the conventional method, when trying to make the thickness of the adhesive sheet after pressing as thin as required recently (for example, 20 μm or less), in-plane non-uniformity in the thickness of the adhesive sheet, Due to variations in the surface pressure of the press used when laminating and integrating, unevenness inevitably formed on the press surface, the dielectric strength tends to fluctuate greatly depending on the part of the conductor pattern there were.

  In this case, in order to guarantee the lower limit value of the withstand voltage of the product, it is necessary to increase the thickness of the adhesive layer, and as a result, it has been extremely difficult to further reduce the size and thickness of the electronic device. .

  The present invention has been made in view of the above circumstances, and its object is to meet the demands for miniaturization and thinning, while suppressing variations in dielectric strength sufficiently small, thereby significantly improving reliability. An object of the present invention is to provide an electronic device that can be enhanced and a method for manufacturing the same.

  In order to solve the above-described problems, an electronic device manufacturing method according to the present invention includes a step of forming a first conductor pattern on a first transfer substrate, and a second conductor pattern on the second transfer substrate. A step of forming an insulating layer on the first conductor pattern and / or the second conductor pattern, the first conductor pattern and the second conductor pattern are opposed to each other, and the first conductor pattern and A step of disposing an insulating material having adhesiveness between the second conductor patterns; and a step of pressing and integrating the first transfer substrate and the second transfer substrate.

  In such a manufacturing method, ideally, an electronic element in which the first conductor pattern and the second conductor pattern are close to each other in contact with each other through the insulating layer is manufactured by pressure bonding. However, there may be a portion where the insulating material remains thin due to, for example, in-plane variation in pressure in the crimping process. As a result, the insulation distance between the first conductor pattern and the second conductor pattern is substantially equal to the thickness of the insulating layer. Therefore, by forming a thin insulating layer, the electronic device can be easily reduced in thickness and size. In addition, since the insulation distance between the first conductor pattern and the second conductor pattern is determined by the thickness of the insulating layer, it is possible to suppress variations in the withstand voltage. This insulating layer ensures the minimum value of the withstand voltage. In the present invention, an electronic element in which two layers of conductor patterns are close to each other can be manufactured by a single crimping process, and therefore, the process is also very simple.

  For example, in the step of forming the insulating layer, before or after the step of forming the insulating layer, forming the insulating layer in a region excluding the connection portion between the first conductor pattern and the second conductor pattern, It further has the process of forming a conductor layer in the connection part. Thereby, the required connection and insulation of a 1st conductor pattern and a 2nd conductor pattern are ensured.

  Preferably, the step of forming the insulating layer includes the step of insulating the surface by altering the surface of the first conductor pattern and / or the second conductor pattern to form the insulating layer; Removing the insulating layer. In this way, unlike applying an insulator, by insulating the surface of the conductor pattern by chemically altering it, the surface of the conductor pattern is thinly and uniformly insulated without being affected by the level difference of the base. A layer can be formed.

  In the step of forming the conductor layer and the insulating layer, the insulating layer is formed on one of the first conductor pattern and the second conductor pattern, and the first conductor pattern and the second conductor pattern The conductor layer is formed on the other. Thereby, formation of the insulating layer on the first conductor pattern and formation of the conductor layer on the second conductor pattern can be processed in parallel, and the conductor layer and the insulating layer are formed on one substrate side. Compared with, productivity can be improved.

  Preferably, the method further includes a step of removing the first transfer substrate and the second transfer substrate after the step of pressing and integrating the first transfer substrate and the second transfer substrate. Thereby, the electronic device in which the first conductor pattern and the second conductor pattern are exposed from both surfaces of the insulating material is manufactured. By removing the transfer substrate used for manufacturing, the entire electronic device can be made thinner.

  In the step of removing the first transfer substrate and the second transfer substrate, the first transfer substrate and the second transfer substrate are removed by wet etching. By removing the transfer substrate by wet etching instead of peeling off the transfer substrate, it is possible to prevent the conductor pattern and part of the insulating material from being peeled off together with the substrate, thereby reducing the yield. Nor.

  In the step of pressing and integrating the first transfer substrate and the second transfer substrate, the first transfer is performed by interposing the insulating material having a through-hole formed at least in the region of the connection portion. The substrate for use and the second transfer substrate are pressure-bonded. In other words, the conductor layer is not covered with the insulating material. Thereby, before an insulating material flows into a connection part, a 1st conductor pattern and a 2nd conductor pattern can be connected by a conductor layer, and a connection failure can be prevented.

  In order to solve the above problems, an electronic device according to the present invention includes an insulating material and a first conductor pattern embedded in one surface side of the insulating material and exposed on the one surface of the insulating material. And the second conductor pattern embedded in the other surface side of the insulating material and exposed on the other surface of the insulating material, and the connection portion of the first conductor pattern and the second conductor pattern, A conductor layer interposed between the first conductor pattern and the second conductor pattern; and formed on the first conductor pattern and / or the second conductor pattern in a region other than the connection portion; and And at least one unit structure having one conductor pattern and an insulating layer interposed between the second conductor patterns.

  In such a configuration, unlike the prior art, an insulating layer is formed on the first conductor pattern and / or the second conductor pattern instead of disposing the insulating material over the entire two insulating materials in which the conductor pattern is embedded. Since the insulating layer is interposed between the two conductor patterns, the insulating distance between the first conductor pattern and the second conductor pattern is determined by the thickness of the insulating layer. Therefore, the thinning of the electronic element can be easily achieved by forming the thin insulating layer. In addition, since the insulation distance between the first conductor pattern and the second conductor pattern is determined by the thickness of the insulating layer, it is possible to suppress variations in the withstand voltage. This insulating layer ensures the minimum value of the withstand voltage. Furthermore, since the first conductor pattern and the second conductor pattern are exposed from both surfaces of the insulating material, there is no extra insulating material in the thickness direction of the electronic element, and the electronic element can be thinned.

  The insulating layer preferably has a withstand voltage higher than that of the insulating material. Here, the “withstand voltage” in the present invention refers to an applied electric field at which a leakage current becomes a predetermined value (arbitrarily set) when a voltage is applied to a measurement target (insulating layer or insulating material). The above-mentioned dielectric breakdown voltage relationship is based on the assumption that the insulating layer and the insulating material have the same thickness. By selecting a material having a higher withstand voltage than the withstand voltage of the insulating material as the insulating layer, the thickness of the insulating layer necessary to ensure a predetermined withstand voltage can be reduced. Can be realized.

  According to the electronic device of the present invention, it is possible to realize an electronic device that can sufficiently suppress variations in dielectric strength voltage and can greatly improve reliability while meeting demands for downsizing and thinning. . According to the method for manufacturing an electronic element of the present invention, the above-described electronic element can be easily manufactured.

  Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, an example in which a conductor pattern for a planar coil is formed as a conductor pattern will be described, but the present invention is not limited to this.

(First embodiment)
FIG. 1 is a transparent top view showing the main part of the planar coil according to the present embodiment, and FIGS. 2 to 9 are process diagrams showing a state in which the planar coil is manufactured. It is I line sectional drawing.

  FIG. 1 shows a conductor pattern of one layer of the planar coil 1. The planar coil 1 has a pair of electrodes 2 and 3 and a coil pattern 4 connected between the electrodes 2 and 3. The coil pattern 4 and the right electrode 3 are connected via a conductor pattern of a layer (not shown). By laminating two or more conductor patterns shown in FIG. 1 and connecting between the conductor patterns, the number of turns of the planar coil 1 is increased.

  Although a spiral planar coil is shown in FIG. 1, a square coil may be used. Further, the present invention is not limited to the coil conductor pattern 10 and can be applied to any method for forming a conductor pattern constituting an electronic component such as a resistor, a capacitor, or a transistor. In this specification, the electronic element includes all functional elements including a conductor pattern, and includes both passive elements and active elements.

  Next, a method for manufacturing the electronic device according to the above embodiment will be described.

  As shown in FIG. 2, a resist 12 having an opening 12 a is formed on the first transfer substrate 11. The material of the first transfer substrate 11 is not limited, and examples thereof include a stainless steel substrate, a substrate having a 0.1 to 10 μm nickel layer formed on the surface of the stainless steel substrate by a plating method, and an aluminum substrate. Moreover, the board | substrate which formed thin films, such as copper and nickel, on the surface of insulating films, such as a polyimide excellent in dimensional stability and mechanical strength, may be sufficient. From the viewpoint of forming the conductor pattern by electroplating, it is preferable that at least the surface of the first transfer substrate 11 has conductivity.

  The stainless steel plate preferably has a thickness of about 0.01 to 2 mm, more preferably 0.05 to 1 mm, in order to ensure the strength and dimensional stability of the substrate during the process. The stainless steel plate as the first transfer substrate 11 desirably has an appropriate roughness, and the surface roughness is preferably in the range of Rmax = 0.2 to 2 μm. If Rmax is less than 0.2 μm, the adhesion between the resist and conductor pattern and the stainless steel plate becomes insufficient, and it becomes easy to peel off. On the other hand, if Rmax exceeds 2 μm, it is not preferable because it provides a variation in the film thickness of the conductor pattern and increases the conductor loss when used for high frequency. It is preferable to form a passivated film on the surface of the stainless steel plate by a passivating treatment in order to ensure peelability from the conductor pattern. In this case, although the resistance is increased by the passive film, a passive film having a thickness that allows subsequent electroplating is formed. For example, as the first transfer substrate 11, a surface of a stainless plate (SUS304 tension annealed material) having a thickness of 1 mm and a surface roughness Rmax of 0.5 μm is passivated and cut into a size of 100 mm square. Can do.

  In forming the resist 12, a dry film as a photoresist having a thickness of about 50 μm is stuck on the first transfer substrate 11, and photolithography processing (exposure and development processing) is performed. Thus, a resist 12 having an opening 12a corresponding to a desired conductor pattern, for example, the electrodes 2, 3 and the coil pattern 4, is formed. The width and interval of the conductor pattern are not particularly limited. For example, the width is 70 μm and the interval is 30 μm.

  Next, as shown in FIG. 3, the first conductor pattern 13 is formed in the opening 12 a of the resist 12 by electroplating with the first transfer substrate 11 as a base. As the first conductor pattern 13, it is preferable to use a metal having a low electric resistance such as Au, Ag, Al, or Cu, but Cu is most preferable from the viewpoint of cost and plating productivity. When forming a Cu conductor pattern by bright copper sulfate plating, use, for example, a copper sulfate plating solution in which an appropriate amount of brightener is added to copper sulfate pentahydrate 200 g / l, sulfuric acid 100 g / l, and chlorine 60 mg / l Just do it. In addition, although there is no limitation in particular about the thickness of the 1st conductor pattern 13, it shall be about 35 micrometers-45 micrometers, for example.

  Next, as shown in FIG. 4, the resist 12 is removed. Specifically, the resist 12 is removed by heating a 5% aqueous sodium hydroxide solution to 50 ° C. and spraying the conductive pattern side with a pressure of 0.15 MPa. Of course, the resist 12 peeling method is not limited to this, and various methods can be adopted.

  Thereafter, the surface of the first conductor pattern 13 is roughened in order to enhance the adhesive force between the first conductor pattern 13 and the resin (insulating material 33) covering the first conductor pattern 13. In this roughening treatment, a blackening treatment with sodium hypochlorite, a treatment with a formic acid-based treatment solution (for example, CZ treatment by MEC), a sulfuric acid / hydrogen peroxide treatment (for example, MB treatment by Nihon McDermid) is used. . The sulfuric acid / hydrogen peroxide treatment is preferable in terms of reliability because the treatment liquid can be made chlorine-free. Here, the upper surface and both side surfaces of the first conductor pattern 13 are roughened, but the conductive substrate 1 formed of stainless steel is not roughened. Thus, it is preferable to use stainless steel for the conductive substrate 1 because a large number of treatment liquids capable of roughing only the conductor pattern can be selected.

  Next, as shown in FIG. 5, the insulating layer 31 is formed on the first conductor pattern 13 on the first conductor pattern 13 in a region other than the connection portion with the other layer. The insulating layer 31 may be formed at least on the surface (upper surface in this example) facing the conductor pattern (second conductor pattern 23) of the other layer among the surfaces of the first conductor pattern 13. However, the insulating layer 31 may also be formed on the side surface of the first conductor pattern 13. An opening is provided in a region on the first conductor pattern 13 which is a connection portion with another layer.

This step can be achieved by forming a 5 μm epoxy resin layer on the first conductor pattern 13 other than the connection site by, for example, a screen printing method. Alternatively, an inorganic insulating film layer such as SiO ₂ , SiN, or alumina may be formed on the entire surface by a method such as CVD, plasma CVD, sputtering, or vapor deposition, and the insulating layer at the connection site may be removed by pattern etching. Further, a method of forming a resin layer on the entire surface with an electrodeposition resist and removing the resin layer at the connection site by pattern etching is also used.

  Alternatively, a method may be used in which after the surface of the first conductor pattern 13 is selectively made high in resistance by oxidation, sulfurization, nitridation or the like to form the insulating layer 31, the insulating layer 31 at the connection site is removed by pattern etching. This method is preferable because the process is simple, the productivity is high, and the adhesion between the high resistance layer and the conductor is good. For example, when applying a so-called blackening treatment on a printed circuit board as it is to oxidize the copper surface, a copper oxide dendrite is grown on the surface in a needle shape to increase the adhesion of the conductor pattern to the resin. In the embodiment, it is preferable to form a continuous high resistance layer in order to ensure insulation between the conductor layers. Examples of the method for forming a continuous high resistance layer include thermal oxidation and oxygen plasma treatment.

  Next, as shown in FIG. 6, a conductor layer 32 is formed at a connection site on the first conductor pattern 13. The conductor layer 32 is formed, for example, by applying a conductor paste to the connection site. Examples of the conductive paste include silver paste, copper paste, and solder paste. A highly reliable paste in which an alloy layer is formed by preheating so as to increase the melting temperature is also preferable. Examples of the method for applying the conductor paste include screen printing and injection with a syringe.

  Next, as shown in FIG. 7, an insulating material 33 having adhesiveness is disposed on the first conductor pattern 13 side of the first transfer substrate 11, and further a second transfer substrate 21 provided with a second conductor pattern 23. Face each other.

  As the insulating material having adhesiveness, for example, a prepreg is used. For example, an epoxy resin prepreg having a 20 μm-thick core material is used. By using a prepreg without a core material, the distance between the first transfer substrate 11 and the second transfer substrate 21 after pressure bonding can be reduced, and the electronic element that is finally formed can be thinned. . In addition, the prepreg containing the core material, the adhesive sheet mixed with the filler for adjusting the linear expansion coefficient instead of the core material or together with the core material, and the high dielectric constant filler were mixed to increase the dielectric constant. An insulating material may be used.

  Moreover, it is preferable to form the through-hole 33a in the position corresponding to a connection site | part in a prepreg. Thereby, before the prepreg flows into the connection site, the first conductor pattern 13 and the second conductor pattern 23 can be connected by the conductor layer 32, and connection failure can be prevented.

  The material of the second transfer substrate 21 and the method of forming the second conductor pattern 23 on the second transfer substrate 21 are the same as those of the first transfer substrate 11. However, the pattern shape of the second conductor pattern 23 is not limited. The first transfer substrate 11 and the second transfer substrate 21 are used after being dried in a convection oven at 100 ° C. for 30 minutes after the formation of the conductor pattern.

  Next, as shown in FIG. 8, the insulating material 33 and the two transfer substrates 11 and 21 are stacked and pressure-bonded. Thereby, the first conductor pattern 13 and the second conductor pattern 23 are embedded in the surface of the insulating material 33. In the crimping step, it is preferable to vacuum press while heating both substrates. The generation of voids can be suppressed by vacuum pressing. In the pressing step, pressure is applied until the second conductor pattern 23 is substantially in contact with the insulating layer 31 formed on the first conductor pattern 13. Thereby, the 2nd conductor pattern 23 and the 1st conductor pattern 13 are connected via the conductor layer 32 in a connection part, and are insulated by the insulating layer 31 in areas other than a connection part.

  Next, as shown in FIG. 9, the first transfer substrate 11 and the second transfer substrate 21 are removed by wet etching. By removing the transfer substrates 11 and 21, an electronic element in which the first conductor pattern 13 is embedded in one surface of the insulating material 33 and the second conductor pattern 23 is embedded in the other surface of the insulating material 33 is obtained. can get. At this time, the conductor patterns 13 and 23 are embedded so that both surfaces of the insulating material 33 become substantially smooth. In addition, the conductor patterns 13 and 23 are exposed from both surfaces of the insulating material 33. The transfer substrates 11 and 21 may be peeled off without performing wet etching.

  As a subsequent process, an electronic element is completed by sticking a magnetic thin film on both sides of the base material provided with the first conductor pattern 13 and the second conductor pattern 23 through an insulating layer as necessary.

  According to the electronic device and the manufacturing method thereof according to the above-described embodiment, most of the excess resin constituting the insulating material 33 is formed on the inner side (opposing surface side) and the outer side of the first conductor pattern 13 and the second conductor pattern 23. Since it is not formed, the thickness of the electronic device can be reduced to the total thickness of the first conductor pattern 13, the conductor layer 32, and the second conductor pattern 23. Therefore, the electronic device can be thinned.

  Further, since the interlayer insulating film between the first conductor pattern 13 and the second conductor pattern 23 is determined by the thickness of the insulating layer 31, it is possible to reduce the thickness of the electronic element, and to reduce the thickness of the interlayer insulating film. Can be suppressed. As a result, variations in dielectric strength can be suppressed. In addition, the insulating layer 31 can ensure the minimum value of the withstand voltage.

  In addition, according to the method for manufacturing an electronic element according to the present embodiment, an electronic element in which the two first conductor patterns 13 and the second conductor pattern 23 are overlaid can be manufactured only through one vacuum pressing step. The number of steps and cost can be reduced as compared with the case where a plurality of vacuum presses are used.

  In addition, according to the present embodiment, since the first conductor pattern 13 and the second conductor pattern 23 can be reliably insulated by the insulating layer 31, a thin prepreg without a core material can be used as the insulating material 33. Can contribute.

(Second Embodiment)
In the present embodiment, a method that is different from the first embodiment in the formation method of the insulating layer 31 and the conductor layer 32 will be described. 10-12 is a figure which shows the state which forms the conductor pattern which concerns on 2nd Embodiment.

  First, similarly to the first embodiment, the first conductor pattern 13 is formed on the first transfer substrate 11 through the steps shown in FIGS. Subsequently, as shown in FIG. 10, an insulating layer 31 is formed on the first conductor pattern 13. The method for forming the insulating layer 31 is the same as in the first embodiment.

  On the other hand, as shown in FIG. 11, the conductor layer 32 is formed on the second conductor pattern 23 formed in the same procedure as the first conductor pattern 13. About the formation method of the conductor layer 32, it is the same as that of 1st Embodiment.

  Next, as shown in FIG. 12, in the same manner as in the first embodiment, an insulating material 33 having adhesiveness is disposed on the first conductor pattern 13 side of the first transfer substrate 11, and further, the second conductor pattern The second transfer substrate 21 provided with 23 is opposed.

  As the subsequent steps, the electronic device is completed through the steps after FIG. 8 described in the first embodiment.

  In the present embodiment, unlike the first embodiment, the insulating layer 31 is formed on the first transfer substrate 11 side, and the conductor layer 32 is formed on the second transfer substrate 21 side. The insulating layer 31 may be formed on the second transfer substrate 21 side, and the conductor layer 32 may be formed on the first transfer substrate 11 side.

  Thereby, the formation of the insulating layer 31 on the first conductor pattern 13 and the formation of the conductor layer 32 on the second conductor pattern can be processed in parallel, and the insulating layer 31 and the conductor are formed on one substrate side. Compared with the formation of the layer 32, productivity can be improved. For example, when the insulating layer 31 and the conductor layer 32 are formed on the same substrate using a screen printing method, the insulating layer 31 is screen-printed, and after the insulating layer 31 is dried, the conductor layer 32 is screen-printed. There is a need. This is to prevent the insulating layer from being scraped by touching the insulating layer 31 previously formed by the printing mask. On the other hand, by forming the insulating layer 31 and the conductor layer 32 on separate substrates, the waiting time between the two screen printing steps can be omitted, and the productivity can be improved.

(Third embodiment)
In the first embodiment, an example of an electronic element including two conductor pattern layers has been described. In the present embodiment, an example of an electronic element including four conductor pattern layers will be described.

FIG. 13 is a cross-sectional view of a main part of the electronic device according to the present embodiment.
The electronic device according to the present embodiment is formed by pressure-bonding two unit structures 10 each having a conductor pattern that has been subjected to the process shown in FIG. Thereby, an electronic element in which the four conductor patterns 13 and 23 are laminated is formed.

  Between the two unit structures 10, the conductor layer 35 is interposed at the connection site, and the insulating layer 34 is interposed in the region other than the connection site. The conductor layer 35 is formed on the conductor pattern of one of the two substrates before pressure bonding. The insulating layer 34 is formed on the conductor pattern of one of the two substrates before pressure bonding. The method for forming the conductor layer 35 is the same as the method for forming the conductor layer 32 described in the first embodiment. The method for forming the insulating layer 34 is the same as the method for forming the insulating layer 31 described in the first embodiment. However, since the insulating layer 34 preferably has adhesiveness, it is preferable to form the insulating layer 34 made of an insulating resin by screen printing or the like.

  Since there are no insulating layers on both sides of the unit structure 10 and it is smooth, an electronic device incorporating a multilayer conductor pattern is manufactured with high productivity by bonding a plurality of substrates through the conductor layer 35 and the insulating layer 34. be able to. At this time, the distance between the substrates is determined by the conductor layer 35 and the insulating layer 34, and the electronic device can be thinned. In addition, although the example in which the unit structures 10 are electrically connected to each other via the conductor layer 35 has been described, the unit structures 10 may not be electrically connected.

The present invention is not limited to the description of the above embodiment.
For example, the electronic component according to the present embodiment may include a plurality of functional elements such as coils and resistors. In addition, the materials and numerical values given in the present embodiment are examples, and the present invention is not limited to these.
In the first embodiment, the example in which the conductor layer 32 is formed after the insulating layer 31 is formed has been described. However, the insulating layer 31 may be formed after the conductor layer 32 is formed. Further, the insulating layer 31 and the conductor layer 32 may be formed on the second transfer substrate 21 side without being formed on the first transfer substrate 11 side. Furthermore, the insulating layer 31 and the conductor layer 32 may be formed on both the first transfer substrate 11 and the second transfer substrate 21.
In addition, various modifications can be made without departing from the scope of the present invention.

  According to the electronic device and the method for manufacturing the same according to the present invention, an electronic device that is reduced in size and thickness can be obtained, and thus, particularly downsizing and high performance are required as in a portable device including the electronic device. It can be used widely and effectively in equipment. Examples of the electronic device of the present invention include a planar coil, a transformer using the planar coil, and a common mode filter. Further, the present invention can be applied to electronic parts such as a printed wiring board.

It is a see-through | perspective top view which shows the principal part of the electronic device which concerns on 1st Embodiment. It is process drawing which shows the state which forms the conductor pattern which concerns on 1st Embodiment. It is process drawing which shows the state which forms the conductor pattern which concerns on 1st Embodiment. It is process drawing which shows the state which forms the conductor pattern which concerns on 1st Embodiment. It is process drawing which shows the state which forms the conductor pattern which concerns on 1st Embodiment. It is process drawing which shows the state which forms the conductor pattern which concerns on 1st Embodiment. It is process drawing which shows the state which forms the conductor pattern which concerns on 1st Embodiment. It is process drawing which shows the state which forms the conductor pattern which concerns on 1st Embodiment. It is process drawing which shows the state which forms the conductor pattern which concerns on 1st Embodiment. It is process drawing which shows the state which forms the conductor pattern which concerns on 2nd Embodiment. It is process drawing which shows the state which forms the conductor pattern which concerns on 2nd Embodiment. It is process drawing which shows the state which forms the conductor pattern which concerns on 2nd Embodiment. It is principal part sectional drawing of the electronic device which concerns on 3rd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Planar coil, 2 ... Electrode, 3 ... Electrode, 4 ... Coil pattern, 10 ... Unit structure, 11 ... 1st transfer substrate, 12 ... Resist, 12a ... Opening part, 13 ... 1st conductor pattern, 21 ... 1st 2 transfer substrate, 23 ... second conductor pattern, 31 ... insulating layer, 32 ... conductor layer, 33 ... insulating material, 33a ... through hole, 34 ... insulating layer, 35 ... conductor layer.

Claims (5)

Forming a first conductor pattern on the first transfer substrate;
Forming a second conductor pattern on the second transfer substrate;
On the first conductor pattern and / or the second conductor pattern, an insulating layer is formed by insulating the surface of the first conductor pattern and the second conductor pattern except for a connection portion between the first conductor pattern and the second conductor pattern by altering the surface. Forming, and
Before or after the step of forming the insulating layer, a step of forming a conductor layer at the connection site;
An insulating material having adhesiveness, wherein the first transfer substrate and the second transfer substrate are opposed to each other, and a through hole is formed at least in the region of the connection portion between the first conductor pattern and the second conductor pattern. A step of arranging
Integrating the first transfer substrate and the second transfer substrate by pressure bonding until the insulation distance between the first conductor pattern and the second conductor pattern is equal to the thickness of the insulating layer ;
The manufacturing method of the electronic device which has this. In the step of forming the conductor layer and the insulating layer,
Forming the insulating layer on one of the first conductor pattern and the second conductor pattern, and forming the conductor layer on the other of the first conductor pattern and the second conductor pattern;
The manufacturing method of the electronic device of Claim 1 . The method further includes the step of removing the first transfer substrate and the second transfer substrate after the step of pressing and integrating the first transfer substrate and the second transfer substrate.
The manufacturing method of the electronic device of Claim 1 or 2 . Insulation,
A first conductor pattern embedded in one surface of the insulating material and exposed on the one surface of the insulating material;
A second conductor pattern embedded in the other surface of the insulating material and exposed on the other surface of the insulating material;
In the connection part of the first conductor pattern and the second conductor pattern, a conductor layer interposed between the first conductor pattern and the second conductor pattern;
The first conductor pattern which is formed on the first conductor pattern and / or the second conductor pattern in a region other than the connection part and is interposed between the first conductor pattern and the second conductor pattern. And / or an insulating layer formed by altering the surface of the second conductor pattern ;
Have
An electronic device comprising at least one unit structure in which an insulation distance between the first conductor pattern and the second conductor pattern is equal to a thickness of the insulating layer . The insulating layer has a withstand voltage higher than the withstand voltage of the insulating material,
The electronic device according to claim 4 .

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