JP2008085083A - Manufacturing method of capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method capable of manufacturing a capacitor with a desired electrostatic capacity stably by a thin film process. <P>SOLUTION: The capacitor manufacturing method comprises processes of preparing a substrate 10 with a metal layer 12a formed on its external surface, forming an insulating layer 20 which is has openings 20x in its regions in each of which a dielectric pattern layer 14 is disposed on the metal layer 12a, forming dielectric pattern layers 14 by embedding a dielectric substance in each of the openings 20x formed at the insulating layer 20, forming an upper electrode 16 on each dielectric pattern layer 14 and removing the insulating layer 20, and forming a lower electrode 12 under each dielectric pattern layer 14 by patterning the metal layer 12a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a capacitor, and more particularly, to a method for manufacturing a capacitor that includes a lower electrode, a dielectric layer, and an upper electrode and can be disposed and built in a wiring board by a thin film process.

  2. Description of the Related Art Conventionally, there is a capacitor that is composed of a lower electrode, a dielectric layer, and an upper electrode, and is arranged and built in a wiring board by a thin film process. As shown in FIGS. 1A and 1B, a method for manufacturing such a capacitor includes preparing a substrate 100 on which a first copper foil 200a is adhered, and placing a dielectric on the first copper foil 200a. The dielectric layer 300a is formed by coating. Furthermore, as shown in FIG.1 (c), the 2nd copper foil 400a is stuck on the dielectric material layer 300a.

  Subsequently, as shown in FIG. 2 (a), a required resist pattern (not shown) is formed on the second copper foil 400a, and the second copper foil 400a is etched using the resist pattern as a mask. An electrode 400 is obtained.

  Next, as shown in FIG. 2B, the dielectric pattern layer 300 is obtained by wet-etching the dielectric layer 300a with an organic solvent using the upper electrode 400 as a mask. At this time, the dielectric pattern layer 300 is formed in an undercut shape by side etching from the edge of the upper electrode 400 to the inside.

  Thereafter, as shown in FIG. 2 (c), a required resist pattern (not shown) for covering the upper electrode 400 is formed, and the first copper foil 200a is etched using the resist pattern as a mask, thereby obtaining a dielectric pattern. A lower electrode 200 is formed under the layer 300. Thus, the capacitor C including the lower electrode 200, the dielectric pattern layer 300, and the upper electrode 400 is formed on the substrate 100.

  In Patent Document 1, a first copper foil, a photosensitive dielectric material, and a second copper foil are laminated on an insulating layer, the upper electrode is formed by patterning the second copper foil, and is exposed by ultraviolet irradiation and development. A method of forming a lower electrode and a circuit pattern simultaneously by patterning a first copper foil after patterning a conductive dielectric material to form a dielectric layer is described.

  In Patent Document 2, a recess is formed in an insulating layer on a substrate by an imprint method, a lower electrode is embedded in the recess, and a photosensitive dielectric layer and an upper electrode are formed on the lower electrode. A method of forming a dielectric layer pattern under the upper electrode by exposing and developing the dielectric layer using the upper electrode as a mask is described later.

In Patent Document 3, a first conductive layer, a dielectric layer, a second conductive layer, and a sacrificial layer are formed on a substrate, and the sacrificial layer and the second conductive layer are patterned to form an upper electrode. It is described that a capacitor is formed in a self-aligning manner by sequentially patterning a dielectric layer and a first conductive layer using an upper electrode as a mask.
JP 2006-156934 A JP 2006-128309 A Japanese translation of PCT publication No. 2002-534791

  In the conventional capacitor manufacturing method described above, as shown in FIG. 2B, due to the characteristics of wet etching, the dielectric pattern layer 300 is side-etched inward from the edge of the upper electrode 400 to form an undercut shape. Formed. In addition, since a certain degree of over-etching is required, the side etching amount of the dielectric pattern layer 300 varies considerably within the substrate 100 and between the substrates 100. For this reason, there is a problem that the effective area of the capacitor becomes smaller than the design value and variation occurs, and the capacitance of the capacitor varies accordingly, and the quality is not stable.

  In Patent Documents 1 to 3, no consideration is given to the problem that the effective area of the capacitor (contact area between the dielectric pattern layer and the upper electrode and the lower electrode) varies.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a capacitor capable of stably forming a capacitor capable of obtaining a desired capacitance by a thin film process.

  In order to solve the above-mentioned problems, the present invention relates to a method for manufacturing a capacitor, comprising a step of preparing a substrate having a metal layer formed on an outer surface, and an insulating layer having an opening in a region where a dielectric pattern layer is disposed. Forming on the metal layer, embedding a dielectric in the opening of the insulating layer to form the dielectric pattern layer, and forming an upper electrode on the dielectric pattern layer In addition, the method includes a step of removing the insulating layer and a step of forming a lower electrode under the dielectric pattern layer by patterning the metal layer.

  In the present invention, first, a substrate having a metal layer (copper foil or the like) formed on the outer surface is prepared, and an insulating layer (resist or the like) provided with an opening in a region where the dielectric pattern layer is disposed is formed on the metal layer. Form on top. Furthermore, a dielectric pattern layer is formed by embedding a dielectric in the opening of the insulating layer by a squeegee method or the like. Next, after an upper electrode is formed on the dielectric pattern layer, the insulating layer is removed to expose the metal layer. When a resist is used as the insulating layer, the insulating layer is simultaneously removed in the step of removing the resist pattern used when forming the upper electrode. Thereafter, the lower electrode is formed under the dielectric pattern layer by patterning the metal layer.

  In the present invention, the contact area between the dielectric pattern layer and the upper and lower electrodes is defined by the opening of the insulating layer. When the insulating layer is made of a resist, the opening is stably formed with high dimensional accuracy by photolithography. Therefore, the dimensional accuracy of the dielectric pattern layer can be remarkably improved as compared with the case where the dielectric pattern layer is formed by wet etching the dielectric layer as in the prior art. Thereby, variation in contact area between the dielectric layer and the upper electrode and the lower electrode is suppressed, and a capacitor having a desired capacitance can be stably formed.

  In order to solve the above problems, the present invention relates to a method of manufacturing a capacitor, and includes a step of forming a lower electrode by patterning a metal layer formed on an outer surface of a substrate, and a pattern region of the lower electrode. Forming an insulating layer provided with an opening on the substrate; forming a dielectric pattern layer by embedding a dielectric in the opening of the insulating layer; and over the dielectric pattern layer. And a step of forming an upper electrode.

  In the present invention, a lower electrode is formed in advance on a substrate, and an insulating layer having an opening in the pattern region of the lower electrode is formed on the substrate. Further, after forming a dielectric pattern layer in the opening of the insulating layer by a squeegee method or the like, an upper electrode is formed on the dielectric pattern layer.

  In the present invention, since it is not necessary to remove the insulating layer since the lower electrode is formed first, a resin layer that cannot be peeled can be used as the insulating layer. The opening of the resin layer is formed with high dimensional accuracy by a laser. Note that a resist may be used as the insulating layer.

  Also in the present invention, since the contact area between the dielectric pattern layer and the lower electrode is accurately defined by the opening of the insulating layer, variation in the effective area of the capacitor is suppressed, and a capacitor having a desired capacitance can be obtained. It can be formed stably.

  In a preferred embodiment in which the capacitor is built in the wiring board using the capacitor manufacturing method of the present invention described above, the substrate is provided with a through-hole conductive layer penetrating the capacitor, and in the step of forming the lower electrode, A wiring pattern connected to the through-hole conductive layer is formed at the same time, and a lower electrode is formed connected to the required wiring pattern. Then, before or after the step of forming the lower electrode, a wiring pattern connected to the through-hole conductive layer is formed on the lower surface side of the substrate. Thereby, the lower electrode of the capacitor is electrically connected to the wiring pattern on the lower surface side of the substrate through the wiring pattern and the through-hole conductive layer connected to the capacitor.

  Further, a required buildup wiring connected to the wiring pattern and the upper electrode of the capacitor is formed on the upper surface side of the substrate, and a buildup wiring connected to the wiring pattern is also formed on the lower surface side of the substrate. Note that the build-up wiring may be formed only on the side of the substrate on which the capacitor is formed.

  As described above, according to the present invention, variations in the contact area between the dielectric pattern layer and the upper and lower electrodes can be suppressed, and a capacitor having a desired capacitance can be stably formed.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  First, a basic process of the capacitor manufacturing method according to the embodiment of the present invention will be described.

(First basic process)
3 and 4 are sectional views showing a first basic process in the capacitor manufacturing method according to the embodiment of the present invention. As shown in FIG. 3A, first, a substrate 10 on which a first metal layer 12a is formed is prepared. The first metal layer 12a is formed on the substrate 10 by attaching or plating a metal foil such as copper. Thereafter, as shown in FIG. 3B, an insulating layer 20 having an opening 20x in the capacitor formation region is formed on the first metal layer 12a. In the first basic process, a photosensitive resist such as a dry film resist that can be easily peeled is used as the insulating layer 20, and the opening 20x is formed by photolithography.

  Next, as shown in FIG. 3C, a paste-like dielectric 14 a is disposed on the end side of the substrate 10, and the dielectric 14 a is applied while being moved laterally by a squeegee 19. After the dielectric 14a is selectively embedded in the opening 20x, the dielectric 14a is cured by heat treatment. As a result, as shown in FIG. 3D, the dielectric pattern layer 14 that is electrically coupled to the first metal layer 12 a is formed in the opening 20 x of the insulating layer 20. In addition to the squeegee method, the dielectric pattern layer 14 may be formed by printing (screen printing or the like).

  Subsequently, as shown in FIG. 3E, a second metal layer 16a is formed on the dielectric pattern layer 14 and the insulating layer 20 by sticking or plating a metal foil such as copper. Further, as shown in FIGS. 4A and 4B, a resist pattern 50 is formed on the second metal layer 16a, and the second metal layer 16a is etched using the resist pattern 50 as a mask. An upper electrode 16 is formed on the layer 14. The upper electrode 16 is formed so as to cover the entire upper surface of the dielectric pattern layer 14. The upper electrode 16 may be formed by other methods such as a semi-additive method.

  Further, as shown in FIG. 4C, the resist pattern 50 is removed, and the insulating layer 20 exposed to the periphery is removed to expose the first metal layer 12a. When the insulating layer 20 is made of a dry film resist, the insulating layer 20 is simultaneously removed when the resist pattern 50 is removed.

  Next, as shown in FIG. 4D, after the first metal layer 12a is etched using the resist pattern 50 covering the upper electrode 16 as a mask, the resist pattern 50 is removed. As a result, the lower electrode 12 is formed under the dielectric pattern layer 14 as shown in FIG. The lower electrode 12 is formed in contact with the entire lower surface of the dielectric pattern layer 14. As described above, the capacitor C including the lower electrode 12, the dielectric pattern layer 14, and the upper electrode 16 is formed on the substrate 10.

  In the first basic process of the capacitor manufacturing method of the present embodiment, first, after the insulating layer 20 having the required opening 20x is formed on the first metal layer 12a on the substrate 10, the opening is formed. The dielectric pattern 14 is formed by embedding the dielectric 14a in the portion 20x. Then, after the upper electrode 16 is formed on the dielectric pattern layer 14 and the insulating layer 20 is removed, the first metal layer 12a is patterned to form the lower electrode 12.

  By adopting such a manufacturing method, the dielectric pattern layer 14 is formed in the opening 20x of the insulating layer 20 in a self-aligned manner. Therefore, the dielectric pattern layer 14, the upper electrode 16 and the lower electrode 12 The contact area is defined by the opening 20x of the insulating layer 20. The opening 20x of the insulating layer 20 is formed with high dimensional accuracy because, for example, a dry film resist is formed by photolithography.

  Therefore, the dimensional accuracy of the dielectric pattern layer can be remarkably improved as compared with the method of forming the dielectric pattern layer by wet etching the dielectric layer. Thereby, a capacitor having a desired effective area can be stably obtained within one substrate 10 or between a plurality of substrates 10, and variations in capacitance of the capacitor C can be suppressed.

(Second basic process)
FIG. 5 is a cross-sectional view showing a second basic process in the method for manufacturing a capacitor according to the embodiment of the present invention. As shown in FIG. 5A, first, a substrate 10 having a first metal layer 12a formed on the upper surface is prepared. The first metal layer 12a is formed on the substrate 10 by attaching or plating a metal foil such as copper. Thereafter, as shown in FIG. 5B, the first metal layer 12a is patterned by photolithography and etching to form the lower electrode 12. Furthermore, the insulating layer 20 is formed by sticking a resin film on the lower electrode 12. In the second basic process, the lower electrode 12 can be formed by various methods such as a semi-additive method.

  Next, as illustrated in FIG. 5C, the insulating layer 20 is processed with a laser to form an opening 20 x in the pattern region of the lower electrode 12. Alternatively, the opening 20x may be formed by photolithography using a photosensitive resin (resin remaining as an interlayer insulating layer of the wiring board) as the insulating layer 20.

  Subsequently, as shown in FIG. 5D, the dielectric is embedded in the opening 20x of the insulating layer 20 by a method similar to the first basic process, thereby being electrically coupled to the lower electrode 12. The dielectric pattern layer 14 is formed. Further, as shown in FIG. 5E, an upper electrode 16 that covers the entire upper surface of the dielectric pattern layer 14 is formed on the dielectric pattern layer 14 by a semi-additive method or the like. Thereby, the capacitor C comprised by the lower electrode 12, the dielectric pattern layer 14, and the upper electrode 16 is formed on the board | substrate 10 similarly to a 1st basic process.

  Even in the second basic process, since the contact area between the dielectric pattern layer 14 and the upper electrode 16 and the lower electrode 12 is accurately defined by the opening 20x of the insulating layer 20, variation in the capacitance of the capacitor is suppressed. can do.

  In the first basic process described above, after the dielectric pattern layer 14 and the upper electrode 16 are formed, the lower first metal layer 12a is patterned to form the lower electrode 12. Therefore, after the upper electrode 16 is formed, It is necessary to remove the insulating layer 20 to expose the first metal layer 12a. Therefore, a dry film resist that can be easily peeled off is used as the insulating layer 20.

  On the other hand, in the second basic process, after the first metal layer 12a on the substrate 10 is previously patterned to form the lower electrode 12, the insulating layer 20 having the opening 20x is formed on the lower electrode 12, The dielectric pattern layer 14 and the upper electrode 16 are sequentially formed by the same method as the first basic process. For this reason, since it is not necessary to remove the insulating layer 20 in the second basic process, various insulating materials such as a resin that cannot be peeled can be used as the insulating layer 20.

(Modification of the first basic process)
6A to 6C are cross-sectional views showing a modification of the first basic process in the capacitor manufacturing method according to the embodiment of the present invention. In the first basic process described above, the lower electrode 12 may be formed first as in the second basic process. That is, as shown in FIG. 6A, first, the first metal layer 12a on the substrate 10 is patterned to form the lower electrode 12, and the opening 20x is provided in the pattern region of the lower electrode 12. Layer 20 (dry film resist) is formed. Further, the dielectric pattern layer 14 is embedded in the opening 20x of the insulating layer 20, and the second metal layer 16a is formed thereon, and then the resist pattern 50 is formed thereon. Subsequently, as shown in FIG. 6B, the upper electrode 16 is formed by etching the second metal layer 16a using the resist pattern 50 as a mask. Thereafter, as shown in FIG. 6C, the resist pattern 50 and the insulating layer 20 (dry film resist) are removed. As a result, the capacitor C having the same structure as that shown in FIG. 4E is formed on the substrate 10.

(First embodiment)
Next, a method of incorporating a capacitor in a wiring board using the first basic process in the capacitor manufacturing method of the embodiment of the present invention will be described. 7 to 10 are sectional views showing a method of incorporating a capacitor in a wiring board using the first basic process described above. As shown in FIG. 7A, first, a copper foil having a structure in which a first copper foil 32a and a second copper foil 32b (metal layer) are attached to both sides of an insulating substrate 30a made of glass epoxy resin or the like. The attached substrate 30 is prepared.

  Next, as illustrated in FIG. 7B, the through-hole TH penetrating the substrate with copper foil 30 is formed by processing the substrate with copper foil 30. Further, as shown in FIG. 7C, the through-hole conductive layer 29 is formed by performing metal plating in the through-hole TH. The through-hole conductive layer 29 may be formed on the side wall so that the hole remains in the through-hole TH. In that case, the hole is filled with resin. The first and second copper foils 32 a and 32 b are interconnected via the through-hole conductive layer 29.

  Subsequently, as shown in FIG. 7 (d), a dry film resist 21 (insulating layer) is formed on the first copper foil 32a, and exposure / development is performed based on photolithography. An opening 21x is formed in the upper surface to expose a required portion of the first copper foil 32a. Since the opening 21x of the dry film resist 21 is formed by photolithography, it is stably formed with high dimensional accuracy. As described above, the effective area of the capacitor is defined by the opening 21x of the dry film resist 21.

  Next, as shown in FIG. 8A, a paste-like dielectric is embedded in the opening 21x of the dry film resist 21 by the squeegee method described above, and then heat-treated to electrically connect the first copper foil 32a. A dielectric pattern layer 34 to be bonded is formed. A suitable material for the dielectric pattern layer 34 is a mixture of barium titanate (BaTiO3) and an epoxy resin, or PCZT (Ca, Ti, Cu, Zr, Pb) or BST (Ti, Cu, Sr, Br) or the like mixed with an epoxy resin is used.

  Next, as shown in FIG. 8B, a third copper foil 36 a is stuck on the dielectric pattern layer 34 and the dry film resist 21. Further, as shown in FIG. 8C, a resist pattern 50 is formed on the third copper foil 36a, and the third copper foil 36a is etched using the resist pattern 50 as a mask, whereby the dielectric pattern layer 34 is electrically connected. The upper electrode 36 is formed to be coupled. Further, as shown in FIG. 8D, the resist pattern 50 is removed. At this time, the dry film resist 21 is removed simultaneously with the resist pattern 50, and the upper surface of the first copper foil 32a is exposed.

  Subsequently, as shown in FIG. 9A, a required resist pattern 50 covering the upper electrode 36 is formed on the upper surface side of the substrate 30 with copper foil, and the first copper foil 32a is etched using the resist pattern 50 as a mask. Later, the resist pattern 50 is removed. Thereby, as shown in FIG. 9B, the lower electrode 32 that is electrically coupled to the dielectric pattern layer 34 is formed under the dielectric pattern layer 34. At this time, simultaneously with the formation of the lower electrode 32, the first copper foil 32a is patterned to form the first wiring pattern 42a on the upper surface of the insulating substrate 30a, and the lower electrode 32 is formed to be connected to the required first wiring pattern 42a. Is done.

  Thus, the capacitor C including the lower electrode 32, the dielectric layer pattern 34, and the upper electrode 36 is formed on the insulating substrate 30a. Further, the second copper foil 32b on the lower surface side of the substrate with copper foil 30 is patterned, and the first wiring pattern 42a is also formed on the lower surface of the insulating substrate 30a. The first wiring patterns 42 a on both sides of the insulating substrate 30 a are formed in a state of being interconnected via the through-hole conductive layer 29. Therefore, the lower electrode 32 of the capacitor C is electrically connected to the first wiring layer 42a on the lower surface side of the insulating substrate 30a through the first wiring pattern 42a and the through-hole conductive layer 29 connected to the capacitor C.

  Further, as shown in FIG. 9B, the resistance portion R is connected between the first wiring patterns 42a by applying a resistance paste to the region between the first wiring patterns 42a.

  Next, as shown in FIG. 9C, a first interlayer insulating layer 44a covering the capacitor C and the first wiring pattern 42a is formed on the upper surface side of the insulating substrate 30a. Further, a first interlayer insulating layer 44a covering the first wiring pattern 42a is also formed on the lower surface side of the insulating substrate 30a. The first interlayer insulating layer 44a is formed by resin application or resin film lamination.

  Next, as shown in FIG. 9C, the first interlayer insulating layer 44a on the upper surface side of the insulating substrate 30a is processed with a laser or the like, thereby connecting the upper electrode 36 of the capacitor C and the first wiring pattern 42a. The first via holes VH1 that respectively reach the first and second holes are formed. Similarly, the first via hole VH1 reaching the first wiring pattern 42a is also formed in the first interlayer insulating layer 44a on the lower surface side of the insulating substrate 30a.

  Subsequently, as shown in FIG. 9D, on the upper surface side of the insulating substrate 30a, the upper electrode 36 of the capacitor C and the first wiring pattern 42a are respectively connected via the first via hole VH1 by a semi-additive method or the like. A second wiring pattern 42b is formed on the first interlayer insulating layer 44a. Similarly, on the lower surface side of the insulating substrate 30a, a second wiring pattern 42b connected to the first wiring pattern 42a through the first via hole VH1 is formed on the first interlayer insulating layer 44a.

  In this way, the capacitor C of the present embodiment has the lower electrode 32 connected to the first wiring pattern 42a, the upper electrode 36 connected to the second wiring pattern 42b, and is disposed on the wiring board to be built-in. Is done.

  Next, as shown in FIG. 10, by repeating the same process, the second via hole VH2 provided in the second interlayer insulating layer 44b covering the second wiring pattern 42b is formed on both sides of the insulating substrate 30a. A third wiring pattern 42c connected to the second wiring pattern 42b is formed on the second interlayer insulating layer 44b. Thereafter, on both sides of the insulating substrate 30a, a solder resist 46 provided with an opening 46x is formed on the third wiring pattern 42c, and Ni / Au plating is applied to the third wiring pattern 42c of the opening 46x. To obtain the connecting portions 47 respectively.

  In the example of FIG. 10, two layers of build-up wiring connected to the first wiring patterns 42a on both sides of the insulating substrate 30a are formed, but n layers (n is an integer of 1 or more) are built-up. Wiring can be arbitrarily formed. Further, the capacitor C can be formed between arbitrary layers.

  As described above, the capacitor built-in substrate 1 manufactured using the first basic process of the capacitor manufacturing method of the present embodiment is obtained. As described above, in the method for manufacturing a capacitor according to the present embodiment, variations in the capacitance of the capacitor are suppressed, so that a high-performance capacitor-embedded substrate can be manufactured with a high yield.

  In addition, although the form which laminates | stacks the wiring pattern electrically connected to the capacitor C on both surfaces of the insulating substrate 30a was illustrated, the wiring pattern electrically connected to the capacitor C is laminated | stacked only on the upper surface side of the insulating substrate 30a. It is good also as a form to do. In this case, the through-hole conductive layer 29 provided on the insulating substrate 30a is omitted, a via hole is formed on the connection portion of the first wiring pattern 42a connected to the lower electrode 32 of the capacitor C, and the lower electrode 32 becomes the second wiring pattern. It is electrically connected to 42b.

(Second embodiment)
Next, a method for incorporating a capacitor in a wiring board using the second basic process in the method for manufacturing a capacitor according to the embodiment of the present invention will be described. 11 to 13 are cross-sectional views showing a method of incorporating a capacitor in a wiring board using the second basic process described above. In the second embodiment, the same elements as those in the first embodiment are denoted by the same reference numerals, and detailed description of the manufacturing method and the like is omitted.

  As shown in FIG. 11A, first, similarly to the first embodiment, the through hole TH is formed in the substrate 30 with copper foil, and the through hole conductive layer 29 is formed in the through hole TH. After that, as shown in FIG. 11B, a resist pattern 50 is formed on the first copper foil 32a of the substrate 30 with copper foil, and the first copper foil 32a is etched using the resist pattern 50 as a mask. 50 is removed. As a result, as shown in FIG. 11C, the capacitor lower electrode 32 and the first wiring pattern 42a connected to the through-hole conductive layer 29 are formed at the same time, and the lower electrode 32 has the required first wiring pattern. 42a is formed. Further, as in the first embodiment, a resistor R is connected between the first wiring patterns 42a.

  Next, similarly, the second copper foil 32b on the lower surface side of the substrate with copper foil 30 is patterned to form the first wiring pattern 42a connected to the through-hole conductive layer 29 also on the lower surface of the insulating substrate 30a. Similar to the first embodiment, the first wiring pattern 42 a connected to the lower electrode 32 is connected to the first wiring pattern 42 a on the lower surface of the insulating substrate 30 a through the through-hole conductive layer 29.

  Next, as shown in FIG. 11D, the insulating resin layer 31 that covers the lower electrode 32 and the first wiring pattern 42a is formed by sticking a resin film on the upper surface side of the insulating substrate 30a. Further, the insulating resin layer 31 is processed by a laser to form an opening 31x in the pattern region of the lower electrode 32. In the second embodiment, the effective area of the capacitor is defined by the opening 31x of the insulating resin layer 31. Subsequently, as shown in FIG. 12A, a dielectric pattern layer 34 is formed by embedding a dielectric in the opening 31x of the insulating resin layer 31 by the same method as in the first embodiment.

  Next, as shown in FIG. 12B, a seed layer 36x made of copper or the like is formed on the dielectric pattern layer 34 and the insulating resin layer 31 by electroless plating or sputtering. Subsequently, a resist pattern 50 having an opening 50x is formed in a region where the upper electrode is disposed on the seed layer 36x. Further, as shown in FIG. 12C, a metal pattern layer 36y made of copper or the like is formed in the opening 50x of the resist pattern 50 by electrolytic plating using the seed layer 36x as a plating power feeding path.

  Subsequently, as shown in FIG. 12D, after the resist pattern 50 is removed, the seed layer 36x is etched using the metal pattern layer 36y as a mask, thereby forming the seed layer 36x and the metal pattern layer 36y. The upper electrode 36 is obtained. Thereby, a capacitor C composed of the lower electrode 32, the dielectric pattern layer 34, and the upper electrode 36 is obtained. In the second embodiment, the insulating resin layer 31 exposed on the upper surface side of the insulating substrate 30a is left as it is.

  Next, as shown in FIG. 13, by performing the same steps as in FIGS. 9C to 10 of the first embodiment, the upper electrode 36 and the first wiring of the capacitor C are formed on the upper surface side of the insulating substrate 30a. Two layers of build-up wiring (second wiring pattern 42b, second interlayer insulating layer 44b, and third wiring pattern 42c) connected to the pattern 42a are formed. A similar two-layer build-up wiring connected to the first wiring pattern 42a is also formed on the lower surface side of the insulating substrate 30a.

  Thus, the capacitor built-in substrate 2 of the second embodiment is obtained.

  In the second embodiment, as in the first embodiment, variation in the capacitance of the capacitor is suppressed, so that a high-performance capacitor-embedded substrate can be manufactured with high yield.

1A to 1C are cross-sectional views (No. 1) showing a conventional method for manufacturing a capacitor. 2A to 2C are cross-sectional views (No. 2) showing a conventional method for manufacturing a capacitor. 3A to 3E are cross-sectional views (part 1) showing a first basic process in the capacitor manufacturing method according to the embodiment of the present invention. 4A to 4E are sectional views (No. 2) showing a first basic process in the method for manufacturing a capacitor according to the embodiment of the present invention. 5A to 5E are cross-sectional views showing a second basic process in the capacitor manufacturing method of the embodiment of the present invention. 6A to 6C are cross-sectional views showing a modification of the first basic process in the capacitor manufacturing method according to the embodiment of the present invention. 7A to 7D are cross-sectional views (No. 1) showing a method of incorporating a capacitor in a wiring board using the first basic process in the method for manufacturing a capacitor according to the embodiment of the present invention. FIGS. 8A to 8D are cross-sectional views (part 2) showing a method of incorporating the capacitor in the wiring board using the first basic process in the capacitor manufacturing method of the embodiment of the present invention. FIGS. 9A to 9D are sectional views (No. 3) showing a method of incorporating the capacitor in the wiring board using the first basic process in the capacitor manufacturing method of the embodiment of the present invention. FIG. 10 is a cross-sectional view (No. 4) showing the method of incorporating the capacitor in the wiring board using the first basic process in the method of manufacturing a capacitor according to the embodiment of the present invention. 11A to 11D are cross-sectional views (No. 1) showing a method of incorporating a capacitor in a wiring board using the second basic process in the capacitor manufacturing method of the embodiment of the present invention. 12A to 12D are cross-sectional views (part 2) showing a method of incorporating the capacitor in the wiring board using the second basic process in the capacitor manufacturing method of the embodiment of the present invention. FIG. 13 is a cross-sectional view (No. 3) showing the method of incorporating the capacitor in the wiring board using the second basic process in the capacitor manufacturing method of the embodiment of the present invention.

Explanation of symbols

1, 2 ... capacitor built-in substrate, 10 ... substrate, 12, 32 ... lower electrode, 12a ... first metal layer, 14, 34 ... dielectric pattern layer, 14a ... dielectric, 16, 36 ... upper electrode, 16a ... first 2 metal layers, 19 ... squeegee, 20 ... insulating layer, 20x, 21x, 31x, 46x ... opening, 21 ... dry film resist, 29 ... through-hole conductive layer, 30 ... substrate with copper foil, 31 ... insulating resin layer, 30a ... insulating substrate, 32a ... first copper foil, 32b ... second copper foil, 36a ... third copper foil, 36x ... seed layer, 36y ... metal pattern layer, 42a, 42b, 42c ... wiring pattern, 44a, 44b ... Interlayer insulating layer 46... Solder resist 47. Connection portion 50. Resist pattern TH TH through hole VH via hole R resistance unit C capacitor

Claims (10)

Preparing a substrate having a metal layer formed on the outer surface;
Forming an insulating layer having an opening in a region where the dielectric pattern layer is disposed on the metal layer;
Forming the dielectric pattern layer by embedding a dielectric in the opening of the insulating layer;
Forming an upper electrode on the dielectric pattern layer and removing the insulating layer;
Forming a lower electrode under the dielectric pattern layer by patterning the metal layer.   The method for manufacturing a capacitor according to claim 1, wherein the insulating layer is a resist, and the opening is formed by photolithography. Forming a lower electrode on the substrate;
Forming an insulating layer having an opening in the pattern region of the lower electrode on the substrate;
Forming a dielectric pattern layer by embedding a dielectric in the opening of the insulating layer;
And a step of forming an upper electrode on the dielectric pattern layer. The insulating layer is formed of a resist, the opening is formed by photolithography, and
The method of manufacturing a capacitor according to claim 3, wherein the insulating layer is removed after the upper electrode is formed.   The method for manufacturing a capacitor according to claim 3, wherein the insulating layer is made of resin, the opening is formed by a laser, and the insulating layer is left on the substrate. In the step of forming the dielectric pattern layer,
6. The method of manufacturing a capacitor according to claim 1, wherein a dielectric is embedded in the opening of the insulating layer by a squeegee method or printing.   6. The method of manufacturing a capacitor according to claim 1, wherein the substrate is an insulating substrate, and the lower electrode and the upper electrode are formed by patterning a copper foil. In the step of forming the lower electrode,
6. The method of manufacturing a capacitor according to claim 1, wherein a wiring pattern is simultaneously formed on the substrate, and the lower electrode is formed so as to be connected to the required wiring pattern. The substrate is provided with a through-hole conductive layer penetrating therethrough,
In the step of forming the lower electrode, the wiring pattern is formed connected to the through-hole conductive layer,
Before or after the step of forming the lower electrode, further comprising a step of forming a wiring pattern connected to the through-hole conductive layer on the lower surface side of the substrate;
9. The capacitor according to claim 8, wherein the lower electrode is electrically connected to the wiring pattern on the lower surface side of the substrate through the wiring pattern connected to the lower electrode and the through-hole conductive layer. Manufacturing method. After forming a capacitor composed of the lower electrode, the dielectric pattern layer and the upper electrode,
On the upper surface side of the substrate, an n-layer (n is an integer of 1 or more) build-up wiring connected to the wiring pattern and the upper electrode of the capacitor is formed, and on the lower surface side of the substrate, the wiring pattern The method for manufacturing a capacitor according to claim 9, further comprising a step of forming a buildup wiring of n layers (n is an integer of 1 or more) connected to the capacitor.

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