JP2018073888A - Electronic component and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component and a method of manufacturing the same capable of securing accuracy of a capacitance value and securing a withstand voltage property at the same time.SOLUTION: The electronic component includes: a substrate 2; a first capacitor 3 having a first electrode 31 on the substrate 2, a first dielectric 32 on the first electrode 31, and a second electrode 33 on the first dielectric 32; and a second capacitor 4 connected in series to the first capacitor 3 and having a second electrode 33, a second dielectric 41 on the second electrode 33, and a third electrode 42 on the second dielectric 41.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to an electronic component and a manufacturing method thereof.

  Conventionally, various techniques relating to an electronic component having a capacitor have been proposed. For example, in Patent Document 1, a MIM (Metal-Insulator-Metal) structure capacitor is formed by forming a high dielectric constant thin film on a lower electrode formed on a substrate and further forming an upper electrode thereon. Technology has been proposed. In this technique, the capacitor is formed so that the outer shape of the upper electrode is included in the outer shape of the lower electrode as seen through from above.

JP-A-6-89831

  Since the technique described in Patent Document 1 has a shape in which the outer shape of the upper electrode is included in the outer shape of the lower electrode, it is assumed that some misalignment occurs in the process of forming the upper electrode after the lower electrode is formed. However, since the opposing areas of the upper and lower electrodes do not change, there is an advantage that the capacitance value is not affected.

  On the other hand, the technique described in Patent Document 1 has a problem that it is difficult to avoid the influence of errors generated in the outer dimensions of the upper electrode in the manufacturing process. In particular, when a capacitor having a relatively large capacity and a small capacity capacitor are manufactured simultaneously by using a high dielectric constant film, the small electrode has a small dimensional error due to the small size of the upper electrode of the small capacity capacitor. As a result, the desired capacity accuracy may not be obtained.

  In addition, the technique described in Patent Document 1 has a problem that the dielectric strength between the electrodes is extremely thin by a thin film process, so that the withstand voltage, that is, the dielectric strength is inferior to that of the thick film capacitor.

  The present disclosure has been made in consideration of the above points, and is to provide an electronic component capable of ensuring both capacitance value accuracy and voltage resistance and a method for manufacturing the same.

In order to solve the above problems, in one aspect of the present disclosure,
A substrate;
A first capacitor having a first electrode on the substrate, a first dielectric on the first electrode, and a second electrode on the first dielectric;
An electronic component comprising: a second capacitor connected in series to the first capacitor and having the second electrode, a second dielectric on the second electrode, and a third electrode on the second dielectric is provided. The

  In a plan view, the outer shape of the second electrode may be included in the outer shape of the first electrode, and the outer shape of the third electrode may be included in the outer shape of the second electrode.

  The thickness of the second electrode may be smaller than the thickness of the first electrode.

  A third capacitor having a fourth electrode on the substrate, a third dielectric on the fourth electrode, and a fifth electrode on the third dielectric may further be provided.

  You may further provide the 1st wiring which connects the said 2nd capacitor and the said 3rd capacitor in series on the said 3rd and 5th electrode.

The fourth electrode is connected to the first electrode on the substrate;
The electronic component further includes a second wiring that connects the first and second capacitors and the third capacitor in parallel between the first and fourth electrodes on the third and fifth electrodes. Good.

  A through electrode connected to the first and second capacitors and penetrating the base material may be further provided.

In another aspect of the disclosure,
Forming a first capacitor comprising: forming a first electrode on a substrate; forming a first dielectric on the first electrode; and forming a second electrode on the first dielectric; ,
Forming a second capacitor connected in series to the first capacitor, comprising: forming a second dielectric on the second electrode; and forming a third electrode on the second dielectric. An electronic component manufacturing method is provided.

  According to the present disclosure, it is possible to ensure both the capacitance value accuracy and the voltage resistance.

It is sectional drawing which shows the electronic component by this embodiment. It is a top view which shows the electronic component by this embodiment. It is an equivalent circuit schematic of the electronic component by this embodiment. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 4A. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 4B. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 4C. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 4D. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 4E. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 5A. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 5B. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 5C. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 5D. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 6A. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 6B. FIG. 6D is a cross-sectional view illustrating the method for manufacturing the electronic component according to the present embodiment following FIG. 6C. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 7A. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 7B. FIG. 7C is a cross-sectional view showing the method for manufacturing the electronic component according to the present embodiment following FIG. 7C. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 7D. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 8A. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 8B. FIG. 8D is a cross-sectional view showing the method for manufacturing the electronic component according to the present embodiment following FIG. 8C. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 9A. It is sectional drawing which shows the manufacturing method of the electronic component by this embodiment following FIG. 9B. It is sectional drawing which shows the electronic component by the 1st modification of this embodiment. It is sectional drawing which shows the electronic component by the 2nd modification of this embodiment. It is sectional drawing which shows the electronic component by the 3rd modification of this embodiment. It is sectional drawing which shows the electronic component by the 4th modification of this embodiment. It is sectional drawing which shows the electronic component by the 5th modification of this embodiment. It is sectional drawing which shows the electronic component by the 6th modification of this embodiment. It is sectional drawing which shows the electronic component by the 7th modification of this embodiment. It is sectional drawing which shows the electronic component by the 8th modification of this embodiment. It is sectional drawing which shows the electronic component by the 9th modification of this embodiment. It is sectional drawing which shows an example of the electronic component by the 10th modification of this embodiment. It is sectional drawing which shows another example of the electronic component by the 10th modification of this embodiment.

  Hereinafter, an electronic component and a manufacturing method thereof according to an embodiment of the present disclosure will be described in detail with reference to the drawings. The following embodiments are examples of embodiments of the present disclosure, and the present disclosure is not construed as being limited to these embodiments. Further, in this specification, terms such as “substrate”, “base material”, “sheet”, and “film” are not distinguished from each other only based on the difference in names. For example, “substrate” and “base material” are concepts including members that can be called sheets and films. In addition, the length and angle values used in the present specification are not limited to strict meanings, and are interpreted to include a range where a similar function can be expected. In the drawings referred to in this embodiment, the same portions or portions having similar functions are denoted by the same reference symbols or similar reference symbols, and repeated description thereof may be omitted. In addition, the dimensional ratio in the drawing may be different from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

(Electronic component 1)
First, an embodiment of an electronic component of the present disclosure will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing an electronic component 1 according to the present embodiment. FIG. 2 is a plan view showing the electronic component 1 according to the present embodiment. FIG. 3 is an equivalent circuit diagram of the electronic component 1 according to the present embodiment. The electronic component 1 of the present embodiment can be suitably used for applications that require a relatively high-accuracy capacitance value, such as an analog high-frequency circuit used for broadband wireless communication.

  As shown in FIG. 1, the electronic component 1 of the present embodiment includes a substrate 2 that is an example of a base material, a first capacitor 3, a second capacitor 4, and a passivation layer 5. The substrate 2 is, for example, an insulating substrate or a semiconductor substrate. As shown in FIG. 3, the first capacitor 3 and the second capacitor 4 are connected in series. The first capacitor 3 and the second capacitor 4 are both thin film capacitors, that is, thin film capacitors.

  As shown in FIG. 1, the first capacitor 3 includes, in order, the first electrode 31 on the substrate 2, that is, the first surface 21, the first dielectric 32 on the first electrode 31, and the first dielectric 32. A second electrode 33. In the example of FIG. 1, the first electrode 31 is in direct contact with the first surface 21 of the substrate 2. Another film such as a silicon oxide film may be located between the first surface 21 of the substrate 2 and the first electrode 31.

  As shown in FIG. 1, the second capacitor 4 includes, in order, a second electrode 33, a second dielectric 41 on the second electrode 33, and a third electrode 42 on the second dielectric 41.

  The passivation layer 5 covers the edges of the electrodes 31, 33 and 42 and the dielectrics 32 and 41. On the other hand, the passivation layer 5 does not cover a region where wiring needs to be connected in order to apply a voltage to the capacitors 3 and 4. In the example of FIG. 1, the passivation layer 5 includes electrodes 31, 33, 42 and dielectrics 32, 41 so as to expose a partial region of the first electrode 31 and a central region of the third electrode 42. The edges are covered.

  Here, in the case of a thin film capacitor having a single layer structure in which a dielectric is sandwiched between a pair of electrodes, the capacitance between the electrodes is slightly deviated from the design because the dielectric thickness between the electrodes is thin and the capacitance density is high. However, there is a risk of deviating greatly from the design. Further, since the dielectric is thin, it is difficult to ensure a dielectric strength voltage with respect to a voltage applied between the electrodes.

  On the other hand, the electronic component 1 having the above-described configuration includes the first capacitor 3 and the second capacitor 4 that are connected in series, that is, the capacitors 3 and 4 having a multilayer structure. The reciprocal of the sum of the reciprocals of the respective capacitances 3 and 4, that is, the value obtained by dividing the product of the capacitances of the capacitors 3 and 4 by the sum of the capacitances of the capacitors 3 and 4.

  Thereby, compared with the capacitor of a single layer structure, the influence which each capacity | capacitance of each capacitor 3 and 4 has on the capacity | capacitance of the electronic component 1 whole can be relieved. As a result, even if the dimensions of the electrodes 31, 33, and 42 constituting the capacitors 3 and 4 are deviated from the design value, it is possible to suppress the capacitance value of the entire electronic component 1 from deviating greatly from the design value. In addition, since the applied voltage can be divided by each of the capacitors 3 and 4 connected in series, it is possible to suppress application of a large voltage to the individual capacitors 3 and 4. Thereby, ensuring of capacitance value accuracy and ensuring of voltage resistance can be made compatible.

  Also, in applications such as a stable bandpass filter, a highly accurate small-capacitance capacitor is required. If a single-layer capacitor dielectric is formed thick in order to obtain a small capacitance, There is a risk that the internal stress of the capacitor may be caused by an increase in compressive stress. On the other hand, according to the present embodiment, the first capacitor 3 and the second capacitor 4 are connected in series, thereby realizing a small capacity in the entire element while suppressing the thickness of the individual dielectrics 32 and 41. be able to. Thereby, the compressive stress of the dielectrics 32 and 41 and the internal breakdown of the capacitors 3 and 4 resulting from this can be suppressed, and reliability can be ensured.

(External shape of electrodes 31, 33, 42)
In addition to the above configuration, in the electronic component 1 of the present embodiment, as shown in FIG. 2, the outer shape of the second electrode 33 is included in the outer shape of the first electrode 31 in plan view, and the third The outer shape of the electrode 42 is included in the outer shape of the second electrode 33.

Here, the capacitance C [F] of the capacitor is expressed by the following equation.
C [F] = ε _r ε ₀ S [m ² ] / d [m] (1)
In Equation (1), ε _r is the dielectric constant of the dielectric, ε ₀ is the vacuum dielectric constant, S is the facing area between the electrodes, and d is the distance between the electrodes.

  According to the electronic component 1 of the present embodiment, since the outer shape of the second electrode 33 is included in the outer shape of the first electrode 31, there is a slight alignment error between the first electrode 31 and the second electrode 33. Even if it occurs, the facing area S between the first electrode 31 and the second electrode 33 can be maintained. Further, according to the electronic component 1 of the present embodiment, since the outer shape of the third electrode 42 is included in the outer shape of the second electrode 33, there is a slight alignment between the second electrode 33 and the third electrode 42. Even if an error occurs, the facing area S between the second electrode 33 and the third electrode 42 can be maintained. Since the facing area S can be maintained regardless of the alignment error, a stable capacitance value can be obtained.

(Thickness of electrodes 31, 33, 42)
In addition to the above configuration, in the electronic component 1 of the present embodiment, the thickness t ₂ of the second electrode 33 is thinner than the thickness t ₁ of the first electrode 31. The thickness _{t 2} of the second electrode is preferably not more than half of the thickness _{t 1} of the first electrode 31, more preferably 1/3 or less of the thickness _{t 1} of the first electrode 31. The thickness _{t 2} of the second electrode 33 is preferably a 0.3μm~ number [mu] m, more preferably 1 to 5 [mu] m. The thickness t ₂ of the second electrode may be larger than the thickness t _{3 of} the third electrode, or may be equal to or less than the thickness t ₃ of the third electrode 42.

Of the three electrodes 31, 33, 42, the lowermost first electrode 31 and the uppermost third electrode 42 serve both as the electrodes of the capacitors 33, 41 and as the wiring. There is. When functioning as wiring, the first electrode 31 and the third electrode 42 are required to pass a sufficient current in the plane direction D2 orthogonal to the thickness direction D1. In order to allow a sufficient current to flow in the surface direction D2, the first electrode 31 and the third electrode 42 are required to have a low electrical resistance value in the surface direction D2, that is, to have a certain thickness t ₁ , t _3. . Therefore, there is a certain limit in making the electrodes 31 and 42 thinner from the viewpoint of causing the first electrode 31 and the third electrode 42 to function as wiring.

On the other hand, the second electrode 33 between the first electrode 31 and the third electrode 42 hardly functions as a wiring. That is, the second electrode 33 hardly needs to reduce the electric resistance value in the surface direction D2 in order to pass a sufficient current in the surface direction D2. Thereby, the thickness t ₂ of the second electrode 33 can be made thinner than the thickness t ₁ of the first electrode 31. Therefore, according to the electronic component 1 of the present embodiment, by reducing the thickness t ₂ of the second electrode 33, without affecting the electrical characteristics of the electronic component 1, thickness of the electronic component 1 in a simple technique Can be realized, and the cost can be reduced. In addition, by reducing the thickness t ₂ of the second electrode 33, the capacitance between the side surface of the second electrode 33 and the first electrode 31, which is also called a fringe capacitance, can be reduced.

  As described above, according to the electronic component 1 of the present embodiment, it is possible to achieve all of ensuring the capacitance value accuracy, ensuring the voltage resistance, and suppressing the compressive stress.

(Production method)
Next, an example of a method for manufacturing the electronic component 1 of the present embodiment will be described with reference to FIGS. 4A to 9C.

  FIG. 4A is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment. First, as shown in FIG. 4A, a substrate 2 is prepared.

  FIG. 4B is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment subsequent to FIG. 4A. After the substrate 2 is prepared, a metal first seed layer 311 is formed on the substrate 2 as shown in FIG. 4B. The first seed layer 311 may be formed by a film forming method such as sputtering, vapor deposition, or electroless plating. The metal constituting the first seed layer 311 may be, for example, Ni, Cu, Ti, or Cr.

  FIG. 4C is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 4B. After the first seed layer 311 is formed, a resist 7 is applied on the first seed layer 311 as shown in FIG. 4C. Then, the resist 7 is patterned by a photolithography method or the like so that the first seed layer 311 within the range corresponding to the first electrode 31 is exposed.

  FIG. 4D is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 4C. After patterning the resist 7, as shown in FIG. 4D, a first metal layer 312 is formed on the first seed layer 311 by electrolytic plating. As a result, the first electrode 31 including the first seed layer 311 and the first metal layer 312 is formed. For example, the first metal layer 312 may be Cu.

  FIG. 4E is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 4D. After the first electrode 31 is formed, the resist 7 is removed as shown in FIG. 4E.

  FIG. 5A is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment subsequent to FIG. 4E. After removing the resist and removing the first seed layer 311 not covered with the first metal layer 312 by etching, the first electrode 31 and the substrate 2 are made of a metal such as Ti, Cr, Ni, etc., not shown. Form a layer. After forming the adhesion layer, a first dielectric 32 is formed on the first electrode 31 and the substrate 2 as shown in FIG. 5A. The formation of the first dielectric 32 may be performed, for example, by vapor deposition, sputtering, atomic layer deposition, or the like. Further, the first dielectric 32 may be an inorganic compound such as an inorganic oxide or an inorganic nitride, for example.

  FIG. 5B is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 5A. After forming the first dielectric 32, the resist 7 is patterned on the first dielectric 32 over a range corresponding to the second electrode 33, as shown in FIG. 5B.

  FIG. 5C is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 5B. After patterning the resist 7 on the first dielectric 32, as shown in FIG. 5C, unnecessary portions of the first dielectric 32 are removed using the resist 7 as a mask, and then the resist 7 is peeled off.

  FIG. 5D is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 5C. After removing unnecessary portions of the first dielectric 32, a second seed layer 331 is formed on the substrate 2, the first electrode 31, and the first dielectric 32 as shown in FIG. 5D. The formation method and material of the second seed layer 331 may be the same as those of the first seed layer 311.

  FIG. 6A is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 5D. After the second seed layer 331 is formed, a resist 7 is applied on the second seed layer 331 as shown in FIG. 6A. Then, the resist 7 is patterned by photolithography or the like so that the second seed layer 331 within the range corresponding to the second electrode 33 is exposed.

  FIG. 6B is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment subsequent to FIG. 6A. After patterning the resist 7, a second metal layer 332 is formed on the second seed layer 331 as shown in FIG. 6B. Thereby, the second electrode 33 including the second seed layer 331 and the second metal layer 332 is formed. The formation method and material of the second metal layer 332 may be the same as that of the first metal layer 312.

  FIG. 6C is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment subsequent to FIG. 6B. After forming the second electrode 33, the resist 7 is peeled off as shown in FIG. 6C.

  FIG. 7A is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 6C. After the resist 7 is removed, as shown in FIG. 7A, the entire upper surface of the substrate 2 is etched to remove unnecessary portions of the second seed layer 331 and reduce the thickness of the second electrode 33.

  FIG. 7B is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 7A. After the entire surface etching, a second dielectric 41 is formed on the substrate 2, the first electrode 31, the first dielectric 32 and the second electrode 33 as shown in FIG. 7B. The formation method and material of the second dielectric 41 may be the same as the first dielectric 32.

  FIG. 7C is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 7B. After the second dielectric 41 is formed, the resist 7 is patterned on the second dielectric 41 over a range corresponding to the third electrode 42, as shown in FIG. 7C.

  FIG. 7D is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 7C. After the resist 7 is patterned on the second dielectric 41, as shown in FIG. 7D, unnecessary portions of the second dielectric 41 are removed using the resist 7 as a mask, and then the resist 7 is peeled off.

  FIG. 8A is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 7D. After removing unnecessary portions of the second dielectric 41, a third seed is formed on the substrate 2, the first electrode 31, the first dielectric 32, the second electrode 33, and the second dielectric 41, as shown in FIG. 8A. Layer 421 is formed. The formation method and material of the third seed layer 421 may be the same as that of the first seed layer 311.

  FIG. 8B is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 8A. After the third seed layer 421 is formed, a resist 7 is applied on the third seed layer 421 as shown in FIG. 8B. Then, the resist 7 is patterned by photolithography or the like so that the third seed layer 421 in the range corresponding to the third electrode 42 is exposed.

  FIG. 8C is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 8B. After patterning the resist 7, a third metal layer 422 is formed on the third seed layer 421 as shown in FIG. 8C. As a result, the third electrode 42 including the third seed layer 421 and the third metal layer 422 is formed. The formation method and material of the third metal layer 422 may be the same as that of the first metal layer 312.

  FIG. 9A is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 8C. After the third electrode 42 is formed, the resist 7 is peeled off as shown in FIG. 9A. Then, unnecessary portions of the third seed layer 421 are removed by overall etching.

  FIG. 9B is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 9A. After removing unnecessary portions of the third seed layer 421, as shown in FIG. 9B, on the substrate 2, the first electrode 31, the first dielectric 32, the second electrode 33, the second dielectric 41, and the third electrode 42. Then, the passivation layer 5 is formed.

  FIG. 9C is a cross-sectional view illustrating the method for manufacturing the electronic component 1 according to the present embodiment following FIG. 9B. After forming the passivation layer 5, as shown in FIG. 9C, the passivation layer 5 is patterned so that the central portion of the third electrode 42 is exposed.

  According to the manufacturing method of this embodiment, the capacitance value accuracy, the withstand voltage, and the compressive stress are suppressed by the thin film process in which the electrodes 31, 33 and 42 and the dielectrics 32 and 41 are alternately stacked. The electronic component 1 that can be achieved in any way can be easily manufactured while ensuring a dimensional margin.

(First modification)
Next, a first modified example including an additional capacitor connected in series to the first capacitor 3 and the second capacitor 4 will be described. FIG. 10 is a cross-sectional view showing an electronic component 1 according to a first modification of the present embodiment.

  As shown in FIG. 10, the electronic component 1 of the first modified example is an example of the third capacitor 8, the fourth capacitor 9, and the first wiring in addition to the configuration of the electronic component 1 of FIG. A certain wiring 10 is provided. As shown in FIG. 10, the third capacitor 8 and the fourth capacitor 9 are located on the substrate 2 in the vicinity of the first capacitor 3, and are connected in series with each other in the thickness direction D1. The third capacitor 8 and the fourth capacitor 9 are also connected in series with the first capacitor 3 and the second capacitor 4 via the wiring 10. The third capacitor 8 and the fourth capacitor 9 are thin film capacitors like the first capacitor 3 and the second capacitor 4.

  As shown in FIG. 10, the third capacitor 8 includes, in order, a fourth electrode 81 on the substrate 2, a third dielectric 82 on the fourth electrode 81, and a fifth electrode 83 on the third dielectric 82. Have

  As shown in FIG. 10, the fourth capacitor 9 includes, in order, a fifth electrode 83, a fourth dielectric 91 on the fifth electrode 83, and a sixth electrode 92 on the fourth dielectric 91.

  The wiring 10 is located on the third electrode 42 and the sixth electrode 92. The wiring 10 is provided in contact with both the third electrode 42 and the sixth electrode 92. Since the wiring 10 is in contact with both the third electrode 42 and the sixth electrode 92, the first and second capacitors 3, 4 and the third and fourth capacitors 8, 9 are connected in series.

  The electronic component 1 of the first modification can be manufactured using the thin film process shown in FIGS. 4A to 9C. In the thin film process, the fourth electrode 81 can be simultaneously formed by the same method as the first electrode 31. Further, the third dielectric 82 can be simultaneously formed by the same method as the first dielectric 32. Further, the fifth electrode 83 can be simultaneously formed by the same method as the second dielectric 41. Further, the fourth dielectric 91 can be simultaneously formed by the same method as the second dielectric 41. Further, the sixth electrode 92 can be simultaneously formed by the same method as the third electrode 42. The wiring 10 can be formed by an electroless plating method or an electrolytic plating method after the third electrode 42 and the sixth electrode 92 are formed.

  The electronic component 1 of the first modified example includes the third and fourth capacitors 8 and 9 further connected in series to the first and second capacitors 3 and 4 connected in series, so that each capacitor 3, 4, The influence of each capacity of 8 and 9 on the capacity of the entire electronic component 1 can be further reduced as compared with the example of FIG. As a result, the displacement of the capacitance value of the entire electronic component 1 due to the dimensional error of the capacitors 3, 4, 8, 9 can be suppressed more effectively than the example of FIG. Further, since the applied voltage can be divided by each of the four capacitors 3, 4, 8, 9 connected in series, a large voltage is applied to each of the capacitors 3, 4, 8, 9. More effectively. Therefore, according to the electronic component 1 of the first modification, it is possible to effectively achieve both the capacitance value accuracy and the breakdown voltage.

  In addition to the above configuration, in the electronic component 1 of the first modification example, the outer shape of the fifth electrode 83 is included in the outer shape of the fourth electrode 81 and the outer shape of the sixth electrode 92 in plan view. The outer shape of the fifth electrode 83 is included.

  Since the outer shape of the fifth electrode 83 is included in the outer shape of the fourth electrode 81, even if a slight alignment error occurs between the fifth electrode 83 and the fourth electrode 81, The area facing the four electrodes 81 can be maintained. Further, since the outer shape of the sixth electrode 92 is included in the outer shape of the fifth electrode 83, even if a slight alignment error occurs between the fifth electrode 83 and the sixth electrode 92, the fifth electrode 83. And the facing area of the sixth electrode 92 can be maintained. Thereby, the electronic component 1 can obtain a stable capacitance value.

In addition to the above configuration, in the electronic component 1 of the first modification, the thickness t ₅ of the fifth electrode 83 is thinner than the thickness t ₄ of the fourth electrode 81. The thickness t ₄ of the fourth electrode 81 may be the same as the thickness t ₁ of the first electrode 31. Further, the thickness t ₅ of the fifth electrode 83 may be the same as the thickness t ₂ of the second electrode 33.

According to a first variant, by reducing the thickness t ₅ of the little fifth electrode 83 that also functions as a wiring, a simple technique without affecting the electrical characteristics of the electronic component 1 thin Can be realized, and the cost can be reduced.

(Second modification)
Next, a second modified example including an additional capacitor connected in parallel to the first capacitor 3 and the second capacitor 4 will be described. FIG. 11 is a cross-sectional view showing an electronic component 1 according to a second modification of the present embodiment.

  In the electronic component 1 according to the first modification, the third capacitor 8 and the fourth capacitor 9 connected in series to the third capacitor 8 are connected in series to the first capacitor 3 and the second capacitor 4 via the wiring 10. On the other hand, in the electronic component 1 of the second modified example, the third capacitor 8 and the fourth capacitor 9 are connected in parallel to the first capacitor 3 and the second capacitor 4.

  Specifically, as shown in FIG. 11, the electronic component 1 of the second modified example has a fourth electrode 81 on the first electrode 31 on the substrate 2 as compared to the electronic component 1 of the first modified example. It differs in that it is connected, and it is common in other points. The fourth electrode 81 may be the same electrode as the first electrode 31.

  The wiring 10 functions as a second wiring, and the first and second capacitors 3, 4 and the third capacitor 8 are provided between the first and fourth electrodes 31, 81 on the third and fifth electrodes 42, 83. Are connected in parallel. More specifically, in the example of FIG. 11, the wiring 10 is connected to the first and second capacitors 3, 4 between the first and fourth electrodes 31, 81 on the third and sixth electrodes 42, 92. And third and fourth capacitors 8 and 9 are connected in parallel.

  According to the second modification, the total capacity of the electronic component 1 is a parallel combination of the series combined capacity of the first capacitor 3 and the second capacitor 4 and the series combined capacity of the third capacitor 8 and the fourth capacitor 9. Since it becomes a capacity | capacitance, the capacity | capacitance of the electronic component 1 whole increases rather than the 1st modification.

  Further, by combining the second modified example with the first modified example, the third and fourth capacitors 8 and 9 connected in series with the first and second capacitors 3 and 4, and the first and second capacitors 3. 4 may be mixed with the third and fourth capacitors 8 and 9 connected in parallel. Thereby, a wide capacity value suitable for high-frequency communication can be obtained.

(Third Modification)
Next, a third modified example including an additional capacitor connected in parallel to the first capacitor 3 and the second capacitor 4 will be described. FIG. 12 is a cross-sectional view showing an electronic component 1 according to a third modification of the present embodiment.

  As shown in FIG. 12, the electronic component 1 of the third modified example is similar to the second modified example in that the fourth electrode 81 on the base material 2, the third dielectric 82 on the fourth electrode 81, The third capacitor 8 having the fifth electrode 83 on the third dielectric 82 is provided. On the other hand, the electronic component 1 of the third modified example is different from the electronic component 1 of the second modified example in that the fourth capacitor 9 is omitted. More specifically, in the third modification, the wiring 10 is provided so as to be in contact with both the third electrode 42 and the fifth electrode 83.

  In the electronic component 1 of the third modification, the formation of the fourth dielectric 91 is omitted when the second dielectric 41 is formed, and the sixth electrode 92 is formed when the third electrode 42 is formed. Can be obtained by omitting.

  In the third modification, no other capacitor that restricts the size of the third capacitor 8 is provided on the third capacitor 8. For this reason, in the third modification, the capacity of the third capacitor 8 can be made relatively large. Since the capacity of the third capacitor 8 can be made relatively large, even if a slight dimensional error of the electrode occurs in the third capacitor 8, it is possible to secure the electrode facing area and suppress the capacitance change.

  According to the third modification, the first capacitor 3 and the second capacitor 4 having relatively small capacities connected in series and the third capacitor 8 having a relatively large capacity connected in parallel thereto are combined. A capacitor having a wide range of capacitance values can be obtained.

(Fourth modification)
Next, a description will be given of a fourth modification inhibits the thickness t ₂ of the second electrode 33. FIG. 13 is a cross-sectional view showing an electronic component according to a fourth modification of the present embodiment. 4A to 9B, in the formation process of the second electrode 33, the second metal layer 332 is formed on the second seed layer 311 by electrolytic plating.

On the other hand, in the fourth modification, the second electrode 33 is formed only by the second seed layer 311. That is, in the fourth modification, the thickness of the second seed layer 311 is the thickness t ₂ of the second electrode 33. In this case, the thickness _{t 2} is, for example, 0. May be the number Myuemu～1myuemu.

  According to the fourth modification, since the formation of the second metal layer 332 can be omitted, the manufacturing time of the electronic component 1 can be shortened to improve the production efficiency, and the manufacturing cost can be reduced. Further, as compared with the case where the second metal layer 332 is formed, the steps formed at the respective edges of the second dielectric 41 and the third electrode 42 on the second electrode 33 can be reduced. Since the step can be reduced, it is possible to suppress the occurrence of a short circuit due to poor protection of the edges of the second dielectric 41 and the third electrode 42 by the passivation layer 5 and to improve the reliability. In addition, since the aspect ratio, which is the ratio of the thickness to the dimension in the surface direction D2 of the second electrode 33, can be reduced, the second electrode 33 can be patterned with high accuracy. Capacitance accuracy can be further improved by patterning the second electrode 33 with high accuracy.

  Note that when the formation of the second electrode 33 is completed, the capacitance value of the first capacitor 3 is measured by a probe or the like, and the first capacitor 3 and the second capacitor according to the measured capacitance value of the first capacitor 3. The shape and dimensions of the second dielectric 41 and the third electrode 42 may be corrected so that the combined capacitance with 4 has a desired value. Thereby, capacity accuracy can be further improved.

  The fourth modification can be combined with the fifth electrode 83 of the first modification. That is, the fifth electrode 83 can be configured only by the seed layer.

(Fifth modification)
Next, the 5th modification provided with the penetration electrode is explained. FIG. 14 is a cross-sectional view showing an electronic component 1 according to a fifth modification of the present embodiment.

  As shown in FIG. 14, the electronic component 1 of the fifth modified example further penetrates the substrate 2 in the thickness direction D1 in addition to the configuration of the electronic component 1 of FIG. A through electrode 11 connected to the electrode 31 is provided.

  The through electrode 11 in the example of FIG. 14 is a filled via type through electrode filled in a through hole 23 that penetrates the substrate 2 from the first surface 21 to the second surface 22. The through electrode 11 includes the first capacitor 3 via the land 11a covering the opening of the through hole 23 on the first surface 21 side and the peripheral edge thereof, and the first electrode 31 connected to the land 11a in the plane direction D2. The second capacitor 4 is connected.

  According to the fifth modification, the provision of the through electrode 11 can increase variations in the connection method between the capacitors 3 and 4 and other passive elements or active elements, thereby improving the degree of freedom in design. Can do.

(Sixth Modification)
Next, a sixth modification having an inductor will be described. FIG. 15 is a cross-sectional view showing an electronic component 1 according to a sixth modification of the present embodiment.

  As shown in FIG. 15, the electronic component 1 of the sixth modified example further connects the first inductor 12, the first inductor 12, and the third electrode 42 in addition to the configuration of the electronic component 1 of FIG. 1. Wiring 13 to be used.

  As shown in FIG. 15, the first inductor 12 includes a first through electrode 121 that penetrates the substrate 2 in the thickness direction D1 and is connected to the third electrode 42 on the first surface 21 via the wiring 13. The conductive layer 122 connected to the first through electrode 121 on the second surface 22 and the conductive layer 122 connected to the conductive layer 122 on the second surface 22 and penetrates the substrate 2 in the thickness direction D1 at a position different from the first through electrode 121. A second through electrode 123.

  Since the electronic component 1 according to the sixth modification can form an LC resonance circuit including the first capacitor 3, the second capacitor 4, and the first inductor 12, it can be more suitably applied to, for example, wireless communication. In addition, an inductor that tends to be relatively large can be made compact by the through electrodes 121 and 122. In addition, by not directly connecting the first electrode 31 and the first inductor 12, inductive coupling between the first inductor 12 and the first electrode 31 can be suppressed. By suppressing inductive coupling, it is possible to prevent the electronic component 1 from having unintended electrical characteristics particularly in a high frequency band.

(Seventh Modification)
Next, a seventh modification having an inductor will be described. FIG. 16 is a cross-sectional view showing an electronic component 1 according to a seventh modification of the present embodiment.

  As shown in FIG. 16, the electronic component 1 of the seventh modified example further connects the second inductor 14, the second inductor 14, and the first electrode 31 in addition to the configuration of the electronic component 1 of FIG. 1. Wiring 15 to be used.

  As shown in FIG. 16, the second inductor 14 includes a first through electrode 141 that penetrates the substrate 2 in the thickness direction D1 and is connected to the first electrode 31 on the first surface 21 through the wiring 15. The conductive layer 142 connected to the first through electrode 141 on the second surface 22 and the conductive layer 142 connected to the conductive layer 142 on the second surface 22 and penetrates the substrate 2 in the thickness direction D1 at a position different from the first through electrode 141. A second through electrode 143.

  Similarly to the electronic component 1 of the sixth modification, the electronic component 1 of the seventh modification can constitute an LC resonance circuit including the first capacitor 3, the second capacitor 4, and the second inductor 14. The electronic component 1 of the seventh modification can shorten the wiring length between the inductor 14 and the capacitors 3 and 4 as compared with the electronic component 1 of the sixth modification. Since the wiring length can be shortened, the loss can be reduced and the quality factor, that is, the Q value can be increased.

(Eighth modification)
Next, an eighth modification having a through electrode will be described. FIG. 17 is a cross-sectional view showing an electronic component 1 according to an eighth modification of the present embodiment.

  As shown in FIG. 17, the electronic component 1 of the eighth modified example includes a through electrode 11 that penetrates the substrate 2 in the thickness direction D1 and is connected to the first electrode 31 on the first surface 21. Common to the electronic component 1 of the fifth modification. On the other hand, the electronic component 1 of the eighth modified example is different from the electronic component 1 of the fifth modified example in that the through electrode 11 is directly connected to the first electrode 31 in the thickness direction D1 without the land 11a. To do. In other words, in the eighth modified example, the first capacitor 3 and the second capacitor 4 are located immediately above the through electrode 11. In other words, in the eighth modification, the first electrode 31 also serves as the land 11a of the through electrode 11.

  According to the eighth modification, since the wiring length in the surface direction D2 between the through electrode 11 and the capacitors 3 and 4 can be made zero, the parasitic resistance and the parasitic inductance of the capacitors 3 and 4 are effectively reduced. Can be reduced.

(Ninth Modification)
Next, a ninth modification including an inductor will be described. FIG. 18 is a cross-sectional view showing an electronic component 1 according to a ninth modification of the present embodiment.

  As shown in FIG. 18, the electronic component 1 of the ninth modified example further includes a third inductor 16 in addition to the configuration of the electronic component 1 of FIG. 1.

  As shown in FIG. 18, the third inductor 16 penetrates the substrate 2 in the thickness direction D <b> 1 and is connected to the first electrode 31 at one end on the first surface 21 side, and the second surface 22. The conductive layer 162 connected to the other end of the first through electrode 161 on the upper side, and connected to the conductive layer 162 on the second surface 22, and penetrates the substrate 2 in the thickness direction D1 at a position different from the first through electrode 161. A second through electrode 163.

  According to the electronic component 1 of the ninth modification, the wiring length in the plane direction D2 between the inductor 16 and the capacitors 3 and 4 can be made zero compared to the seventh modification. It is possible to prevent an unintended inductance from occurring between the capacitor 16 and the capacitors 3 and 4. Thereby, the electronic component 1 can be formed with high accuracy.

(10th modification)
Next, a tenth modified example provided with a conformal via type through electrode will be described. FIG. 19 is a cross-sectional view showing an example of an electronic component 1 according to a tenth modification of the present embodiment. FIG. 20 is a cross-sectional view showing another example of an electronic component according to the tenth modification of the present embodiment.

  Until now, the example of the electronic component 1 provided with the filled via type through electrode alone or as a part of the inductor has been described. The through electrode in the present disclosure is not limited to a filled via type through electrode.

  For example, as shown in FIG. 19, the first through electrode 141 and the second through electrode 143 constituting the second inductor 14 described in the seventh modification are used as conformal via type through electrodes having a hollow portion. Also good. In the example of FIG. 19, the inside of the first through electrode 141 and the second through electrode 143 is a gap 145. The passivation layer 5 corresponding to the gap 145 in the thickness direction D1 is provided with a through hole 51 in the thickness direction D1.

  Further, as shown in FIG. 20, the resin layer 146 may be filled into the conformal via type first through electrode 141 and second through electrode 143.

  In addition, you may combine these suitably for each modification mentioned above.

  Moreover, the specific usage aspect of the electronic component 1 of this indication is not specifically limited. For example, the electronic component 1 may be incorporated in an interposer substrate that relays a baseband IC and a power amplifier IC of a wireless communication module, or may be mounted on an existing substrate, or packaged itself. An electronic component may be configured.

  The aspects of the present disclosure are not limited to the individual embodiments described above, and include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. That is, various additions, changes, and partial deletions can be made without departing from the concept and spirit of the present disclosure derived from the contents defined in the claims and equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Electronic component 2 Board | substrate 3 1st capacitor 31 1st electrode 32 1st dielectric material 33 2nd electrode 4 2nd capacitor 41 2nd dielectric material 42 3rd electrode

Claims (8)

A substrate;
A first capacitor having a first electrode on the substrate, a first dielectric on the first electrode, and a second electrode on the first dielectric;
An electronic component comprising: a second capacitor connected in series to the first capacitor and having the second electrode, a second dielectric on the second electrode, and a third electrode on the second dielectric.   2. The electronic component according to claim 1, wherein, in a plan view, the outer shape of the second electrode is included in the outer shape of the first electrode, and the outer shape of the third electrode is included in the outer shape of the second electrode.   The electronic component according to claim 1, wherein a thickness of the second electrode is thinner than a thickness of the first electrode.   4. The third capacitor according to claim 1, further comprising a third capacitor having a fourth electrode on the substrate, a third dielectric on the fourth electrode, and a fifth electrode on the third dielectric. 5. The electronic component described.   The electronic component according to claim 4, further comprising a first wiring that connects the second capacitor and the third capacitor in series on the third and fifth electrodes. The fourth electrode is connected to the first electrode on the substrate;
The electronic component further includes a second wiring that connects the first and second capacitors and the third capacitor in parallel between the first and fourth electrodes on the third and fifth electrodes. 4. The electronic component according to 4.   The electronic component according to claim 1, further comprising a through electrode connected to the first and second capacitors and penetrating the base material. Forming a first capacitor comprising: forming a first electrode on a substrate; forming a first dielectric on the first electrode; and forming a second electrode on the first dielectric; ,
Forming a second capacitor connected in series to the first capacitor, comprising: forming a second dielectric on the second electrode; and forming a third electrode on the second dielectric. Manufacturing method for electronic parts.

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