JP2008251885A - Multilayer thin film capacitor and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To downsize a multilayer thin-film capacitor and upsize its area without causing ESL to be increased. <P>SOLUTION: A micro-lens array 2A is formed in an SiO<SB>2</SB>insulating film 2a on an Si substrate 1a, on which a lower Pt electrode 4a, a lower BST film 5a, an intermediate Pt electrode 6a, an upper BST film 7a, and an upper Pt electrode 8a are deposited in sequence, thus forming a capacitor. A power supply part 21a is formed on it, which is connected to respective electrodes through an SiO<SB>2</SB>insulating film 13a. The electrode layers and dielectric layers both become almost analogous to a micro-lens array shape of the SiO<SB>2</SB>insulating film 2a, and the capacitance of the capacitor increases without changing the occupied area. On condition of the same capacitance, the occupied area is reduced, and an increase of ELS can also be controlled. This ESL controlling effect is greater in a multilayer thin film capacitor than in a unilayer thin film capacitor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multilayer thin film capacitor and a method for manufacturing the same, and more particularly to an improvement for increasing the capacity thereof.

In order to meet the demands for miniaturization, light weight, and high performance of electric products, the density of component mounting has been increasing, and miniaturization of various electronic components has been demanded. Multilayer thin film capacitors have a structure consisting of, for example, a substrate / insulating film / lower electrode / dielectric thin film layer / intermediate electrode / upper dielectric thin film layer / upper electrode, but are similarly required to be miniaturized. At the same time, a large capacity, high withstand voltage, and low ESL (equivalent series inductance) are also desired. For example, when attention is focused on increasing the capacity, the basic methods include increasing the area, reducing the thickness of the dielectric film, and increasing the relative dielectric constant of the dielectric. However, increasing the area is contrary to miniaturization of components, and reducing the thickness of the dielectric film lowers the breakdown voltage. In addition, the increase in the dielectric constant of the dielectric is limited by the material, and the current dielectric constant of a material such as BST (barium strontium titanate, (Ba, Sr) TiO ₃ ) is the maximum value. It is technically difficult to increase further.

Under these circumstances, the thin film capacitor and its manufacturing method described in the following Patent Document 1 and the following Patent Document 2 are described as means for realizing the miniaturization, large capacity, and high breakdown voltage of the thin film capacitor. There are also cathode materials for electrolytic capacitors. These are methods for increasing the capacity by forming curved irregularities on the substrate to increase the surface area. Furthermore, the “dielectric thin film capacitor manufacturing method” described in the following Patent Document 3 is a method in which a jagged shape is formed on a substrate to similarly increase the capacity.
JP-A-8-148379 JP-A-5-13282 JP 2000-31387 A

  However, in the conventional thin film capacitor described above, the capacity can be increased in the case of a single layer capacitor of electrode film / dielectric thin film / electrode film, but there is a problem that ESL increases as the area increases.

  The present invention focuses on the above points, and an object of the present invention is to reduce the size and area of a capacitor without increasing the ESL.

  In order to achieve the above object, the present invention provides a method of manufacturing a multilayer thin film capacitor in which thin film dielectrics and electrodes are alternately stacked on a substrate, the step of forming a curved surface shape on the substrate, the curved surface shape A step of alternately laminating the dielectric and electrode thin films on the substrate on which is formed. Another invention is a multilayer thin film capacitor in which thin film dielectrics and electrodes are alternately laminated on a substrate, wherein a curved shape is formed on the substrate, and the curved shape is formed on the substrate on which the curved shape is formed. It has a laminated structure in which thin films of dielectrics and electrodes are alternately formed. One of the main forms is characterized in that the curved surface shape is one or both of a convex shape and a concave shape. One of the other forms is characterized in that the main surface of the substrate is a combination of the curved surface shape and the planar shape. The above and other objects, features and advantages of the present invention will become apparent from the following detailed description and the accompanying drawings.

  According to the present invention, since the substrate has a curved portion, the laminated structure of the dielectric and the electrode also has a curved shape, the area as a capacitor increases, and the capacitance increases. As a result, under the condition of the same capacity, the occupied area can be reduced and an increase in ELS can also be suppressed. In addition, the ESL suppression effect is greater in the multilayer thin film capacitor than in the single layer thin film capacitor.

  Hereinafter, the best mode for carrying out the present invention will be described in detail based on examples.

First, Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1A shows a main cross section of the multilayer thin film capacitor of this example. In this example, the present invention is applied to a multilayer thin film capacitor having two dielectric layers. An SiO ₂ insulating film 2a is formed on the Si substrate 1a. A microlens array 2A having a hemispherical lens shape is formed on the SiO ₂ insulating film 2a. FIG. 1B shows a perspective view of the microlens array 2A on the SiO ₂ insulating film 2a.

On the SiO ₂ insulating film 2a, a lower Pt electrode 4a, a lower BST film 5a, an intermediate Pt electrode 6a, an upper BST film 7a, and an upper Pt electrode 8a are further formed in this order, and a capacitor is formed by these laminated structures. The On top of that, a power feeding portion 21a connected to each electrode through the SiO ₂ insulating film 13a is formed. Details will be described later.

Thus, since the capacitor is laminated on the SiO ₂ insulating film 2a on which the microlens array 2A is formed, the electrode layer and the dielectric layer are almost the same as the microlens array shape of the SiO ₂ insulating film 2a. It will be similar. Thereby, the area as a capacitor can be increased without changing the occupation area of the multilayer thin film capacitor.

  Next, an example of a manufacturing process of the multilayer thin film capacitor of the embodiment will be described with reference to FIGS.

<Laminated MIM formation>
First, the laminated MIM formation process will be described with reference to FIGS. An SiO ₂ insulating film 2a having a thickness of, for example, 10 μm is formed on the Si substrate 1a by a CVD method (see FIG. 3A). Next, a resist is applied on the SiO ₂ insulating film 2a, and a pattern is formed using a microlens forming mask (not shown). A large number of hemispherical resist arrays 3a are formed, and post-annealing at 100 ° C., UV irradiation, and drying at 250 ° C. are performed (see FIG. 3B). Next, a hemispherical microlens array 2A having a diameter of 5 μm, for example, is formed on the surface of the SiO ₂ insulating film 2a using the resist array 3a as a mask (see FIG. 3C).

  Next, the continuous Pt electrode 4a, the lower BST film 5a, the intermediate Pt electrode 6a, the upper BST film 7a, and the upper Pt electrode 8a are sequentially formed in the same chamber (see FIG. 3D). The thickness of each layer at this time is, for example, lower Pt electrode 4a: 150 nm, lower BST film 5a: 250 nm, intermediate Pt electrode 6a: 150 nm, upper BST film 7a: 250 nm, and upper Pt electrode 8a: 150 nm. Thereafter, annealing is performed at 650 ° C. Next, a 1.5 μm-thick resist 9a patterned for forming the multilayer thin film capacitor is formed on the upper Pt electrode 8a (see FIG. 3E).

Next, RIE (Reactive Ion Etching) is performed using the resist 9a as a mask and BCl ₃ gas as a process gas, and a lower Pt electrode 4a, a lower BST film 5a, an intermediate Pt electrode 6a, and an upper BST film 7a on the wafer. The upper Pt electrode 8a is separated into quadrangles each having a size corresponding to each multilayer thin film capacitor (see FIG. 4A). At this time, the RIE is performed under the condition that the underlying SiO ₂ insulating film 2a is not etched as much as possible. After this step, the resist 9a is peeled and removed by an ashing step mainly including oxygen gas and a wet cleaning step (see FIG. 4B). Next, in order to form a contact hole for the lower Pt electrode 4a, a resist 10a having a film thickness of 1.5 μm is patterned so that a part of the rectangular multilayer thin film capacitor is exposed (see FIG. 4C).

Thereafter, using the resist 10a as a mask, RIE is performed using BCl ₃ gas as a process gas, and the lower BST film 5a, intermediate Pt electrode 6a, upper BST film 7a, and upper Pt electrode 8a are etched (FIG. 4D). reference). At this time, etching is stopped at the lower Pt electrode 4a by observing light emission during BST-RIE. At this time, similarly, RIE is performed under the condition that the underlying SiO ₂ insulating film 2a is not etched as much as possible.

Next, the resist 10a is peeled and removed by an ashing process and a wet cleaning process mainly composed of oxygen gas (see FIG. 5A). Then, for example, a resist 11a having a film thickness of 1.5 μm is formed by patterning to form a contact hole for the intermediate Pt electrode 6a (see FIG. 5B). Next, using this resist 11a as a mask, RIE is performed using BCl ₃ gas as a process gas, and the upper BST film 7a and the upper Pt electrode 8a are etched (see FIG. 5C). In this case as well, the etching is stopped at the intermediate Pt electrode 6a by observing the light emission during the BST-RIE. Thereafter, the resist 11a is peeled and removed by an ashing process mainly including oxygen gas and a wet cleaning process (see FIG. 5D).

<Contact via formation of laminated MIM>
Next, the contact via forming process of the laminated MIM will be described. For example, an Al ₂ O ₃ film 12a having a thickness of 150 nm is formed by sputtering on the main surface (see FIG. 6A), and a 3 μm thick SiO ₂ insulating film 13a is further formed thereon by a CVD method. (See FIG. 6B). Next, a 4 μm-thick resist 14a to which the contact hole pattern is transferred is formed on the SiO ₂ insulating film 13a (see FIG. 6C). Then, using this resist 14a as a mask, the SiO ₂ insulating film 13a is etched by RIE using C ₄ F ₈ / O ₂ / Ar gas, and then the Al ₂ O ₃ film 12a is etched by RIE using BCl ₃ gas. (See FIG. 6D). As a result, a contact hole 14A is formed as shown in FIG.

Next, the resist 14a is peeled and removed by an oxygen gas-based ashing process and a wet cleaning process (see FIG. 7A). Next, for example, a Ta barrier film with a thickness of 50 nm / a Cu seed layer 15a with a thickness of 100 nm are formed by sputtering. At this time, a Ta barrier film / Cu seed layer 15a is formed not only on the wafer surface but also on the entire surface of the contact hole 14A (see FIG. 7B). Further, electrolytic Cu plating is performed to fill the entire inside of the contact hole 14A with a Cu plating film 16a (see FIG. 7C). Next, the Cu plating film 16a and the Ta barrier film / Cu seed layer 15a on the upper surface of the SiO ₂ insulating film 13a are removed by a CMP process (see FIG. 8A). As a result, Cu vias (Via) 16A are formed, which serve as contacts for supplying power to the multilayer thin film capacitor electrode portion.

<Formation of feeding part>
Next, a process of forming a power feeding part to the multilayer thin film capacitor electrode part will be described. For example, a 200 nm thick SiN insulating film 17a is formed on the main surface by plasma CVD (see FIG. 8B). Then, a resist 18a having a thickness of 1.5 μm is formed thereon by a spin coating method, and a contact via hole pattern is transferred (see FIG. 8C). Next, using this resist 18a as a mask, the SiN insulating film 17a is etched by RIE using C ₄ F ₈ / O ₂ / Ar gas (see FIG. 9A). Next, the resist 18a is removed by a wet process (see FIG. 9B). Thereafter, plating is performed in the order of Ni 19a and Au 20a to form a power feeding portion 21a (see FIG. 9C).

Next, the simulation results of the characteristics of the multilayer thin film capacitor having the microlens array structure of this embodiment and the planar multilayer thin film capacitor are compared. In contrast to the present embodiment shown in FIG. 1A, a planar multilayer thin film capacitor is as shown in FIG. The same number is used for the corresponding elements of both, and “a” is attached to this embodiment, and “b” is attached to the related art. A lower Pt electrode 4b, a lower BST film 5b, an intermediate Pt electrode 6b, an upper BST film 7b, and an upper Pt electrode 8b are sequentially formed on the SiO ₂ insulating film 2b on the Si substrate 1b. It is formed. On top of this, a power feeding portion 21b connected to each electrode through the SiO ₂ insulating film 13b is formed.

  FIG. 2A is a graph showing a comparison of the capacitance of a capacitor formed on a flat substrate according to this embodiment and the prior art. As shown in the figure, the capacitance of this embodiment is twice as large as that of the prior art. FIG. 2B is a graph showing a comparison of both ESLs. As shown in the figure, the ESL of this example can be suppressed to 1.5 times that of the prior art. This is because the capacitor is formed on the concavo-convex substrate, so that the Pt electrode also has an concavo-convex shape, and the magnetic field at the Pt electrode is offset, contributing to the suppression of ESL.

  Judging from the overall effect on the multilayer thin film capacitor characteristics of the above comparison results of capacitance and ESL, the capacitance increased by a factor of 2, whereas the increase in ESL was about 1.5 times. If so, the present embodiment can reduce the occupied area and can suppress the increase in ELS. Furthermore, the ESL suppression effect is greater in the multilayer thin film capacitor than in the single layer thin film capacitor.

Next, Embodiment 2 of the present invention will be described with reference to FIG. In the first embodiment described above, the microlens array 2A is formed on the SiO ₂ insulating film 2a. However, in the embodiment shown in FIG. 10A, a cylindrical cylindrical lens array 2AC is formed instead of the microlens array 2A. This is an example. The cross section viewed in the direction of the arrow along the line # 10- # 10 in the same figure is the same as FIG.

FIG. 5B shows an example in which a microlens array 2AM in the reverse direction is formed between the microlens arrays 2A of the first embodiment. The main surface of the SiO ₂ insulating film 2a is shown in FIG. According to this example, the area as a capacitor is further increased as compared with the first embodiment. Further, since the multilayer thin film capacitor has a smooth curved surface, the concentration of the electric field in the acute angle portion is reduced. In the case of the scratch structure of Patent Document 3 described above, in order to double the capacitance, the shape of the top of the scratch corresponds to an acute angle of 60 °, electric field concentration occurs near the top, and the breakdown voltage is at least 10% or more. Will decline. Thus, according to the present embodiment, it is possible to increase the capacitor capacity without causing a decrease in the breakdown voltage. In the embodiment of FIG. 10A described above, if a cylindrical lens array in the reverse direction is formed between the cylindrical lens arrays 2AC as in this example, the capacitor capacity and the breakdown voltage are similarly improved. be able to.

Next, Embodiment 3 of the present invention will be described with reference to FIGS. In each of the above-described embodiments, a concave / convex curved surface such as a microlens array is formed on the SiO ₂ insulating film 2a on the flat Si substrate 1a. In this embodiment, the concave / convex curved surface is formed on the Si substrate 1a. It is an example. FIG. 11A differs from the above-described embodiment of FIG. 1 in that the microlens array 1X is formed on the Si substrate 1a. The microlens array 1X can be formed by applying a resist on the Si substrate 1a and then performing etching with a Cl ₂ / O ₂ gas. A 3 μm thick SiO ₂ insulating film 2a is formed thereon, for example, by CVD. The state after film formation is as shown in FIG. The subsequent steps are the same as in the first embodiment.

FIG. 12A shows an example in which the cylindrical lens array 1Y is formed on the Si substrate 1a in FIG. FIG. 12B shows an example in which a convex microlens array 1Z and a concave microlens array 1ZM are formed on the Si substrate 1a in FIG. 10B. The portions of the Si substrate 1a and the SiO ₂ insulating film 2a are as shown in FIG.

In addition, this invention is not limited to the Example mentioned above, A various change can be added in the range which does not deviate from the summary of this invention. For example, the following are also included.
(1) In the above embodiment, the lower Pt electrode 4a is laminated on the SiO ₂ insulating film 2a of the Si substrate 1a. However, a TiOx film or the like is inserted between the SiO ₂ insulating film 2a and the lower Pt electrode 4a. Thus, the adhesion may be improved.
(2) The materials shown in the above embodiments are examples, and may be changed as appropriate. For example, a conductive metal oxide such as IrO ₂ , RuO ₂ , SrRuO ₃ , or LaNiO ₃ may be used as the electrode material in place of Pt instead of a metal such as Ru, Ir, Ag, Pd, Ni, or Cu. In addition to the dielectric material BST, a dielectric material such as STO, TaxOy, BaTiO ₃ , PbZrTiO ₃ (PZT), or an insulating material such as Al ₂ O ₃ or SiO _{2 is used} as the aggregate. Ceramics or the like may be used, or TiN, TaN, TixOy, TaxOy, or the like may be used instead of the Al ₂ O ₃ film of the MIM portion protective film. Further, TaN, TaSiN, TiSiN or the like may be used instead of Ta as a barrier film for the Cu-plated film.
(3) Various known techniques may be similarly applied to the film thickness of each part, the film forming method, and the processing method. For example, with respect to the film formation method, methods such as a sputtering method, a vapor deposition method, a CVD method, and a spin coating method can be cited. The surface shape may be a quadrangle, a circle, or the like, and the number of thin film capacitors stacked is not limited to the case where the dielectric is two layers, but may be three or more layers.
(4) The concave and convex shapes of the microlens array and cylindrical lens array shown in the above embodiments need not be completely spherical or cylindrical. Various shapes such as a spherical shape and a spindle shape may be combined.
(5) In the above embodiment, Si is used as the substrate, but an insulating substrate such as Al ₂ O ₃ , SiO ₂ , SiC may be used.

  According to the present invention, it is possible to increase the capacity of a multilayer thin film capacitor without causing an increase in ESL. Therefore, peripheral circuits of RF (high frequency) modules such as Bluetooth (registered trademark) and wireless LAN, RF -Suitable for MEMS (Micro Electro Mechanical Systems) and the like.

(A) is a principal sectional view of the multilayer thin film capacitor of Example 1 of the present invention, (B) is a perspective view showing the shape of the substrate surface, (C) is a principal sectional view of the multilayer thin film capacitor of the prior art. . In the graph which compares the characteristic of the said Example and a prior art, (A) shows a capacitance and (B) shows ESL. It is a figure which shows the manufacturing process of the said Example 1. FIG. It is a figure which shows the manufacturing process of the said Example 1. FIG. It is a figure which shows the manufacturing process of the said Example 1. FIG. It is a figure which shows the manufacturing process of the said Example 1. FIG. It is a figure which shows the manufacturing process of the said Example 1. FIG. It is a figure which shows the manufacturing process of the said Example 1. FIG. It is a figure which shows the manufacturing process of the said Example 1. FIG. It is a figure which shows Example 2 of this invention. It is a figure which shows Example 3 of this invention. It is a figure which shows Example 3 of this invention.

Explanation of symbols

1a: Si substrate 2a: SiO ₂ insulating film 1X, 1Z, 1ZM, 2A, 2AM: microlens array 1Y, 2AC: cylindrical lens array 3a: resist array 4a: lower Pt electrode 5a: lower BST film 6a: intermediate Pt electrode 7a : upper BST film 8a: upper Pt electrode 9a: resist 10a: resist 11a: resist 12a: _Al 2 _{O 3} film 13a: SiO ₂ insulating film 14a: resist 14A: contact hole 15a: Ta barrier film / Cu seed layer 16a: Cu Plating film 16A: Cu via 17a: SiN insulating film 18a: Resist 19a: Ni
20a: Au
21a: Power feeding unit

Claims (6)

A method of manufacturing a multilayer thin film capacitor in which thin film dielectrics and electrodes are alternately stacked on a substrate,
Forming a curved surface shape on the substrate;
A step of alternately laminating the dielectric and the electrode thin film on the substrate on which the curved surface shape is formed;
A method for producing a multilayer thin film capacitor, comprising:   2. The method of manufacturing a multilayer thin film capacitor according to claim 1, wherein the curved surface shape is one or both of a convex shape and a concave shape.   3. The method of manufacturing a multilayer thin film capacitor according to claim 2, wherein the main surface of the substrate has a shape obtained by combining the curved surface shape and the planar shape. A thin film capacitor in which thin film dielectrics and electrodes are alternately stacked on a substrate,
A multilayer thin film capacitor comprising a multilayer structure in which a curved surface is formed on the substrate, and the dielectric and electrode thin films are alternately formed on the curved surface.   5. The multilayer thin film capacitor according to claim 4, wherein the curved surface shape is one or both of a convex shape and a concave shape.   6. The multilayer thin film capacitor according to claim 5, wherein a main surface of the substrate has a shape obtained by combining the curved surface shape and a planar shape.

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