JP2008078278A - Capacitor part, its manufacturing method, and capacitor built-in board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor part which is capable of restraining a gap between a contact area of a dielectric layer with an upper electrode and its designed value so as to acquire a desired static capacitance and being easily built in a printed-circuit board through a laser via process even if a small capacitance is set. <P>SOLUTION: A printed-circuit board comprises a board 10a, a lower electrode 14 formed on the board 10a, a dielectric layer 16 which is patterned and formed on the lower electrode 14, a protective insulating layer 20 which is formed from inside to outside of the dielectric layer 16 and equipped with an opening 20x in the region of the dielectric layer 16, and an upper electrode 18 formed spreading from the opening 20x to the upper surface of the protective insulating layer 20. A contact area between the dielectric layer 16 and the upper electrode 18 is demarcated by the opening 20x of the protective insulating layer 20. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a capacitor component, a method of manufacturing the same, and a substrate with a built-in capacitor. More specifically, the present invention relates to a wiring board in which a lower electrode, a dielectric layer and an upper electrode are formed on a substrate and embedded in an insulating layer. The present invention relates to a capacitor component that can be easily built in, a manufacturing method thereof, and a capacitor built-in substrate.

  2. Description of the Related Art Conventionally, there is a capacitor component formed by sequentially forming a lower electrode made of a thin film, a dielectric layer, and an upper electrode on a substrate. In recent years, a technique for incorporating such capacitor components in a wiring board in a state of being embedded in an insulating layer has been reported.

  In Patent Document 1, a passivation film covering a connection terminal of an electronic component such as a capacitor is formed on the entire surface, and the electronic component is embedded in an insulating layer of a wiring board and mounted on the insulating layer and the passivation film. A method for exposing a connection terminal by forming a via hole is described.

  Patent Document 2 describes that a capacitor device formed by integrating a plurality of capacitors having different capacitances on a substrate into one chip is embedded in a wiring substrate in a state of being embedded with an insulating film. .

Further, in Patent Document 3, a capacitor provided with a penetrating opening is formed on a wiring board, the opening is buried with an insulating layer, and a via hole penetrating the insulating layer in the opening is formed. A method of forming wiring is described.
JP 2005-327984 A JP 2005-191266 A JP 2006-173494 A

  Incidentally, some conventional capacitor parts are configured such that the entire upper electrode is disposed in contact with the pattern region of the dielectric layer formed on the lower electrode. In the capacitor component, the contact area between the dielectric layer and the upper electrode is one of the factors that determine the capacitance of the capacitor component. However, since an etching shift occurs when the upper electrode is formed, the contact area between the dielectric layer and the upper electrode becomes smaller than the design value, and accordingly, the capacitance of the capacitor component is smaller than the design value. There is a problem that becomes smaller.

  Further, as described in Patent Document 2, when the capacitor component is built in the wiring board, the capacitor component is covered with an insulating layer, and then the insulating layer is processed with a laser to thereby form an upper electrode of the capacitor component and It is necessary to form a via hole connected to the lower electrode. However, when designing a capacitor component having a relatively small capacitance, the area of the upper electrode may be smaller than the beam diameter of the laser, making it difficult to use the laser via process when incorporating the capacitor component in the wiring board. become.

  The present invention was created in view of the above problems, and a deviation from the design value of the contact area between the dielectric layer and the upper electrode is suppressed to obtain a desired capacitance. It is an object of the present invention to provide a capacitor component that can be easily incorporated into a wiring board using a laser via process, a manufacturing method thereof, and a capacitor-embedded board even when set to be small.

  In order to solve the above-described problems, the present invention relates to a capacitor component, and relates to a substrate, a lower electrode formed on the substrate, and a dielectric formed by being electrically coupled to the lower electrode and patterned. A first insulating layer formed on the dielectric layer and having a first opening in a pattern region of the dielectric layer; and electrically coupled to the dielectric layer, An upper electrode formed from the inside of the opening to the upper surface of the protective insulating layer, and a contact area between the dielectric layer and the upper electrode is defined by the first opening of the protective insulating layer. Features.

  In the present invention, a lower electrode is formed on a substrate (silicon, resin, etc.), and a dielectric layer electrically coupled to the lower electrode is formed by patterning. The dielectric layer may be formed by anodizing the valve metal layer, or may be patterned after various dielectric layers are formed on the lower electrode. Further, a protective insulating layer (polyimide resin or the like) having a first opening is formed in the pattern region of the dielectric layer, and an upper electrode is formed from the first opening to the upper surface of the protective insulating layer. That is, the contact area between the dielectric layer and the upper electrode is defined by the first opening of the protective insulating layer.

  For this reason, for example, when the upper electrode is formed by the semi-additive method, the pattern edge of the upper electrode is disposed on the protective insulating layer even if the outer electrode is formed to have a smaller outer shape than the design dimension by wet etching. Therefore, the contact area between the dielectric layer and the upper electrode is not affected at all, and a capacitor element having a desired capacitance can be obtained.

  In the above-described invention, the area of the first opening of the protective insulating layer is adjusted according to the capacitance of the capacitor element, and the entire area of the upper electrode is the laser via process when the capacitor component is built in the wiring board. It is adjusted according to the beam diameter of the laser used in the above. In the capacitor component of the present invention, even if the contact area between the dielectric layer and the upper electrode is reduced in order to obtain a capacitor element having a small capacitance, the entire area of the upper electrode is independent of the capacitance. It becomes possible to set large.

  Therefore, since the entire area of the upper electrode can be ensured according to the beam diameter of the laser, the laser does not protrude from the upper electrode, and there is no possibility that a connection failure will occur. Thereby, even a capacitor component having a small capacitance can be easily built in the wiring board using a laser via process.

  In the above-described invention, the substrate is formed of a silicon substrate provided with an insulating layer on the lower electrode side, or a resin layer. When the substrate is formed from a resin layer, the capacitor element is formed on the resin layer in a state where the resin layer is supported by the glass substrate, and then the glass substrate is peeled off from the resin layer and removed. By adopting such a manufacturing method, a thin resin layer can be used as a substrate, so that the capacitor component can be thinned.

  As described above, the capacitor component of the present invention can provide a desired capacitance, and even a capacitor component having a small capacitance can be easily built into a wiring board using a laser via process. it can

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  Before describing the capacitor component of the present embodiment, problems of the capacitor component of the related art will be described. As shown in FIG. 1, in the related-art capacitor component, a lower electrode 200 made of a tantalum layer is formed on a substrate 100, and a dielectric layer 300 made of a tantalum oxide layer is formed on a part of the lower electrode 200. ing. The tantalum oxide layer is formed by anodizing the tantalum layer halfway in the film thickness direction.

  An upper electrode 500 including a seed layer 420 and a metal pattern layer 440 is formed on the dielectric layer 300. The entire upper electrode 500 is formed in contact with the dielectric layer 300.

  Further, a lower electrode lead portion 600 including a seed layer 420 and a metal pattern layer 440 is formed on the lower electrode 200, and the connection portion of the lower electrode 200 is adjusted to be the same as the height of the upper electrode 500. ing.

The inventor of the present application creates a plurality of capacitors whose upper electrode dimensions are designed so that the capacitance is 1.1 to 10 pF in the capacitor parts of the related technology described above, and measures the capacitance of each capacitor. did. The film thickness of the dielectric layer 300 (tantalum oxide layer) of each capacitor was set to 300 nm. In this case, the capacitance density is 70 nF / cm ² .

For example, when the capacitance of the capacitor component is set to 10 pF, the area of the upper electrode 500 is 120 × 120 μm ² (design value). When the capacitance of the capacitor component is set to 1.1 pF, the area of the upper electrode 500 is 40 × 40 μm ² (design value).

  According to the result, as shown in FIG. 2, when the design capacitance value of each capacitor component is x and the measurement capacitance value is y, an approximate expression indicating the relationship is y = 0.89x, and on average − It was found that an error of 11% occurred. As shown in FIG. 3, the error rate from the design capacitance value tends to increase as the design capacitance value of the capacitor component decreases. In the case of the minimum capacitance (1.1 pF), the design capacitance value is reduced. On the other hand, it was -35%, and the largest error rate was generated.

  The reason why the measured capacitance value is smaller than the designed capacitance value is that when the upper electrode 500 is formed, the actual finished area is smaller than the designed area. The contact area between the upper electrode 500 and the dielectric layer 300 is one of the factors that determine the capacitance of the capacitor component.

  The method for forming the upper electrode 500 of the capacitor component shown in FIG. 1 (semi-additive method) will be described. First, a seed layer 420 is formed on the dielectric layer 300, and a required opening is provided thereon. A resist (not shown) is formed. Subsequently, a metal pattern layer 440 is formed in the opening of the resist by electrolytic plating. Further, after the resist is removed, the seed layer 420 is etched using the metal pattern layer 440 as a mask to obtain the upper electrode 500.

  The related-art capacitor component has a structure in which the entire upper electrode 500 is in contact with the dielectric layer 300, and a considerable etching shift occurs in the process of etching the seed layer 420 in the semi-additive method. The size of the upper electrode 500 is smaller than the design value.

  In the experiment of the present inventor, when the design capacitance value is 1.1 pF, the design dimension of the upper electrode 500 is 40 μm □, but actually it is as small as 34 to 37 μm □. As described above, in the capacitor parts of the related art, there is a problem that the dimension of the upper electrode is smaller than the design value and the capacitance of the capacitor deviates from the design value.

  When the capacitor component is built in the wiring board, the capacitor component is covered with an insulating layer, and then the insulating layer is processed with a laser to form via holes connected to the upper electrode and the lower electrode of the capacitor component. The At this time, since the laser beam diameter is 50 μm or more, it is necessary to set the dimension of the upper electrode to be larger than that.

  However, in the related-art capacitor parts, when the capacitance is designed to be 1.1 pF, for example, the size of the upper electrode is 40 μm □, and the laser protrudes from the upper electrode 500. It becomes difficult to use a laser via process.

  The capacitor component of the present embodiment described below can solve the above-described problems.

(First embodiment)
4 to 6 are cross-sectional views illustrating a method for manufacturing a capacitor component according to the first embodiment of the present invention, and FIG. 7 is a cross-sectional view illustrating the capacitor component.

  As shown in FIG. 4A, the capacitor component manufacturing method according to the first embodiment is as follows. First, a silicon wafer 10 having a thickness of about 725 μm is prepared, and the silicon wafer 10 is thermally oxidized to be formed on both sides thereof. Silicon oxide layers 12 (insulating layers) each having a thickness of about 300 nm are formed. Note that a plurality of capacitor formation regions are defined in the silicon wafer 10.

  Thereafter, as shown in FIG. 4B, a tantalum (Ta) layer 14a having a thickness of about 600 nm is formed on the silicon oxide layer 12 on the silicon wafer 10 by sputtering. Further, as shown in FIG. 4C, a resist 19 having an opening 19x is formed on a required portion of the tantalum layer 14a.

  Next, as shown in FIG. 4 (d), the surface layer portion of the tantalum layer 14a exposed in the opening 19x of the resist 19 is oxidized by an anodizing method with a formation voltage of about 200 V to tantalum oxide with a thickness of about 300 nm. Layer 16a is formed. Thereafter, the resist 19 is removed. Thereby, the tantalum layer 14a becomes the lower electrode 14 for the capacitor, and the tantalum oxide layer 16a formed halfway in the film thickness direction of the tantalum layer 14a becomes the dielectric layer 16 for the capacitor. The dielectric layer 16 is patterned and formed in each capacitor formation region of the silicon wafer 10.

  Tantalum is an example of valve metal, which has a so-called valve action, in which the metal oxide obtained by anodizing it passes current only in one direction and hardly passes current in the opposite direction. It is. In addition to tantalum, the valve metal includes niobium, aluminum, or titanium. A niobium oxide layer, an aluminum oxide layer, or a titanium oxide layer obtained by anodizing a part of such a valve metal layer is used. It may be used as the dielectric layer 16.

Alternatively, a silicon oxide layer or a ferroelectric layer (BTO (BaTiO ₃ ), BST ((Ba, Sr) TiO ₃ ), PZT (Pb (Zr, Ti) O ₃ )) or the like is sputtered on the lower electrode 14. The dielectric layer 16 may be formed by patterning based on photolithography.

  Next, as shown in FIG. 5A, the protective insulating layer 20 is formed in which the first opening 20 x is provided on the dielectric layer 16 and the second opening 20 y is provided on the lower electrode 14. . The protective insulating layer is formed from the peripheral side to the outside of the dielectric layer 16, and the first opening 20x is disposed in the pattern region of the dielectric layer 16 so that the dielectric layer 16 having a required area is exposed.

  The protective insulating layer 20 is preferably formed by patterning a photosensitive polyimide resin by photolithography. A polyimide resin having a film thickness of about 10 μm and a relative dielectric constant of about 3.7 is used. Alternatively, in addition to polyimide resin, various insulating materials can be used as long as they have equivalent insulating characteristics such as phenol resin.

  As will be described later, the upper electrode is formed from the first opening 20x of the protective insulating layer 20 to the upper surface of the protective insulating layer 20, and the dielectric layer 16 and the upper electrode 18 are contacted by the opening 20x of the protective insulating layer 20. An area is defined. Thus, in this embodiment, the accuracy of the contact area between the dielectric layer 16 and the upper electrode 18 is determined by the accuracy of photolithography when the protective insulating layer 20 is patterned.

  Next, as shown in FIG. 5B, a chromium (Cr) layer having a thickness of 50 nm and a copper (Cu) layer having a thickness of 500 nm are formed on the upper surface of the structure in FIG. The seed layer 18a is obtained by forming sequentially. Subsequently, as shown in FIG. 5C, a resist 29 having a first opening 29x provided above the dielectric layer 16 and a second opening 29y provided above the lower electrode 14 is used as a seed layer. Form on 18a. Further, as shown in FIG. 5D, a copper layer pattern having a film thickness of about 10 μm in the first and second openings 29x and 29y of the resist 29 by electrolytic plating using the seed layer 18a as a plating power feeding path. 18b is formed.

  Next, as shown in FIG. 6A, the resist 29 is removed to expose the seed layer 18a. Thereafter, as shown in FIG. 6B, the seed layer 18a is wet-etched using the copper layer pattern 18b as a mask. As a result, the upper electrode 18 constituted by the seed layer 18a and the copper layer pattern 18b and electrically coupled to the dielectric layer 16 is obtained. The upper electrode 18 is formed by embedding the first opening 20 x of the protective insulating layer 20 and is formed to extend on the upper surface of the protective insulating layer 20.

  At the same time, the lower electrode lead portion 15 constituted by the seed layer 18a and the copper layer pattern 18b and connected to the lower electrode 14 is obtained. The upper surface of the lower electrode lead portion 15 serves as a connection portion of the lower electrode 14, and the upper surfaces of the upper electrode 18 and the lower electrode lead portion 15 are formed to have substantially the same height.

  In this way, the capacitor element C composed of the lower electrode 14, the dielectric layer 16 and the upper electrode 18 is formed in each capacitor forming region of the silicon wafer 10.

  In the present embodiment, the protective insulating layer 20 having the first opening 20x is formed in the pattern region of the dielectric layer 16, and the upper electrode 18 extends from the first opening 20x to the upper surface of the protective insulating layer 20. It is formed.

  For this reason, when the seed layer 18a is wet-etched using the copper layer pattern 18b as a mask to obtain the upper electrode 18, even if the outer shape of the upper electrode 18 is smaller than the design dimension, the pattern edge of the upper electrode 18 is a protective insulating layer. Therefore, the contact area between the dielectric layer 16 and the upper electrode 18 is not affected at all. This is because the contact area between the dielectric layer 16 and the upper electrode 18 is determined by the first opening 20 x of the protective insulating layer 20. Therefore, unlike the related art, the contact area between the dielectric layer 16 and the upper electrode 18 is not greatly deviated from the design value, and the capacitor element C having a desired capacitance can be obtained.

  The upper electrode 18 may be formed by patterning the metal layer by photolithography and etching after the metal layer is formed by sputtering or the like.

  Subsequently, as shown in FIG. 6C, the silicon wafer 10 is polished and thinned from the lower surface side until the silicon wafer 10 has a thickness of about 50 μm. Further, the silicon wafer 10 is cut into pieces so as to obtain individual capacitor formation regions of the silicon wafer 10 and separated into individual pieces. Thereby, as shown in FIG. 7, the capacitor component 1 of 1st Embodiment is obtained.

  As shown in FIG. 7, in the capacitor component 1 of the first embodiment, the lower electrode 14 made of a tantalum layer is formed on the upper surface side of the silicon substrate 10a via the silicon oxide layer 12. A dielectric layer 16 made of a tantalum oxide layer is formed in a pattern on a part of the lower electrode 14 in the middle of the film thickness direction. The tantalum oxide layer is obtained by anodizing the tantalum layer. The lower electrode 14 includes an extending portion 14 x extending in the lateral direction from the lower side of the dielectric layer 16.

  A protective insulating layer 20 having first and second openings 20x and 20y provided on the dielectric layer 16 and the extended portion 14x of the lower electrode 14 is formed from the periphery of the dielectric layer 16 to the outside. ing. The protective insulating layer 20 is preferably formed from a resin such as polyimide. Furthermore, an upper electrode 18 that is electrically coupled to the dielectric layer 16 is formed from the first opening 20x of the protective insulating layer 20 to the upper surface of the protective insulating layer 20, and a pattern edge of the upper electrode 18 is formed on the protective insulating layer. 20 is arranged on the top. The upper electrode 18 includes a seed layer 18a and a copper layer pattern 18b.

  A lower electrode lead portion 15 connected to the lower electrode 14 is formed from the second opening 20 y of the protective insulating layer 20 to the upper surface of the protective insulating layer 20, and the upper surface serves as a connection portion of the lower electrode 14. ing. The lower electrode lead portion 15 is made of the same material as the upper electrode 18. By providing the lower electrode lead portion 15 on the lower electrode 14, the connection portion of the lower electrode 14 is set to have substantially the same height as the upper electrode 18.

  As described above, in the capacitor component 1 of this embodiment, the contact area between the dielectric layer 16 and the upper electrode 18 is defined by the first opening 20x of the protective insulating layer 20, and the pattern edge of the upper electrode 18 is obtained. Is raised to the upper surface of the protective insulating layer 20. Therefore, as described in the manufacturing method described above, when the upper electrode 18 is formed by the semi-additive method, even if the outer shape of the upper electrode 18 becomes smaller than the design value due to the etching shift, the dielectric layer 16 and the upper electrode The contact area with 18 is not affected at all.

  In addition, since the upper electrode 18 is arranged so as to be raised on the upper surface of the protective insulating layer 20, even when the contact area between the dielectric layer 16 and the upper electrode 18 is reduced in order to obtain a capacitor having a small capacitance, The entire area of the upper electrode 18 can be set large regardless of the capacitance. As a result, as will be described later, the entire area of the upper electrode 18 can be adjusted in accordance with the laser via process. Therefore, even a capacitor component having a small capacitance can be easily incorporated in the wiring board using the laser via process. be able to.

  The inventor of the present application creates a plurality of capacitors whose upper electrode dimensions are designed so that the capacitance is 1.1 to 10 pF in the capacitor component of this embodiment, and measures the capacitance of each capacitor. Compared with the capacitor parts of the related technology mentioned above. The film thickness of the dielectric layer 16 (tantalum oxide layer) of each capacitor was set to 300 nm as in the related art.

  FIG. 8 shows the relationship between the design capacitance value and the measured capacitance value of the capacitor component of the present embodiment, and the data of the capacitor component of the related technology of FIG. 2 described above is shown again for comparison. As shown in FIG. 8, when the design capacitance value of each capacitor component is x and the measured capacitance value is y, an approximate expression indicating the relationship is y = 0.96x, and the measured capacitance value of the capacitor component of this embodiment is as follows. The average error from the design capacitance value was -4%, which is less than half of the error (-11%) of the capacitor part of the related art described above.

  FIG. 9 is a diagram showing an error rate ((designed capacity value−measured capacity average value) / designed capacity value) × 100 (%) of the measured capacity average value from each designed capacity value. The data of capacitor parts of related technology is reprinted. As shown in FIG. 9, the error rate of the capacitor component of this embodiment is lower than that of the related art at each design capacitance value. The error at the smallest design capacitance (1.1 pF) was 10%, reduced to 1/3 of the error (30%) of the related art capacitor component.

  Further, the dimension (diameter) of the first opening 20x of the protective insulating layer 20 that defines the contact area between the dielectric layer 16 and the upper electrode 18 is stably formed at −1 to −2 μm with respect to the design value. I was able to. Considering that the size (diameter) of the upper electrode of the capacitor component of the related art is −3 to −6 μm with respect to the design value, the capacitor component of the present embodiment includes the dielectric layer 16 and the upper electrode 18. It can be seen that the contact area can be closer to the design value.

As shown in FIG. 10, in the capacitor component of this embodiment, the protective insulating layer 20 is formed to define the contact area between the dielectric layer 16 and the upper electrode 18, so that the upper electrode 18 and the lower electrode 14 are formed. , A protective insulating layer 20 is disposed between them, thereby generating a parasitic capacitance PC. When the area of the first opening 20x of the protective insulating layer 20 is 40 μ × 40 μm ² (design capacitance value: 1.1 pF) and the entire area of the upper electrode 18 is 300 × 200 μm ² , the parasitic capacitance is 0.15 pF. It becomes.

Therefore, the protective insulating layer 20 having a low relative dielectric constant is used, the thickness thereof is increased, and the entire area of the upper electrode 18 is reduced (for example, 150 × 150 μm ² ) to reduce the cover on the protective insulating layer 20. It is preferable to reduce the parasitic capacitance PC by doing so. Thereby, the capacity | capacitance precision of a capacitor component can further be improved. For example, when a tantalum oxide layer is used as the dielectric layer 16, the protective dielectric layer 20 has a relative dielectric constant of 4 or less and a film thickness of 10 to 50 μm.

  Next, a method for incorporating the capacitor component of this embodiment in a wiring board will be described.

  First, a core substrate 30 as shown in FIG. In the core substrate 30, a through hole 32x is provided in an insulating substrate 32 made of glass epoxy resin or the like, and a through hole plating layer 34 is provided in the through hole 32x. A first wiring layer 36 a interconnected through a through-hole plating layer 34 is formed on both sides of the insulating substrate 32. In the present embodiment, the core substrate 30 including the first wiring layer 36a is used as an example of the mounted body on which the capacitor component is mounted.

  Next, as illustrated in FIG. 11B, an adhesive layer 38 is formed on the upper surface side of the core substrate 30. As the adhesive layer 38, a resin in a semi-cured state (B stage) is used. Subsequently, as shown in FIG. 11C, the capacitor component 1 of the present embodiment described above is prepared, and the capacitor component 1 is disposed on the adhesive layer 38 with the silicon substrate 10a side facing down. Furthermore, the capacitor component 1 is fixed to the adhesive layer 38 by curing the adhesive layer 38 by heat treatment.

  Subsequently, as shown in FIG. 12A, a first interlayer insulating layer 40 a that covers the capacitor component 1 is formed on the upper surface side of the core substrate 30 by sticking a resin film or the like. Further, a first interlayer insulating layer 40 a that covers the first wiring layer 36 a is also formed on the lower surface side of the core substrate 30.

  Next, as shown in FIG. 12B, the first interlayer insulating layer 40 a on the upper surface side of the core substrate 30 is processed with a laser, so that the depth reaching the upper electrode 18 and the lower electrode lead portion 15 of the capacitor component 1 is reached. The first via hole VH1 is formed.

  In addition, the first interlayer insulating layer 40a and the adhesive layer 38 on the upper surface side of the core substrate 30 are processed by a laser to form a first via hole VH1 having a depth reaching the first wiring layer 36a. Further, on the lower surface side of the core substrate 30, the first via hole VH1 is formed in the portion of the first interlayer insulating layer 40a on the first wiring layer 36a.

Here, when the capacitor part of the related art described above is employed, when the capacitance of the capacitor is set to be relatively small as 1.1 pF, when the film thickness of the tantalum oxide layer is 300 nm, the area of the upper electrode is 40 μ × 40 μm ² is set. However, since the laser beam diameter used when forming the first via hole VH1 is 50 to 100 μm, in the related-art capacitor component, the laser protrudes from the upper electrode, resulting in poor connection.

  On the other hand, in the capacitor component 1 of the present embodiment, the upper electrode 18 is disposed so as to be raised from the inside of the first opening 20x of the protective insulating layer 20 to the upper surface of the protective insulating layer 20. Therefore, even when the contact area between the dielectric layer 16 and the upper electrode 18 is reduced in order to obtain a capacitor element having a small capacitance, the entire area of the upper electrode 18 is large regardless of the capacitance. It becomes possible to set.

Therefore, even if the capacitor part has a small electrostatic capacity, the entire area of the upper electrode can be secured large in accordance with the laser beam diameter (for example, 300 × 200 μm ² ), so that the laser does not protrude from the upper electrode. There is no risk of connection failure.

  Next, as shown in FIG. 12C, the first and second electrode lead portions 15 and 15 of the capacitor component 1 are connected to the first wiring layer 36a through the first via hole VH1 by a semi-additive method or the like. Two wiring layers 36b are formed on the first interlayer insulating layer 40a. Also on the lower surface side of the core substrate 30, a second wiring layer 36b connected to the first wiring layer 36a through the first via hole VH1 is formed.

  Next, as illustrated in FIG. 13, the second interlayer insulating layer 40 b in which the second via hole VH <b> 2 is provided on the second wiring layer 36 b is formed on both sides of the core substrate 30. Thereafter, the third wiring layer 36c connected to the second wiring layer 36b through the second via hole VH2 is formed on both surfaces of the core substrate 30 on the second interlayer insulating layer 40b. Further, a solder resist 42 having an opening 42x provided on the third wiring layer 36c is formed on both sides of the core substrate 30, and Ni / Au plating is applied to the portion of the third wiring layer 36c in the opening 42x. Is applied to form the connecting portion 37.

  Thereby, the capacitor built-in substrate 5 configured by incorporating the capacitor component 1 of the present embodiment in the wiring substrate is obtained. As described above, in the capacitor built-in substrate 5 of the present embodiment, even if the capacitor part has a small electrostatic capacity, the entire area of the upper electrode 18 can be set large regardless of the electrostatic capacity. The capacitor component can be built in the wiring board.

(Second Embodiment)
14 and 15 are sectional views showing a method for manufacturing a capacitor component according to the second embodiment of the present invention, and FIG. 16 is a sectional view showing the capacitor component. The second embodiment is different from the first embodiment in that a resin layer is used as a substrate instead of a silicon substrate. In the second embodiment, the same elements as those in the first embodiment are denoted by the same reference numerals, and detailed description of the manufacturing method and the like will be omitted.

  As shown in FIG. 14A, the capacitor component manufacturing method according to the second embodiment first prepares a glass substrate 50, and chromium (Cr) or nickel having a film thickness of 50 to 100 nm on the glass substrate 50. (Ni) is formed by a sputtering method to obtain the peeling metal layer 52.

  Next, as shown in FIG. 14B, a resin layer 54 having a thickness of 5 to 50 μm is formed on the peeling metal layer 52. The resin layer 54 is obtained, for example, by applying a liquid polyimide resin and then curing it by heat treatment. The glass substrate 50 functions as a support for the resin layer 54, and various substrates that function as a support in addition to the glass substrate 50 can be used.

  Subsequently, as shown in FIG. 14C, the lower electrode 14 made of a tantalum layer and a part of the tantalum layer are anodized on the resin layer 54 by the same method as in the first embodiment. A dielectric layer 16 made of a tantalum oxide layer is formed.

  Next, as shown in FIG. 14D, the same structure as that of the first embodiment is formed on the resin layer 52 by performing the steps from FIG. 5A to FIG. 6B of the first embodiment. The capacitor element C is formed.

  Subsequently, as shown in FIG. 15A, a protective film 56 is attached to the upper surface of the structure shown in FIG. Further, the peeling metal layer 52 formed on the wafer-like glass substrate 50 is partially removed from the side surface to the inside of the glass substrate 50 by wet etching using a nitric acid-based etchant. Thereby, the glass substrate 50 will be in the state which can be easily peeled from the metal layer 52 for peeling.

  Subsequently, after the glass substrate 50 is peeled and removed from the peeling metal layer 52, the peeling metal layer 52 remaining in the center of the lower surface of the resin layer 54 is removed by wet etching. Thereby, as shown in FIG.15 (b), the lower surface of the resin layer 54 will be in the exposed state. Thereafter, as shown in FIG. 15C, the protective film 56 is removed.

  Further, the structure shown in FIG. 15C is cut into pieces so as to obtain each capacitor formation region, and is separated into pieces. Thereby, as shown in FIG. 16, the capacitor component 2 of 2nd Embodiment is obtained.

  As shown in FIG. 16, in the capacitor component 2 of the second embodiment, the lower electrode 14 made of a tantalum layer is formed on the resin layer 54 that functions as a substrate, and the tantalum layer is anodized on the surface layer portion of the lower electrode 14. A dielectric layer 16 made of a tantalum oxide layer is provided. As in the first embodiment, the protective insulating layer 20 in which the first opening 20x is provided in the pattern region of the dielectric layer 16 and the second opening 20y is provided on the lower electrode 14 is the dielectric. The layer 16 is formed from the periphery to the outside.

  Further, as in the first embodiment, the upper electrode 18 composed of the seed layer 18a and the copper layer pattern 18b and electrically coupled to the dielectric layer 16 is protected from the first opening 20x of the protective insulating layer 20. It is formed over the upper surface of the layer 20. A lower electrode lead portion 15 made of the same material as the upper electrode 18 is formed from the second opening 20 y of the protective insulating layer 20 to the upper surface of the protective insulating layer 20.

  The capacitor component 2 according to the second embodiment is obtained by replacing the silicon substrate 10a of the capacitor component 1 according to the first embodiment with a resin layer 54, and has the same effect as that of the first embodiment. In addition, in the second embodiment, the glass substrate 50 is removed after the capacitor element C is formed on the resin layer 54 with the thin resin layer 54 supported by the glass substrate 50. A thin capacitor component using the thin resin layer 54 as a substrate is easily manufactured.

  The capacitor component 2 of the second embodiment is also built in the wiring board by the same method as that of the first embodiment. In the second embodiment, since the capacitor component can be further reduced in thickness, it is easy to incorporate the capacitor component in the wiring board, and the capacitor embedded substrate can be reduced in thickness.

FIG. 1 is a cross-sectional view showing a capacitor component of the related art. FIG. 2 is a diagram showing the relationship between each design capacitance value and the measured capacitance value in the capacitor component of the related art. FIG. 3 is a diagram showing the error rate of the measured capacitance average value from each design capacitance value in the capacitor component of the related art. 4A to 4D are cross-sectional views (No. 1) showing the method for manufacturing the capacitor component according to the first embodiment of the present invention. 5A to 5D are sectional views (No. 2) showing the method for manufacturing the capacitor component according to the first embodiment of the present invention. 6A to 6C are cross-sectional views (part 3) illustrating the method of manufacturing the capacitor component according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing the capacitor component according to the first embodiment of the present invention. FIG. 8 is a diagram showing the relationship between each design capacitance value and the measured capacitance value in the capacitor component according to the first embodiment of the present invention. FIG. 9 is a diagram showing an error rate of the measured capacitance average value with respect to each design capacitance value in the capacitor component according to the first embodiment of the present invention. FIG. 10 is a schematic diagram for explaining the parasitic capacitance generated in the capacitor component according to the embodiment of the present invention. 11A to 11C are cross-sectional views (part 1) showing the method for manufacturing the capacitor built-in substrate according to the first embodiment of the present invention. 12A to 12C are sectional views (No. 2) showing the method for manufacturing the capacitor built-in substrate according to the first embodiment of the present invention. FIG. 13 is a cross-sectional view showing the capacitor built-in substrate according to the first embodiment of the present invention. 14A to 14D are sectional views (No. 1) showing the method for manufacturing the capacitor component according to the second embodiment of the present invention. FIGS. 15A to 15C are sectional views (No. 2) showing the method for manufacturing the capacitor component according to the second embodiment of the present invention. FIG. 16 is a cross-sectional view showing a capacitor component according to the second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 ... Capacitor component, 5 ... Capacitor built-in substrate, 10 ... Silicon wafer, 12 ... Silicon oxide layer, 14a ... Tantalum layer, 14 ... Lower electrode, 15 ... Lower electrode extraction part, 16 ... Dielectric layer, 16a ... Tantalum Oxide layer, 18 ... upper electrode, 18a ... seed layer, 18b ... copper layer pattern, 19, 29 ... resist film, 19x, 29x, 42x ... opening, 20 ... protective insulating layer, 20x ... first opening, 20y ... 2nd opening, 30 ... Core substrate, 32 ... Insulating substrate, 32x ... Through hole, 34 ... Sue hole plating layer, 36a ... 1st wiring layer, 36b ... 2nd wiring layer, 36c ... 3rd wiring layer, 38 ... Adhesion Layer, 37... Connecting portion, 40a... First interlayer insulating layer, 40b... Second interlayer insulating layer, 42... Solder resist, VH1, VH2 .. via hole, C .. capacitor element, PC.

Claims (10)

A substrate,
A lower electrode formed on the substrate;
A dielectric layer that is electrically coupled and patterned to the lower electrode;
A protective insulating layer formed on the dielectric layer and having a first opening in a pattern region of the dielectric layer;
An upper electrode electrically coupled to the dielectric layer and formed from the first opening to the upper surface of the protective insulating layer;
The capacitor part, wherein a contact area between the dielectric layer and the upper electrode is defined by the first opening of the protective insulating layer.   The lower electrode has an extending portion extending laterally from the dielectric layer, and the protective insulating layer is provided with a second opening on the extending portion of the lower electrode. 2. The capacitor component according to claim 1, wherein a lower electrode lead portion connected to the lower electrode is provided from two openings to an upper surface of the protective insulating layer.   2. The capacitor component according to claim 1, wherein the substrate is made of a silicon substrate having an insulating layer provided on the lower electrode side or a resin layer.   4. The capacitor component according to claim 1, wherein the protective insulating layer is made of polyimide resin or phenol resin. 5.   4. The capacitor according to claim 1, wherein the lower electrode is formed of a valve metal layer, and the dielectric layer is formed by anodizing a part of the valve metal layer. 5. parts.   The area of the first opening of the protective insulating layer is adjusted according to the capacitance of the capacitor element, and the entire area of the upper electrode is used in a laser via process when the capacitor component is built in the wiring board. 4. The capacitor component according to claim 1, wherein the capacitor component is adjusted according to a beam diameter of the laser. A mounted body,
The capacitor component according to any one of claims 1 to 6 mounted on the mounted body;
An interlayer insulating layer covering the capacitor component;
A via hole formed in the interlayer insulating layer and connected to the upper electrode and the lower electrode of the capacitor component;
A capacitor-embedded substrate, comprising: a wiring layer formed on the interlayer insulating layer and electrically connected to the upper electrode and the lower electrode through the via hole.   The capacitor built-in substrate according to claim 7, wherein the via hole is formed by a laser. Forming a lower electrode on the substrate;
Patterning and forming a dielectric layer electrically coupled to the lower electrode;
Forming a protective insulating layer having an opening in a pattern region of the dielectric layer;
Forming an upper electrode electrically coupled to the dielectric layer on the upper surface of the protective insulating layer from within the opening of the protective insulating layer. In the step of forming the lower electrode, the lower electrode is formed from a valve metal layer,
10. The method of manufacturing a capacitor component according to claim 9, wherein in the step of forming the dielectric layer, the dielectric layer is obtained by anodizing a surface layer portion of the valve metal layer.

Images