TW200849434A - Memory devices including separating insulating structures on wires and methods of forming - Google Patents

Memory devices including separating insulating structures on wires and methods of forming Download PDF

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Publication number
TW200849434A
TW200849434A TW097120638A TW97120638A TW200849434A TW 200849434 A TW200849434 A TW 200849434A TW 097120638 A TW097120638 A TW 097120638A TW 97120638 A TW97120638 A TW 97120638A TW 200849434 A TW200849434 A TW 200849434A
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TW
Taiwan
Prior art keywords
wire
wires
wafer
separate
separation
Prior art date
Application number
TW097120638A
Other languages
English (en)
Inventor
Cheol-Joon Yoo
Original Assignee
Samsung Electronics Co Ltd
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Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200849434A publication Critical patent/TW200849434A/zh

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Description

200849434 28264pif.doc 九、發明說明： 【發明所屬之技術領域】 本發明概言之是關於半導體領域，且更具 h 關於半導體接線（wiring)及相關方法。 疋 【先前技術】 隨著電路之積體程度愈來愈高，用以於曰 面安裝晶片）_導訊號之導線之間隔（即間距
=可向㈣容納積體電路日日日片以及基板之裝置封穿外部 m、訊號，或者從裝置封裝之料供給峨。 裝製程之一部分，可使基板(具有安裝於上面 用以連接二者之導線）經歷模製製程，此模製 衣私用以㈣體電路及基板囊封於裝置封裝中。因導線間 =能彳M、，故模㈣程可導致某些導_互接觸（或者 =板接觸）’進而可形成電氣短路。此種現象有時稱為 $線偏移（wire sweeping )」。 用以解決導線偏移之其中—種方法是於積體電路裝置 衣作期間料線塗覆时紐料。導線之塗覆闡述於例如 JP 2004-282021中以及美國專利第6,822,34〇號中。 【發明内容】 根據本發明之實施例可提供包含導線上有分離隔離結 構之記憶體元件以及其形成方法。根據鱗實施例，包含 於積體電路元件巾之導線上可軸有分離隔離結構。導線 分離隔離結構可環繞導線之相應截面部分，此可用作 「分隔裝置（stand-offs)」，以防止緊鄰之導線（或其他 5 200849434 28264pif.doc 短路，藉以減少具有在各導線(或其他組 形狀:二分離隔離結構可具有實質呈球形之外側 有實質_\ Γ之其他實施财，分離隔離結構可具 中，、八側形狀。於根據本發明之再—些實施例 Γ ο 隔離1構間隔可實質上相等，此外，位於分離 【實的導線之外露部分亦可細^ 面地以舉例方式顯示本發明實施例之附酿 式，而π座ί 然而，本發明亦可實施為諸多種不同形 提供”伽於本文所述之實顺實施例。而是， 向孰:;=池貫施例旨在使本揭露内容透徹及完整，並 迷及所_術者全面傳達本發明之範圍。而a，本文所 庫:Γ:Γ例亦皆包含其互補導電類型實施例。 應」稱一元件「連接至」、「減至」或「因 舞接至=ΐ:形式)另—元件時，其既可直接連接至、 當裤二Ζ應70件’亦可存在中間元件。相比之下， 應」另：牛J接連接至」、「直接耦接至」*「直接因 皆指代相:不存在中間元件。通篇中，相同編號 項中一文中所用措詞「及/或」包含相關羅列 或夕者之任一及所有組合併可縮寫為「/」。 來可使"-」、「第二」、「第 然而該=疋件、組件、區域、層及，或區段， 70件、组件、區域、層及/或區段不應受限於該等 200849434 28264pif.doc 措詞。該等措詞僅用於使各元件、組件、區域、層或區段 相互區別。因此，可將下文所述第_元件、組件、區域、 層或區段稱為第二元件、組件、輯、層或區段，此並不 脫離本發明之教示内容。 本文所用術語只是為了描述特定實施例，而非旨在限 定本發明。除上下文明確指明外，本文中所用單數形式「一 (a或an)」及「該（the)」旨在亦包括複數形式。進一 Ο
Q 步應理解’本，兄明書中所用措詞「包括（咖卸嫩及/或 comprising)」是規定所述特徵、整數、步驟、操作、元 件、及/或組件之存在，但不排除亦存在或增加一或多個苴 2徵、整數、步驟、操作、元件、組件、及/或其群組之 =在，比之T，本說明書中所用措詞「基本上由…組成
Stm°〇f)」（及/或其變化形式）是規定各特徵、整
Li敕?作、元件、及/或組件之所述數量，且排除其 他餐被、整數二步驟、操作、元件、及/或組件。 及斜外’本文所用之所有術語（包括技術術語 所丘4何二自具有本發_屬技術領域中之通常技術者 各。^二Ϊ —步應理解，除在本文中明確指明外， (例如在㈣字典中所定義之術語）應被認為具有 14在相關技術背景及本申請宰 w 二: =有理想化或過於正式之意義，除非本文中明確規定如 φ,tl文所更詳細說明’在根據本發明之某些實施例 ，匕§於積體電路元件中導 /、-、 綠上可形成有分離隔離結 7 200849434 28264pif.doc
構。導線上之分_雜構可環繞導線之相練面部分， 此可用作「分隔裝置（siand_Qffs)」，以防止緊鄰之導線 (或其他相鄰組件）相互鱗，藉以減少具有在纟導線（或 其他組件）之間減小間距之元件的相關聯之缺陷。於根據 本發明之某些實施例中，分離隔離結構可具有實質呈球形 之外側形狀。於根據本發明之其他實施例中，分離隔離結 構可具有實質橢_之外侧形狀。於根據本發明之再一些 實施例中，分離隔離結構之間隔可實f上相等，此外，位 於分離隔離結構之間的導線之外露部分亦可實質上相等。 ，根據本發明之再―些實施财，分離隔離結構可形 成於在橫向上緊鄰及/或在垂直方向上緊鄰之導線上。舉例 =姑於某些積體電路讀中，將多個⑸堆疊於基板上， 因^吏垂直方向上之料線之間存在短路（即墟至上部 =或下部晶片之導線之間電氣短路）之可能性以及在連 接至同U之導線之間錢向上存在電氣短路之可能 於根據本發明之再一 助於避免導線盘晶片或基；太：1 ’刀：U可有 ^ I、日日乃忒丞板本身之間的電氣短路。舉例而 言，t有時被稱作「凸塊反向製程（b腿P，⑽_)」 ^-衣程巾，導線首先結合至絲上並隨後結合至晶片 由^線之結合次序及/以於導線在橫向上結合減小 、導線與晶片表面之間隔。相應 導繞盘發明之某些實施例中’分離隔離結構可充當 hi曰目片表面及/或基板本身之間的分隔裝置，藉以減少 8 200849434 28264pif.dc 電氣短路。 於根據本發明之再一些實施例中， Ο 理以減小導線與欲沉積於導線上之可错由斟導線預處 形成分離隔離結構。一旦預處理完成；，"之間的表面張力而 之相應截面部分之分離隔離結構^ 便可形成環繞導線 施例中，此預處理製程可包含利用j，據本發明之某些實 理。於根據本發明之再一些實施虱氣或氮氣實施電漿處 供預處理。 —焉&歹中，可利用濕式製程提 _於根據本發明之再―些實施、、 隔離液體而提供分離隔離結槿，_可猎由對導線塗覆 基（resin base)之聚合物 ^^離液體包含具有樹脂 strength reinforcing agent) ( adhesiye 及溶劑。於根據本發明之某竑每 聚醯亞胺樹脂、丙烯酸樹月旨、例中，基體樹脂可以是 (silicone resin)。於根據太级及氣樹脂、或聚矽氧樹脂 以η右播〜叫 ^ 务明之某些實施例中，溶劑可
以疋有機溶劑，包含按聚合物 ^ Jr J 於根據本發明之再一些&夏計少於約50%。 構後，可實施硬結處理，包二:例中’於形成分離隔離結 離隔離結構。於本發明之再j 200°c之溫度下加熱分 象、、°構後，可彻紫外光輻射實施硬結處理。 於根據本發明之再一此资 , , 二焉知例中，於形成分離隔離結 :揮:=分離之硬結處理，其中於第 次硬έ士二里售；2成此多個分離隔離結構之溶劑。於第--人硬結處理後可提供第二次硬結處理，其可包括提供環氧 200849434 28264pif.doc 模製化合物’用於形成塗覆於分離隔雜構上之模製材 料於本么月之某些貫施例中，上述第一次硬結處理可於 高於約70°C之溫度下進行。 ._目^積體電料件⑽之示意性剖視®，積體電路 • 以牛100包含文裝於基板110上之積體電路晶片120 (於 下文中％作「晶片」）。具體而言’晶片12()藉由黏合劑 Π5女衣於基板iig上。電訊號藉由多條用於將晶片no 〇 ，耦接至基板11G之導線⑽傳導至晶片㈣自120傳 及曰官月確顯示，然而導線140可減至基板110 及/或晶片120上之結合焊墊（或類似物）。 積體電路元件由模製材料15() 可將該等結構固定於1中 展才接衣材枓1M) 支撐。萨麵+钕-/, 一亚為和肢电路元件100提供結構 侧。焊料凸塊16〇 基板110之反對 , 賴，此料他結敎可件⑽絲於其他 〇 應理解，焊料 =日乂進订封裳，以供後續使用。 r?憶4==;=;= 至主機系統之平板型端子。 、、 编接 - ^可將多個分離隔離結構145形成於導雄14Λ u 繞其相應截面部分。位於此多個分上，以環 • 導線立β八-T 隹^離結構145之間的 ® 」y 如圖6及7所不，導綠卜夕八^ _ 充當間隔件或分隔裝置，以減小離結構145可 硪j牙、岫之導線140之間出現 200849434 28264pif.doc 短绛之可能性。更具體而言’形成於緊鄰之導線i4〇上之 分離隔離結構145可充當分隔裝置，崎顧 電路⑽之模製製程導致某些導線14Q偏轉並觸及=肢 . 導線（例如因導線較細）B寺，分離隔離結構145用二之 • ^離作狀分隔結構，以防止緊鄰之導線之間出現雷$具 路，進而提高高度積體化之積體電路100、且尤其 各導線緊密相間及/或導線極細之高度積體化電路：；： 〇 性。 屯略之可靠 圖2是積體電路元件1〇〇之示意性剖視圖，
元件⑽包含堆疊於其上面之第—晶片12G及第^路 130’其中第二晶片13〇小於第一晶片12〇。如圖：片 —步顯示，第一晶片12〇與第二晶片13〇藉由黏合 ， 互耦接於一起。第一組導線ΐ4θΑ將第一晶片l2〇 目 至基板Π0。第二組導線140B將第二晶片13〇電連接=接 板110。多個第一分離隔離結構145A位於第一組導線基 〇 上，以環繞其截面部分。多個第二分離隔離結構l45B A 於第二組導線140B上，以環繞其截面部分。 位 相應地，第一導線140A與第二導線140B於垂直方。 上相互緊鄰，因而在形成模製材料15〇時可導致緊鄰= ^ 線偏轉，假若不於第一導線140A與第二導線14〇b上八‘ . 形成分離隔離結構145A與145B，此可導致出現電=別 路。此外，第一導線140A與第二導線140B可根據所$紐 「凸塊正向（bump_f0rward)」結合製程形成，於此 中，首先將導線結合至晶片120或130上，然後再蛛八° 200849434 28264pif.doc Ο υ 暴板liu上。因此，形成於第一導線14〇Α/第二導線14犯 上之为離隔離結構145Α/145Β可防止緊鄰之導線（包括橫 向緊鄰之導線與垂直緊鄰之導線二者）之間出現電氣短 路。此外，分離隔離結構145Α/145Β亦可降低導線可能與 第一晶片120及第二晶片130之表面發生短路之可能性了 圖3是積體電路元件200之示意性剖視圖賣 元件·包含分卿成於基板110上之第_晶片 二晶片现，其中第一晶片220與第二晶片23〇之尺；: 致相同。如圖3所進-步顯示’第—組導線2佩將第一 晶片220電連接至基板UQ，而第二組導線2娜將第二曰 片曾230電連接至基板nQ。根據圖3，第—導線2彻第= '刀別+包含形成於其上面之多個分離隔離結構 245Α/245Β，以藉由充當緊鄰（垂直方向及/或棒向）導線 :之置而降低彼等導線之間出現電氣短路之可能 性。如圖3所進-步顯示，第一晶片22〇 _ 藉由炎層221隔開，夾層功可充當用於隔^：日片= 弟二晶片之垂直分隔裝置，以使藤將晶片綠接=基板 110之相應導線，具有足夠空間 土 日雍捏埶UL ^ 口口至晶片22〇及23〇 亡相私墊。此外，圖3所示之結合製程亦 知、圖2所述之凸塊正向製程來達成。 / 圖4是積體電路元件3〇〇之示意性 元細包含堆疊於基板u。上並藉由黏合見 之弟-晶請與第二晶片33〇 二層二5 “1 第一晶片320藉由上面带忐古少/n、 所進一步顯不， 上面$成有多個分離隔離結構345A之 200849434 28264pif.doc 第一組導線340A電連接至基板110。第二組導線34〇b 第二晶片330電連接至基板11〇。第二組導線34〇b上分 形成有多個分離隔離結構345B，此可降低在緊鄰之 • (垂直緊鄰或橫向緊鄰）之間出現電氣短路之可能性。 應理解，形成於導線上之分離隔離結構345A/345B亦 可降低相應導線與晶片相應表面在其外邊緣處出現電 路之可能性。具體而言，圖4所示之結合方法採用所謂之 〇 「凸塊反向（bumPreverse)」結合製程，其中導線首先結 合至基板110上之焊墊343，然後再結合至相應晶片32〇 或330之外邊緣之焊墊。應理解，此種凸塊反向製程可辦 大導線可能與第-晶片320及第二晶片33〇之相應表面^ 生紐路之可能性（假若不包含分離隔離結構345A/345b)。 圖5疋積體電路元件400之示意性剖視圖，積體電路 元件400包含堆疊於基板41〇上之第一晶片42〇與第二晶 片430。如圖5所進一步顯示，第一組導線44〇A將基板 41〇電耦接至位於第一晶片420之下表面上之結合焊墊 1 442。如圖所示，結合焊墊442位於第一晶片420之下表面 之中央部處。此外，第二組導線44〇B將基板41〇電耦接 至位於第一晶片430之上表面上之居中結合焊墊44〇B。
• 如圖5所進一步顯示，第二導線440A及第二導線440B 上分別开>成有多個分離隔離結構445A/445B。如本文所 述’分離隔離結構445A/445B可環繞其所在導線 440A/440B之相應截面部分，以充當分隔裝置，藉以使導 線較不易與緊鄰（垂直緊鄰及/或橫向緊鄰）之導線或其他 13 200849434 28264pif.doc 〇 υ 表面發生短路。應理解，圖5所示之結合佈置亦可根 文參照圖4所述之凸塊反向製程形成。如上文參照圖|上 7所述，導線上之分離隔離結構445可充當間隔件^八^ 裝置，以降低緊鄰之導線440間發生短路之可能性〜。刀隔 圖8是分離隔離結構845之示意圖，分離隔離 形成於導線840上，以環繞導線84〇之相應截面部分。』 體而言，分離隔離結構845之外侧形狀可實質上呈 /、 此外，沿線846截取之分離隔離結構845之剖視圖顯=° 截面實質上呈環形’如圖1GA所示。具體而言，目1〇^ 示分離隔離結構845之外側形狀δ47及内侧形狀g : 質呈圓形且同轴地形成。此外，内側形狀848所 ：： 部區域通常被導線840佔據，分離隔離結構科5於 截面846之部分處環繞導線請。此外嗜於分離隔离^ 構84S之邊緣附近之截面849之直徑小於在中央部處： 取之截面。 戳 圖9是形成於導線940上之分離隔離結構945之示音 ，’其中於根據本發明之某些實施例中，分離隔離結構^ 二有實質橢圓形狀。具體而言，形成於導線94()上之分 1結構94 5之橢圓形狀環繞導線9 4 〇之相應截面部分，
中二供如圖!所"Γ之貫質橢圓形環形形狀。此外，如圖10B 所截=2^%形分離隔離結構945於其中央部946處 ^取之截面大於橢_分義離賴94 附攻所截取之截面直#。 ^ I %/ 圖11是根據本發明之某些實施例，多個緊密相間之導 14 200849434 28264pif.doc 線1141之示意圖，此 間隔更寬且上面形#、夕^固導線1141與緊鄰之多個導線之 儘管圖中顯示僅有個分離隔離結構1145。應理解， 間之導線1141上個分離隔離結構Π45形成於緊密相 可形成更多之隔離結、；^於根據本發明之某些實施例中，亦 根據圖11，緊滋 密，從而使各分離隔線1141彼此之間隔足夠緊
(j 線1141上。此外，—、、^構1145 一同形成於緊密相間之導 與緊鄰之-組緊密相間^相間之導線1141定義為一組 此，形成於緊鄰之—㈣力‘ 1141間隔更寬之導線。因 、、、緊忿相間之導線1141上之分離隔離 11 -夕/他分離隔離結構1145分離開。因此，圖 導線ml中^隹隔離結構1145各別環繞於一組緊密相間 柳、… 所有導線之一個相應截面部分。此外，緊 =緊密相間之導線上已形成有相應之分離隔離結構 ’此可用作使其與緊鄰之各組緊密相間導線1141隔離 之分隔裝置。 一圖12是其間具有實質相等間隔1249之導線組1241 之示思圖。包含於導線組丨241中之各該導線U40上已形 成有分離隔離結構1245，分離隔離結構1245環繞導線組 241中包§之各‘線之相應截面部分。因此，導線 與導線組1241之間隔1249被選擇成能形成分離隔離結構 1245，以環繞導線組1241中各該導線之相應截面部分。 圖13是導線1341之示意圖，導線1341上形成有相應 之分離隔離結構1345，以環繞各該導線1341之相應截: 15 200849434 28264pif.doc 部分。此外，形成於緊鄰之導線1341上之分離隔離結構 1345相互偏置，從而形成z字开>圖案穿過各導線，如線 1343及1344所示。 圖14是根據本發明之某些實施例，包含記憶元件之記 憶卡700之示意圖，記憶元件中具有導線，導線上形成有 分離隔離結構。根據圖14，非揮發性記憶體控制器710可 協調記憶卡7⑻之總體操作，包括用以因應來自控制器710 之命令而儲存及擷取資料之記憶體720之操作。此外，記 憶體720包含記憶元件，此等記憶元件如本文所述進行封 裝且包含根據本發明某些實施例所述在上面形成有分離隔 離結構之導線。 ，
圖14所示記憶卡700符合一「形體因婁丈（form-factor)」 (即記憶卡之實體尺寸及形狀），以提供多媒體卡 (Multi-Media Card ; MMC)、安全數位記憶卡（secure Digital memory card)、記憶棒（Memory Stick)等，其尺 寸及形狀使此等記憶卡能夠與其他相容元件（例如讀卡器） 一起使用。如熟習此項技術者所知，SD代表MMc標準之 較新開發之版本，此可使MMC相容記憶卡與SD相容元 件一起使用。根據本發明之某些實施例，MMC/SD形體因 數相容元件之尺寸為約32mmx約24mmx約1.4mm。MMC 才示準與SD標準進一步論述於全球資訊網之 「www.mmca.org.」網站中。 圖15是包含處理器電路810之電子系統800之示意 圖’處理器電路810用以透過耦接至揮發性記憶體系統 16 200849434 28264pif.doc 820、輸入/輸出系統介面830及非揮發性記憶體系統835 之匯流排840來協調電子系統8〇〇之總體運作。記憶體系 統820及非揮發性記憶體系統835可包含記憶元件，此等 記憶元件如本文所述進行封裝，且包含根據本發明某些實 施例、如本文所述在上面形成有分離隔離結構之導線。 Ο ο 圖16-18是根據本發明某些實施例，用以於積體電路 元件之導線上形成分離隔離結構之方法之示意性剖視圖。 根據圖16，第一晶片120及第二晶片130安裝於基板11〇 上。第一晶片120藉由黏合劑層115固定於基板η〇上， 第一曰曰片130藉由第二黏合劑層固定於第一晶片120 上。如圖16所示，第一晶片12〇大於第二晶片13〇。如在 ，、16中所進一步顯示，第一組導線140Α將第一晶片12〇 電，接至基板H0 ±之結合焊墊。第二組導線14〇β將第 ^晶片130電連接至基板11〇上之第二組結合焊墊。應理 解，可根據任一習知製程提供圖16中所示之結構。〜 程來根ίΠ根據本發明之某些實施例，提供預處理製 =八^」導線140A及刚之表面，以準備接收用於 =構之隔離材料。舉例而言，於根據本發明 例中’可利用氬氣或氮氣作為氣氛環境，藉由 製程。於根據本發明之其他實施例 硬制來提供此預處理製程。應理解，預處 4二張力欲沉積於導線上之隔離版 分離Ρ5離幢牛柄材料之間之表面張力下降可促進 口構，以更規則之間隔形成於導線上並具有更規 17 200849434 28264pif.doc 則之形狀（例如橢圓形、圓形等等）。 一：f麵預處理製程之後，可使隔離材料液分佈於積 ，琶路上以沉積於導線】40A及140B上，藉以形成、 綠結構。具體而言，於根據本發明之某些實施例中， Ο ο 至導線之隔離液可包含具有樹脂基之聚合物、森 強劑、硬結觸媒及溶劑。於根據本發明之某些實施曰 ^1基脰树月曰可包含聚酿亞胺樹脂、丙稀酸脂、& 月旨和/或聚魏_。應理解，可於_液中包含 增強樹脂，以促_離液結合至導線上。3、 如，發明之發明者所瞭解，可利用液體隔離材料之粦 :;二二::成之分離隔離結構之外側形狀。具體而言： rid /促使分離隔離結構具有更均勻之形狀， 發日隹離隔離結構則可能變大。如本發明之 r 、· v瞭解，隔離液之黏度可介於約幾十厘泊 竿中cps)至約幾百cps範圍内。於根據本發明之 ί二=?度可介於約10⑽ 2〇ePSM k4s|^—些實施例中，此黏度可介於約 物-部分之溶劑來;=产應二解，可利用上述作為聚合 溶劑2可關轉述範圍， 可利用熱處理、紫外145Α及145Β之後’ ‘二捏tlf隔離結構經歷硬結製程。於此硬結製程 …揮掉^合物中所包含之溶劑。於根據本發明之 18 200849434 28264pif.doc 某二Λ知例中，〉谷劑之揮發溫度可低於隔離材料之硬纟士旧 t更根據本發明之某些實施例中，環氧^ 20(TC '料％ C，而聚^亞胺樹脂之硬結溫度則約為 2根據本發明之再—些實施例中，可提供多個分離 硬^程，其中第—硬結製程僅被提供用於揮發掉溶劑，. 而弟-硬結製程則被提供作為用於封裝積體電路之 Ο 分T而言，如圖18所示，於基板上形成模製 =:，以覆蓋導線及形成於導線上之分離隔離結構。 後，便可實施第二硬結製程，藉以完成模 衣材枓之形細及提供上述練亞_脂之硬結溫度。 結構之貫舰隔離材料相關聯之實舰參數。具體而古，隹 可自D°W C—ng公司購得且被稱作 -I 關聯之參數。於用鄉成本文所述分離 構之貫例性製程期間，於約i至約％廳之壓力 下以兩於基板約4+/-1 mm之高度，噴塗約3+/_。.如^量 之 Dow Corning M〇del 應_77〇〇，以利用 供氬氣電漿處理達約300秒。 刀卞知 =上縣射料紅㈣成厚歧大於導線厚度 ί 不到4G微米的分離隔離結構。此 开了導線上之緊鄰之分離隔離結構之間 形成間隔力為200微米之分離隔離結構。 圖20是顯示形成於用於將晶片53()電減至基板训 19 200849434 28264pif.doc 之導線上之分離隔離結構545之照片，其中導線在形成之 各分離隔離結構之間具有外露部分540。圖21顯示圖2〇 中所示影像之放大圖，其更詳細地顯示形成於導線上的， 分離隔離結構545之規則間隔且其間具有不含分離隔離么士 構540之外露部分。如圖21戶斤進一步顯示，分離隔離^ 545可用作導線與下面基板表面之間的分隔裝置，以 線發生電氣短路。 Ο
圖22顯示截面照片，其突出顯示藉由如上文參照圖 16_18所述利用氬氣電漿預處理製程形成分 ⑷而防止緊鄰之導線·之間相互電氣短路。_+構 如圖23及24所示 〇之外侧形狀可 乂據^於形成分離隔離結構545之隔離液的粘度而異。且 脰而g，如圖23所示，分離隔離結構545可具 ^ =狀。相比之下，圖24所示之分離隔離 促=科側縣，此可如上文所域由提高錢來加以 積體ΐί文所述，於根據本發明之某㈣施例中，包含於 之八=路轉中之導線上可形成有分離隔離結構 匕 結構可環繞導線之相應截面部分，此作^ =1少與在各導線（或其他組件）之t具有t互短路’ 兀件相關聯之缺陷。於根據本發 之間距 離隔離結構可具有實f呈球形之外例:二，中，分 之其他實施例中，分 於根據本發明 中77娜雜構可具有實__之外側 20 200849434 28264pif.doc V、，八鄭/千、# 二貝犯1夕丨』甲，分離隔離結構之 間隔可實質上相等，此外，位於分離隔離結構之間的 之外露部分亦可實質上相等。 、'― 雖然本發明已以較佳實施例揭露如上’然J:並非用乂 發明’任何熟習此技藝者，在不脫料發明之精= t耗圍内，當可作些許之更動與潤飾，因此本發明之 範圍當視後附之申請專利範圍所界定者為準。 Γ ο 【圖式簡單說明】 降立！ ^疋根據本發明某些實施例之積體電路元件之示音 中==，體電路^包含安裝於基板上之晶片二 隔^構猎由導線相互電性連接，導線上形成有分離 晶片堆疊於積 導線上形成有分離隔離結構，由¥線笔性連接至基板， 性剖些實施例之積體電路元件之示意 等晶片堆疊於積H路多個相同尺寸之晶片，此 板’導線上形成有分離隔離結構1由導線電性連接至基 圖4是根據本發明某此麻 =，此積體電路元;體電路元件之示意 曰曰片堆豐於積體電路其 二—相同尺寸之晶片，此二 導線上形成有麵^結構i料轉電餘接至基板， 200849434 28264pif.doc 圖5疋根據本發明某些實施例之積體電路 性剖視圖，此積體電路元件包含二相同尺寸之 不意 ”於積體電路基板上並藉由導線而電：連拄此二 板，導線上具有分離隔離結構。 至基 圖6是根據本發料些實補，μ 】積體電路基板之導線之照片，導線上形成有分ς隔: Ο ，7是圖6所示根據本發明某些實施例之 圖、更絆細地例示分離隔離結構。 …之近视 ㈣ί 8是根據本發明某些實施例之隔離結構之干土 此IW碓結構具有實質呈球形之截面。 不忍圖， &根據本發料些實施例之分離崎 。刀離隔離結構具有實質呈橢圓形之截面、。不意 ^及_是根據本發明某些實施例具有〜 /之为離隔離結構之球形截面及擴 =貝％形 圖Π是根據本發明某此實 ，面之·圖。 圖’其中與各組之間的間隔她' =且干=導線之示意 此相間报窄，且其中導線上形成有隔^導線均彼 圖12是根據本發明某些實 I構。 線實際上彼此等間距且具有環之示意圖，各導 個分離隔離結構。 〜線之截面部分之單 圖13是根據本發明某此警 上形成有分離隔離結構—、=之導線之示意圖，導線 離隔離結構形成Z字形圖案〔成於相互緊鄰之導線上之分 200849434 28264pif.doc 圖14是根據本發料些實關之記 記憶卡包含射具料.域元件，料^有圖: 隔離結構。 ^战有刀離 圖1：)是根據本發明某些實施例之電子系一土 電子系統包含其中形成有導線之記憶元件，導 形成有分離隔離結構。 ¥線上 Ο Ο 人，KM是根據本發明某些實施例，用以於其 3之導線上形成分離隔離結構 、/、斤匕 图1〇曰本故甘θ 傅又万忐之不思性剖視圖。 .,f "疋、口 ’/、_示與可用於提供根據本發明羊此一 _之分雜離結構之隔離材料相關之 ^某上貫 圖20是根據本發明某些實施例之導線之^值遂 形成有分離隔離結構。 …、片，V線上 圖21是圖20之更詳細之視圖，豆中且 某些實施例之導線，導線上形成有分__構據本發明 線截面之照m形成有分離隔離結構。件中¥ 圖23是顯示根據本發明某&實絲 之外側形狀之^。 例之分離隔離結構 圖24是顯示根據本發明某些實施例之 之外側形狀之照片。 刀離隔離結構 【主要元件符號說明】 1〇〇 ： ^ 知體電路元件 110 ··基板 115 ·黏合劑層 23 200849434 28264pif.doc 120 :第一晶片 125 :第二黏合劑層 130 :第二晶片 140 :導線 • 140a :第一組導線 • 140b :第二組導線 145 :分離隔離結構 145a :第一分離隔離結構 145b :第二分離隔離結構 150 :模製材料 160 :焊料凸塊 2⑻：積體電路元件 220 ··第一晶片 221 :夾層 230 ··第二晶片 240a :第一組導線 240b :第二組導線 245a ·分離隔離結構 245b :分離隔離結構 300 :積體電路元件 ^ 320 ··第一晶片 • 325 :黏合劑層 330 :第二晶片 340a :第一組導線 24 200849434 28264pif.doc 340b :第二組導線 343 :焊墊 345a :分離隔離結構 345b :分離隔離結構 400 :積體電路元件 410 :基板 420 :第一晶片 430 :第二晶片 440a ··第一組導線 440b :第二組導線 442 :結合焊墊 445a :分離隔離結構 445b :分離隔離結構 510 :基板 530 :晶片 540 :外露部分 545 :分離隔離結構 545a ··分離隔離結構 700 :記憶卡 710 :非揮發性記憶體控制器 720 :記憶體 800 :電子系統 810 :處理器電路 820 :揮發性記憶體系統 25 200849434 28264pif.doc 830 輸入/輸出系統介面 835 非揮發性記憶體系統 840 匯流排 845 分離隔離結構 846 線 847 外侧形狀 848 内側形狀 849 截面 940 導線 945 分離隔離結構 946 中央部 947 邊緣部 1141 :導線 1145 :分離隔離結構 1240 :導線 1241 :導線組 1245 :分離隔離結構 1249 :間隔 1341 :導線 1343 :線 1344 :線 1345 :分離隔離結構 26

Claims (1)

  1. 200849434 28264pif.doc 十、申請專利範圍： 1. 一種半導體元件，包含： 基板，位於所述半導體元件中； 晶片，位於所述基板上； 導線，電库禺接至所述晶片，以及 多個分離隔離體結構，位於所述導線上並環繞所述導 線之相應截面部分。 2. 如申請專利範圍第1項所述之半導體元件，其中所 述導線之位於所述多個分離隔離體中緊鄰之分離隔離體之 間的部分，實質上不含有所述分離隔離體結構。 3. 如申請專利範圍第1項所述之半導體元件，其中所 述分離隔離體結構之截面部分包含環形形狀。 4. 如申請專利範圍第1項所述之半導體元件，其中所 述分離隔離體結構組成形狀，包含在所述形狀之中央的直 徑，大於毗鄰所述形狀之邊緣之直徑。 5. 如申請專利範圍第1項所述之半導體元件，其中所 述分離隔離體結構包含實質呈球形之外侧形狀。 6. 如申請專利範圍第1項所述之半導體元件，其中所 述分離隔離體結構包含實質呈橢圓形之外側形狀。 7. 如申請專利範圍第1項所述之半導體元件，其中所 述多個分離隔離體結構沿所述導線以貫質相等之間隔相 間，藉以於其間界定所述導線之實質相等之外露部分。 8. 如申請專利範圍第1項所述之半導體元件，其中所 述多個分離隔離體結構之截面中央之厚度實質相等。 27 200849434 28264pif.doc 9·如申請專利範圍第1項所述之半導體元件，其中所 述導線包含第一導線，所述元件進一步包含： 緊鄰所述第一導線之第二導線，其中所述多個分離隔 離體結構之每一者，皆位於所述第一導線及所述第二導線 ‘ 之毗鄰截面部分上並環繞所述姉1：鄰截面部分。 • · 10·如申請專利範圍第9項所述之半導體元件，其中所 述第一導線及所述第二導線包含一組導線，且其中包含於 f 所述/組導線中之所述導線之間隔’小於所述一組導線與 緊鄰之/組導線之間隔。 u•如申請專利範圍第1項所述之半導體元件，其中所 述導線包括包含於多個導線中之一導線，所述元件進一步 包含： 位於所述多個導線中每一所述導線上之相應多個分離 隔離體結構，其中緊鄰之導線之被環繞截面部分相互偏置。 12·如申請專利範圍第1項所述之半導體元件，其中所 述晶片包含第一晶片，所述元件進一步包含： V 第>晶片，位於所述元件中之所述第一晶片上；以及 第二導線，直接於所述第一導線上方電耦接至所述第 二晶片，其中所述第一導線及所述第二導線各自包含分別 環繞戶斤述第一導線及所述弟一導線之截面部分之相應多個 - 分離隔離體結構。 • 13·如申請專利範圍第12項所述之半導體元件，其中 所述第/導線及所述第二導線利用正向凸塊製程或反向凸 塊製蘀分別耦接於所述第一晶片及所述第二晶片與所述基 28 200849434 28264pif.doc 板之間。 14·一種電子系統，包含·· 處理器，用以協調電子系統之操作； 系統介面，電耦接至所述處理器， 器與外部系統之間的通訊；以及 扠仏所述處理 料接至所述處理器且包含至少―個 件，所述至少一個記憶元件包含： 凡
    υ 晶片，位於所述記憶元件之基板上； $線’電輕接至所述晶片；以及 夕们刀離隔離體結構，位於所述導線上且環繞所 述導線之相應戴面部分。 15· —種^己憶卡，包含·· 非揮發性記憶體控制器，用以協調所述 操 作；以及 圮憶體，電耦接至所述非揮發性記憶體控制器，包含 軍，性記憶體，所述非揮發性記憶體包含·· 曰=片，位於所述非揮發性記憶體之基板上； ^線，電耦接至所述晶片；以及 綠個刀離隔離體結構，位於所述導線上並環繞所述導 、、、之相應截面部分。 16·、7種用於隔離半導體元件中之導線之方法，包含·· 於導線上形成多個分離隔離體結構，以環繞所述導線 又相應截面部分。 η· 一種用於隔離半導體元件中之導線之方法，包含： 29 200849434 28264pif.doc 預處理輕接於晶片與基板之間的導線，以減小所 線與欲沉積於所述導線上之材料之間的表面張力，藉以提 供經預處理之導線；以及 曰 在所述經預處理之導線上形成包含所述材料之多個八 離隔離體結構，以環繞所述導線之相應截面部分。
    ϋ 18·如申請專利範圍第17項所述之用於隔離半導體元 件中之導線之方法，其中所述預處理包括實施包含Ar 之電漿處理。 、 19·如 、、#專利範圍第項所述之用於隔離半導體元 件中之導線之方法，其中祕理包括濕式製程。 20.如申請專利範圍第17項所述之用於隔離半導體 件之方法，其中形成多個分離隔離體結構包括對 所述V線應用隔離液，所述隔離液包含： 聚合物，包含基體樹脂、黏合 以及溶劑。 更結觸媒、 件中ί導圍第2〇項所述之用於隔離半導體元 π烯酸;^，，其巾所4絲_包含聚M亞胺樹 1麵、物編。 件中之導線之2G項所述之用於隔離半導體元 量計少於約5〇%之有機包含按所述聚合物之重 件中之導線之乾圍第18項所述之用於隔離半導體元 〆 ，進_步包含· 於约200攝氏戶 · 又^度下對所述多個分離隔離體結構 30 Ο ϋ 200849434 28264pif.doc 實施硬結處理。 24·女口中含杳^ ^ 件中之導線2太、、I砘圍第18項所述之用於隔離半導體元 、 ^ ，進一步包含·· 處理。,〃輻射對所述多個分離隔離體結構實施硬結 件中之導線^^目帛18項所述之驗隔離半導體元 、，、 万法，進一步包含·· 發掉用於離體結構實施第—硬結處理，以揮 對所述多個離隔離體結構之溶劑；並且隨後 之第二硬體結構f施包含環氧模製化合物 述多嶋:離體==物用於提供塗覆於所 於約叫氏度之 —硬結處理包括於高 27.如申請專利範圍；;項=^ 件中之導綠夕古、i_ 口弗18項所述之用於隔離半導體元 包括對所述導線塗覆ί =成^多個分離隔離體結構， I隔離液，所述隔離液包含： 以及^丨。基體樹脂、黏合強度增強劑、硬結觸媒、 件中:範圍第25、項所述之用於隔離半導體元 脂、丙物m、w胺樹 31
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KR100874925B1 (ko) 2008-12-19
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KR20080106786A (ko) 2008-12-09
US20080296780A1 (en) 2008-12-04

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