CN105845587A - 半导体结构及其制法 - Google Patents

半导体结构及其制法 Download PDF

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Publication number
CN105845587A
CN105845587A CN201510019414.3A CN201510019414A CN105845587A CN 105845587 A CN105845587 A CN 105845587A CN 201510019414 A CN201510019414 A CN 201510019414A CN 105845587 A CN105845587 A CN 105845587A
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China
Prior art keywords
layer
opening
metal level
preparation
passivation layer
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CN201510019414.3A
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English (en)
Inventor
陈以婕
孙崧桓
张辰安
吴建宏
黄富堂
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN105845587A publication Critical patent/CN105845587A/zh
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    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent

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Abstract

一种半导体结构及其制法，先提供具有多个电性连接垫的晶片，于该电性连接垫上形成金属层，并于部份该金属层上形成钝化层。接着于该金属层上形成导电柱。由于该金属层上有钝化层保护，该金属层可避免底切问题，而能提升导电柱的支撑度，进而提升产品信赖性。

Description

半导体结构及其制法
技术领域
本发明涉及一种半导体结构，尤指一种具有导电柱的半导体结构。
背景技术
随着电子产业的蓬勃发展，电子产品在型态上趋于轻薄短小，在功能上则逐渐迈入高性能、高功能、高速度化的研发方向。而目前半导体晶片的封装形式包含打线式(Wire Bonding)封装或覆晶式(FlipChip)封装等，其中，相较于打线式封装，覆晶式封装更能缩减整体半导体装置的体积。
一般覆晶式封装是将半导体晶片的作用面上藉由导电凸块结合至封装基板的电性连接垫上，再填入底胶于该半导体晶片的作用面与封装基板之间，以包覆该导电凸块。而为了增加覆晶的对位精确性，导电凸块的组成材质则显得非常重要。
现有提供半导体晶片利用铜柱作结合的技术，可参阅图1A至图1D。
如图1A所示，提供一具有多个电性连接垫100的晶片10(本图仅以一电性连接垫说明)，其外表面是由氮化硅(SiN)层101所构成，且该氮化硅层101藉由开孔外露该电性连接垫100。接着，形成介电层12于该氮化硅层101及开孔壁面上，再形成钛(Ti)层11于该介电层12的全部表面及该电性连接垫100上，又形成铜(Cu)层13于该钛层11的全部表面上。
如图1B所示，形成阻层14于该铜层13上，且于该阻层14上形成开口区140，以外露部分铜层13。接着，形成铜柱15于该开口区140中的铜层13上，再形成焊锡材16于该铜柱15的顶面。
如图1C所示，移除该阻层14，以外露出铜层13。
如图1D所示，利用铜柱15作为止挡部，以蚀刻移除外露的该铜层13及其下方的钛层11。于后续制程中，可于该铜柱15与焊锡材16上形成焊锡凸块以对接至该封装基板(图未示)上，再进行回焊制程，以形成用于固定与电性连接该晶片10与封装基板的导电凸块。
当进行回焊制程时，该铜柱15不会变形，故可防止熔融(melt)及崩塌(collapse)，使现有晶片10藉由该铜柱15可避免位置偏移。因此，导电凸块中的铜柱15可增加覆晶的对位精确性。
然而，现有半导体结构的制法中，因利用蚀刻液进行蚀刻具有等向性，故会向内蚀刻。因此，当蚀刻移除该外露的铜层13及其下方的钛层11时，该钛层11会产生底切(undercut)过大的问题(如图1D所示的底切处K)，造成该铜柱15的支撑度不足，导致导电凸块的信赖性不佳而降低产品良率的问题。
因此，如何避免上述现有技术「因底切问题而使信赖性不佳而降低产品良率」的问题，实为当前所要解决的目标。
发明内容
鉴于上述现有技术的缺失，本发明提供一种半导体结构及其制法，可避免底切问题，而能提升导电柱的支撑度，进而提升产品信赖性。
本发明的半导体结构的制法，包括：提供一具有多个电性连接垫及保护层的晶片，其中，该保护层具有多个保护层开口以外露部份该电性连接垫；于该保护层上形成电性连接该电性连接垫的金属层；形成第一钝化层于部份该金属层上，再于该第一钝化层中形成多个第一开口以外露部份该金属层；形成多个导电柱于该第一开口中的该部份外露的金属层上；以及移除部分的该金属层，以保留该导电柱及该第一钝化层下的金属层。
本发明还提供一种半导体结构的制法，包括：提供一具有多个电性连接垫及保护层的晶片，该保护层具有保护层开口以外露部份该电性连接垫；于该保护层上形成电性连接该电性连接垫的金属层，并外露部份该保护层；形成第一钝化层于部份该金属层及保护层上并包覆该金属层的侧面，再于该第一钝化层中形成多个第一开口，以外露部份该金属层；以及形成多个导电柱于该第一开口中的该部份外露的金属层上。
本发明再提供一种半导体结构，包括：晶片，其具有保护层及多个外露的电性连接垫，该保护层具有保护层开口以外露部份该电性连接垫；金属层，其形成于该保护层上并电性连接该电性连接垫；第一钝化层，其形成于该金属层上，并具有多个第一开口以外露部份该金属层；以及多个导电柱，其形成于该第一开口中的部份外露的该金属层上，以电性连接该金属层。
由上可知，本发明的半导体结构及其制法，接置于导电柱下的金属层由于有钝化层保护，因此在进行后续制程(如蚀刻)时，该金属层可避免底切(undercut)过大的问题，可提供导电柱足够的支撑度，在形成用于固定与电性连接该半导体结构与封装基板的导电凸块后，该导电凸块的信赖性佳，产品良率因而得以提升。
附图说明
图1A至图1D为现有半导体结构的制法的剖面示意图；
图2A至图2G”为本发明半导体结构的制法的一实施例的剖面示意图；以及
图3A至图3F”为本发明半导体结构的制法的另一实施例的剖面示意图。
符号说明
10,20 晶片
100,200 电性连接垫
101 氮化硅层
11 钛层
12 介电层
13 铜层
14,23,29 阻层
140 开口区
15 铜柱
16,251 焊锡材
2,2’,2” 半导体结构
201 保护层
2010 保护层开口
21' 金属材料
21,21a 金属层
211,221 侧面
22,22',26,28 钝化层
220,260,280 钝化层开口
230 阻层开口
24 导电柱
25 导电材
250 镍材
27 线路重布层
D1,D2 宽度
K 底切处。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“顶”、“侧”、“第一”、“第二”及“第三”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2G，其为本发明半导体结构的制法的一实施例的剖面示意图。
如图2A所示，先提供一具有例如铝(Al)材的多个电性连接垫200及保护层201的晶片20。于一实施例中，该晶片20可为晶圆中的多个晶片的一者。于本图中，仅略以具有一电性连接垫200及保护层201的晶片20说明之，该晶片20的外表面是由例如为氮化硅(SiN)的保护层201所构成，该保护层201具有一保护层开口2010以外露部份该电性连接垫200。然，有关晶片结构的种类繁多，且为业界所熟知，故不再赘述。
如图2B所示，形成材质例如为钛(Ti)及铜(Cu)的金属层21于该保护层201及其外露部份的该电性连接垫200上，该金属层21电性连接该电性连接垫200。于一实施例中，该金属层21以溅镀(suptter)方式形成。
如图2C所示，形成钝化层(passivation)22于部份该金属层21上，该钝化层22具有钝化层开口220，以令部份该金属层21外露于该钝化层开口220中。其中，该钝化层开口220的位置相对位于该保护层开口2010上方，且该钝化层开口220的宽度大于或等于该保护层开口2010的宽度。
于一实施例中，该钝化层22除了外露该钝化层开口220中的该金属层21外，更外露该金属层21的其他部份，即该钝化层22仅形成于部份该金属层21上，使得多个电性连接垫200的两相邻者之间的第一钝化层22为不连续，且该钝化层22的宽度以5～10μm较佳。
如图2D所示，形成例如为光阻的阻层23于该金属层21及该钝化层22上，再利用曝光显影的方式形成阻层开口230，以外露该金属层21的部份表面，而该阻层开口230对应形成于该钝化层开口220的上方。于一实施例中，该阻层开口230的宽度大于该钝化层开口220的宽度，以外露部份该钝化层22及该钝化层开口220中的部份该金属层21。
如图2E所示，以电镀方式形成导电柱24于该阻层开口230中的部份该钝化层22及金属层21上。于本实施例中，该导电柱24为铜柱。而由于该阻层开口230的宽度大于该钝化层开口220的宽度，因此在形成导电柱24时，部份该钝化层22会嵌埋入导电柱24中。
此外，也可形成导电材25于该导电柱24的顶面上。于本实施例中，该导电材25可由镍(Ni)材250及焊锡材251所组成。
如图2F所示，移除该阻层23，以外露未被该导电柱24及该钝化层22所覆盖的部份金属层21，且还外露未被该导电柱24所覆盖的部份钝化层22。
如图2G所示，蚀刻移除未被该导电柱24及该钝化层22所覆盖的部份金属层21，以保留该导电柱24及该钝化层22下的金属层21a，并部份外露该保护层201，以取得一种半导体结构2。其中，未被蚀刻移除而保留的金属层21a的宽度D1大于该导电柱24的宽度D2。另未被移除而保留的金属层21a的侧面211与该钝化层22的侧面221齐平。
于后续制程中，可于该导电柱24与导电材25上形成焊锡凸块，以对接至封装基板(图未示)，再进行回焊制程，以形成用于固定与电性连接该半导体结构与封装基板的导电凸块。
于另一实施例中，在提供如图2A所示的晶片20后，如图2G’所示，可先于该保护层201及电性连接垫200上形成钝化层26，该钝化层26包覆该保护层201，且具有钝化层开口260以外露部份电性连接垫200。接着于该钝化层26及该钝化层开口260中的该电性连接垫200的外露部份上，以溅镀方式形成金属层21。之后的制程相同于前述图2C至图2G所示，于此不再赘述。
于另一实施例中，在形成如图2G’所示的钝化层26后，可先形成线路重布层27(Re-Distribution Layer,RDL)于该钝化层26及该钝化层开口260所外露的部份该电性连接垫200上，如图2G”所示。接着于该线路重布层27上形成钝化层28，该钝化层28具有钝化层开口280，以外露部份该线路重布层27。之后于该钝化层28及该钝化层开口280所外露的部份线路重布层27上，以溅镀方式形成金属层21。之后的制程相同于前述图2C至图2G所示，于此不再赘述。于本实施例中，钝化层开口260、280二者位置为错位，如此一来即能达成移动接点位置的目的，能够使用更密集的布线方式。
请参阅图3A至图3F，其为本发明半导体结构的制法的另一实施例的剖面示意图。于本实施例中部份制程相同于前述如图2A至图2G”所示，以下仅说明不同处，相同制程的步骤于此不再赘述。
如图3A所示，其步骤为接续前述图2A之后。首先，形成金属材料21’于该晶片20的电性连接垫200与保护层201上，接着该金属材料21’上形成阻层29，并外露部份该金属材料21’。而该阻层29的形成位置为相对于该金属材料21’电性连接该电性连接垫200的上方。
如图3B所示，先以蚀刻方式移除未被阻层29所覆盖的金属材料21’(即移除金属材料21’的外露部份)，再移除该阻层29，可得到剩余的金属材料21’作为金属层21a。
如图3C所示，形成钝化层22于部份该金属层21a及该晶片20的保护层201上，该钝化层22具有钝化层开口220，以令部份该金属层21a外露于该钝化层开口220中。其中，该钝化层22包覆该金属层21a的侧面211，且该钝化层22的宽度以5～10μm较佳。
于一实施例中，该钝化层22除了外露该钝化层开口220中的该金属层21a外，更外露部份该保护层201，即该钝化层22仅形成于部份该金属层21a及该保护层201上，并包覆该金属层21a的侧面211，使得多个电性连接垫200的两相邻者之间的钝化层22为不连续。
于另一实施例中，如图3C'所示，该钝化层22'仅外露该钝化层开口220中的该金属层21a，而该保护层201已被该钝化层22'所覆盖而未外露，即该多个电性连接垫200的两相邻者之间的钝化层22'为连续。
如图3D所示，形成例如为光阻的阻层23于该晶片20的保护层201及该钝化层22上，再利用曝光显影的方式形成阻层开口230，以外露该金属层21a的部份表面，而该阻层开口230对应形成于该钝化层开口220的上方。于一实施例中，该阻层开口230的宽度大于该钝化层开口220的宽度，以外露部份该钝化层22及该钝化层开口220中的部份该金属层21a。
如图3E所示，形成导电柱24及导电材，其制程如前述图2E，于此不再赘述。
如图3F所示，移除该阻层23，即可取得一种半导体结构2，其中，金属层21a的宽度D1大于或等于该导电柱24的宽度D2。本实施例与前述实施例不同之处在于，本实施例的金属层21a在接置导电柱24之前，已先进行蚀刻制程而取得所欲的金属层21a，不同于前述实施例是于在金属层21上接置导电柱24并移除阻层23后，必须经蚀刻制程以取得所欲的金属层21a。
于另一实施例中，在提供如图2A所示的晶片20后，如图3F’所示，可先于该保护层201及电性连接垫200上形成钝化层26，该钝化层26包覆该保护层201，且具有钝化层开口260以外露部份电性连接垫200。接着于该钝化层26及该钝化层开口260中的该电性连接垫200的外露部份上，进行如图3A的形成金属层21a的步骤。之后的制程相同于前述图3C至图3F所示，于此不再赘述。
于另一实施例中，在形成如图3F’所示的钝化层26后，可先形成线路重布层27(Re-Distribution Layer,RDL)于该钝化层26及该钝化层开口260所外露的部份该电性连接垫200上，如图3F”所示。接着于该线路重布层27上形成钝化层28，该钝化层28具有钝化层开口280，以外露部份该线路重布层27。之后于该钝化层28及该钝化层开口280所外露的部份线路重布层27上，进行如图3A的形成金属层21a的步骤。之后的制程相同于前述图3C至图3F所示，于此不再赘述。于本实施例中，钝化层开口260、280二者位置为错位。
本发明还提供一种半导体结构2，如图2G所示，该半导体结构2还包括晶片20、金属层21a、钝化层22及导电柱24。
该晶片20具有例如铝材的多个电性连接垫200及例如为氮化硅(SiN)的保护层201，该保护层201具有一保护层开口2010以外露部份该电性连接垫200。
该金属层21a形成于该保护层201及其外露部份的该电性连接垫200上，以电性连接该电性连接垫200。于一实施例中，该金属层21a的材质例如为钛(Ti)及铜(Cu)。
该钝化层22形成于部份该金属层21a上，该钝化层22具有钝化层开口220，以令部份该金属层21a外露于该钝化层开口220中。
该导电柱24形成于该钝化层开口220中的该金属层21a的外露部份上，以电性连接该钝化层22的该钝化层开口220中的该金属层21a的外露部份。于一实施例中，该导电柱24为铜柱。另该金属层21a的宽度D1大于该导电柱24的宽度D2。导电柱24的顶面形成有导电材25，该导电材25可由镍(Ni)材250及焊锡材251所组成。于其他实施例中，该导电材25可为焊锡材料。
于一实施例中，钝化层22部份嵌埋入该导电柱24中。该钝化层22也可不嵌埋入该导电柱24中，即该导电柱24的宽度D2等于该钝化层开口220的宽度。
于一实施例中，如图2G所示，该金属层21a的侧面211与该钝化层22的侧面221齐平。于另一实施例中，如图3F所示，该钝化层22包覆该金属层21a的侧面211。
本发明再提供一种半导体结构2’，如图2G’、图3F’所示。以下仅说明本实施例的半导体结构2’与前述半导体结构2不同之处，相同部份不再赘述。
该半导体结构2’还包括钝化层26，该钝化层26形成于该晶片20上，即形成于保护层201及金属层21之间，该钝化层26具有钝化层开口260以外露部份该晶片20的电性连接垫200，且包覆该晶片20的保护层201。而该半导体结构2’的金属层21即形成于该钝化层26及钝化层开口260中的该电性连接垫200的外露部份上。
本发明再提供一种半导体结构2”，如图2G”、图3F”所示。以下仅说明本实施例的半导体结构2”与前述半导体结构2’不同之处，相同部份不再赘述。
该半导体结构2”还包括线路重布层27及钝化层28。该线路重布层27形成于钝化层26及钝化层开口260所外露的部份该电性连接垫200上。钝化层28形成于该线路重布层27上，并具有钝化层开口280以外露部份该线路重布层27。于本实施例中，该钝化层开口260、280二者位置为错位。
综上所述，本发明半导体结构及其制法，接置于导电柱下的金属层由于有钝化层保护，因此在进行后续制程(如蚀刻)时，该金属层可避免底切(undercut)过大的问题，可提供导电柱足够的支撑度，在形成用于固定与电性连接该半导体结构与封装基板的导电凸块后，该导电凸块的信赖性佳，产品良率因而得以提升。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (38)

1.一种半导体结构的制法，其特征为，该制法包括：
提供一具有多个电性连接垫及保护层的晶片，其中，该保护层具有多个保护层开口以外露部份该电性连接垫；
于该保护层上形成电性连接该电性连接垫的金属层；
形成第一钝化层于部份该金属层上，再于该第一钝化层中形成多个第一开口以外露部份该金属层；
形成多个导电柱于该第一开口中的该部份外露的金属层上；以及
移除部分的该金属层，以保留该导电柱及该第一钝化层下的金属层。
2.根据权利要求1所述的半导体结构的制法，其特征为，该第一开口的位置为相对位于该保护层开口上方，且该第一开口的宽度大于或等于该保护层开口的宽度。
3.根据权利要求1所述的半导体结构的制法，其特征为，该多个电性连接垫的两相邻者之间的该第一钝化层为不连续。
4.根据权利要求1所述的半导体结构的制法，其特征为，该保留的金属层的侧面与该第一钝化层的侧面齐平。
5.根据权利要求1所述的半导体结构的制法，其特征为，形成该金属层的材质为钛及铜。
6.根据权利要求1所述的半导体结构的制法，其特征为，该导电柱为铜柱。
7.根据权利要求1所述的半导体结构的制法，其特征为，该制法还包括于移除该金属层之前，形成导电材于该导电柱的顶面。
8.根据权利要求1所述的半导体结构的制法，其特征为，该保留的金属层的宽度大于该导电柱的宽度。
9.根据权利要求1所述的半导体结构的制法，其特征为，该制法还包括提供该具有多个电性连接垫及保护层的晶片后，先形成第二钝化层于该保护层及电性连接垫上，还于该第二钝化层中形成多个第二开口以外露部份该电性连接垫，再于该第二开口中的该电性连接垫的外露部份及该第二钝化层上形成该金属层。
10.根据权利要求9所述的半导体结构的制法，其特征为，该制法还包括形成该第二钝化层于该保护层及电性连接垫上后，先形成线路重布层于该第二钝化层及该第二开口中的电性连接垫的外露部份上，接着形成第三钝化层于该线路重布层上，再于该线路重布层上形成该金属层。
11.根据权利要求10所述的半导体结构的制法，其特征为，该第三钝化层具有外露部份该线路重布层的第三开口，且该第三开口及该第二开口的位置为错位。
12.根据权利要求1所述的半导体结构的制法，其特征为，形成该导电柱时将部份该第一钝化层嵌埋入该导电柱中。
13.根据权利要求1所述的半导体结构的制法，其特征为，形成该导电柱的步骤还包括：
形成阻层于该金属层及该第一钝化层上，再于该阻层中形成多个开口，以外露该金属层的部份表面；
于部份外露于该阻层开口中的金属层上形成该多个导电柱；以及
移除该阻层。
14.一种半导体结构的制法，其特征为，该制法包括：
提供一具有多个电性连接垫及保护层的晶片，该保护层具有保护层开口以外露部份该电性连接垫；
于该保护层上形成电性连接该电性连接垫的金属层，并外露部份该保护层；
形成第一钝化层于部份该金属层及该保护层上并包覆该金属层的侧面，再于该第一钝化层中形成多个第一开口，以外露部份该金属层；以及
形成多个导电柱于该第一开口中的该部份外露的金属层上。
15.根据权利要求14所述的半导体结构的制法，其特征为，该第一开口的位置为相对位于该保护层开口上方，且该第一开口的宽度大于或等于该保护层开口的宽度。
16.根据权利要求14所述的半导体结构的制法，其特征为，形成该金属层的步骤还包括：
将金属材料形成于该电性连接垫及该保护层上；
形成阻层于该金属材料上，并外露部份该金属材料；
移除外露的部份该金属材料，以得到该金属层；以及
移除该阻层。
17.根据权利要求14所述的半导体结构的制法，其特征为，形成该金属层的材质为钛及铜。
18.根据权利要求14所述的半导体结构的制法，其特征为中，该导电柱为铜柱。
19.根据权利要求14所述的半导体结构的制法，其特征为，该制法还包括形成导电材于该导电柱的顶面。
20.根据权利要求14所述的半导体结构的制法，其特征为，该金属层的宽度大于或等于该导电柱的宽度。
21.根据权利要求14所述的半导体结构的制法，其特征为，该制法还包括提供该具有多个电性连接垫及保护层的晶片后，先形成第二钝化层于该保护层及电性连接垫上，还于该第二钝化层中形成多个第二开口以外露部份该电性连接垫，再于该第二开口中的该电性连接垫的外露部份及该第二钝化层上形成该金属层。
22.根据权利要求21所述的半导体结构的制法，其特征为，该制法还包括形成该第二钝化层于该保护层及电性连接垫上后，先形成线路重布层于该第二钝化层及该第二开口中的电性连接垫的外露部份上，接着形成第三钝化层于该线路重布层上，再于该线路重布层上形成该金属层。
23.根据权利要求22所述的半导体结构的制法，其特征为，该第三钝化层具有外露部份该线路重布层的第三开口，且该第三开口及该第二开口的位置为错位。
24.根据权利要求14所述的半导体结构的制法，其特征为，形成该导电柱时将部份该第一钝化层嵌埋入该导电柱中。
25.根据权利要求14所述的半导体结构的制法，其特征为，形成该导电柱的步骤还包括：
形成阻层于该保护层及该第一钝化层上，再于该阻层中形成多个开口，以外露该金属层的部份表面；
于部份外露于该阻层开口中的金属层上形成该多个导电柱；以及
移除该阻层。
26.根据权利要求14所述的半导体结构的制法，其特征为，该多个电性连接垫的两相邻者之间的该第一钝化层为连续或不连续。
27.一种半导体结构，其特征为，该半导体结构包括：
晶片，其具有一保护层及多个电性连接垫，该保护层具有保护层开口以外露该电性连接垫；
金属层，其形成于该保护层上并电性连接该电性连接垫；
第一钝化层，其形成于该金属层上，并具有多个第一开口以外露部份该金属层；以及
多个导电柱，其形成于该第一开口中的部份外露的该金属层上，以电性连接该金属层。
28.根据权利要求27所述的半导体结构，其特征为，该金属层的侧面与该第一钝化层的侧面齐平。
29.根据权利要求27所述的半导体结构，其特征为，形成该金属层的材质为钛及铜。
30.根据权利要求27所述的半导体结构，其特征为，该导电柱为铜柱。
31.根据权利要求27所述的半导体结构，其特征为，该金属层的宽度大于或等于该导电柱的宽度。
32.根据权利要求27所述的半导体结构，其特征为，该第一钝化层部份嵌埋入该导电柱中。
33.根据权利要求27所述的半导体结构，其特征为，该第一钝化层包覆该金属层的侧面。
34.根据权利要求27所述的半导体结构，其特征为，该半导体结构还包括第二钝化层，其形成于该保护层与该金属层之间，且该第二钝化层具有多个第二开口以外露部份该电性连接垫。
35.根据权利要求34所述的半导体结构，其特征为，该半导体结构还包括线路重布层及第三钝化层，该线路重布层形成于该第二钝化层及该第二开口中的该电性连接垫的外露部份上，该第三钝化层并形成于该线路重布层上且具有第三开口以外露部份该线路重布层。
36.根据权利要求35所述的半导体结构，其特征为，该第二开口及该第三开口的位置形成为错位关系。
37.根据权利要求27所述的半导体结构，其特征为，该导电柱的顶面还形成有导电材。
38.根据权利要求27所述的半导体结构，其特征为，该第一开口的位置为相对位于该保护层开口上方，且该第一开口的宽度大于或等于该保护层开口的宽度。
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TW201624579A (zh) 2016-07-01
US20190259723A1 (en) 2019-08-22
US10325872B2 (en) 2019-06-18

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