TW200826207A - Chip scale package structure and method for fabricating the same - Google Patents

Chip scale package structure and method for fabricating the same Download PDF

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TW200826207A
TW200826207A TW95146383A TW95146383A TW200826207A TW 200826207 A TW200826207 A TW 200826207A TW 95146383 A TW95146383 A TW 95146383A TW 95146383 A TW95146383 A TW 95146383A TW 200826207 A TW200826207 A TW 200826207A
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conductive
wafer
carrier
layer
trace
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TW95146383A
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TWI313037B (en
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Han-Ping Pu
Chien-Ping Huang
Cheng-Hsu Hsiao
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Siliconware Precision Industries Co Ltd
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Priority to TW95146383A priority Critical patent/TWI313037B/zh
Priority to US11/891,134 priority patent/US7750467B2/en
Publication of TW200826207A publication Critical patent/TW200826207A/zh
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Publication of TWI313037B publication Critical patent/TWI313037B/zh
Priority to US12/788,772 priority patent/US8058100B2/en

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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200826207 九、發明說明： 【發明所屬之技術領域】 • 本發明係有關於一種半導體封裝結構及其製法，尤指 一種晶片級封裝結構及其製法。 【先前技術】 隨著半導體技術的演進，半導體產品已開發出不同封 裝產品型態，而為追求半導體封裝結構之輕薄短小，因而 •么展出種日日片級封裝結構（chip scale package，CSP)，其 ，特徵在於此種晶片級封裝結構僅具有與晶片尺寸相等或略 大的尺寸。 美國專利第 5,892,179、6，1〇3,552、6,287,893、 6,350,668及6,433,427號案即揭露—種傳統之csp結構， 係直接於晶片上形成增層而無需使用如基板或導線架等晶 片承載件，且利用重佈線（redistributi〇n layer, RDL)技術重 配晶片上的銲墊至所欲位置。如第！圖所示，是種csp結 構具有形成於晶片1 〇之作用表面（active surface)丨〇〇上的 .增層，包括：介電層（dielectric layer)n，敷設於晶片1〇 之作用表面1〇0上並開設有複數貫孔11〇，以使晶片1〇上 的銲塾κη藉該貫孔110外露；以及線路層12，形成㈣ 介電層U上並電性連接至晶片1〇上外露的銲塾ΐ(π。該/ 線路層12上復敷設-拒銲層13，並藉複數穿通該拒鮮層 13之開孔13〇使線路層12的預定部分外露而與銲球μ銲 連，以利用該銲球14作為與外界裝置電性連接之輸入/輸 出端。 19806 5 200826207 然而上述CSP結構之缺點在於重佈線技術之施用或 佈δ又於晶片上的導電跡線往往受限於晶片之尺寸或其作用 表面之面積大小，尤其當晶片之積集度提昇且晶片尺寸曰 趨=小的情況下，晶片甚至無法提供足夠或更多表面區域 以安置較多或更多數量的銲球俾供有效與外界電性連接之 用0 ，鑑此，美國專利第6,271，469號案揭露另一種於晶片 上形成增層的封裝結構，得提供較為充足或較多的表面區 域以承載較多或更多的輸入/輸出端或銲球。如第2圖所 示，是種封裝結構利用一封裝膠體25包覆住晶片2〇之非 作用表面202及側面203,而使晶片2〇之作用表面2〇〇外 2且與封裝膠體25的表面250齊平。然後，敷設一第一介 電層26於晶片20之作用表面2〇〇及封裝膠體25的表面 250上’並利用雷射鑽孔（laserdrilHng)技術開設複數貫穿 =第-介電層26之貫孔，藉之露出晶片2〇上的鮮塾 μ 一。接者，形成第一線路層22於該第一介電層％，並使 :-線路層22與外露之銲墊2〇1電性連接。而後，於該第 =層22上敷設一第二介電層” ,並開設複數貫穿第 =电層27Λ貫孔270以藉之露出第一線路層22的預定 第：線二介電層27上形成第二線路層28，而使 線路層28與第—線路層22的外露部分電性連接。最 第二線路層28上敷設拒銲層23，使第二線路層28 ^疋部分餘銲層23之開孔2料露而與銲球Μ電性 。因此’用以包覆晶片20之封裝膠體25的表面25〇 19806 200826207 得提供較晶片20作ffl I & ΛΛ 表面2〇〇大之表面區域而能安置較多 鈈球24以有效達成與外界之電性連接。 門亡：封裴結構之缺點在於當使用雷射鑽孔技術 “又貝牙弟一介電層之貫孔以露出晶片上的銲墊時，晶片 上的銲墊為第一介電厣戶斤 ^ ^ 包曰所復，而使雷射通常難以準確地 碎:出#墊的位置，因而無法使所開設的貫孔精確地對應 至銲墊的位置；由於晶片上的銲塾無法完全露出，故難以 確保線路層與鲜墊間之電性拿。 . 电r生運接口口貝，而使製成品的良率 及信賴性受損。同時，於晶片及封裝膠體上敷設第一介電 層並利用，射鐵孔技術開設貫孔會增加成本及製程之複雜 性，且該第一介電層與晶片及封裝朦體具有不同的熱膨服 係數（CTE)，故於高溫環境或熱循環下，第一介電層與晶 片、及封農膠體會產生不同的熱應力而易使其間之界面發生 脫層，從而降低製成品的品質及信賴性。 復請參閱第3A至3D圖，為改善上述之缺點，美國專 利US7,002,245另揭示一種CSP結構及製法，如第圖 所不，首先製備一具複數晶片3〇之晶圓，各該晶片之 2用表面上設有複數銲墊301，且該銲墊301上形成有導 電凸塊31，並切割該晶圓以形成複數具導電凸塊之晶 片30 ;如第3B圖所示，將各該晶片3〇藉其導電凸塊？！ 黏置於一膠片（adhesion tape)36上，並形成包覆該晶片3〇 與導電凸塊31之封裝膠體35;如第3C圖所示，移θ除該膠 片，以使該導電凸塊3 1之端部外露出該封裝膠體35且與 該封裝膠體35之表面齊平，並於該封裝膠體35 ^ 面l· 7 19806 200826207 :成複數導電跡線32，且使該導電跡 導電凸塊以之外露端部，·如第犯圖所示連/妾= =該導電_上，且使該導電跡線3以 :出該拒銲層33而供接置銲球34，最刀 』:：形嫩具有單離之晶片的半導 衣- 然而，上述CSP結構之製法中，係採 (batch-type)將複數具導電凸塊之晶片呈陣列方式^置於 :片上’其中由於機具之誤差或其它原因，每一：片以 對接置位置盔法揞湓扯別‘ 甘日日片之相 '精確t制，亦即無法精確控制各唁B 鉻出封裝膠體之導電凸塊端 J谷忒日日片外 上複數晶片接置位S 同時，對應於一膠片 置，造成於另一膠片上複數晶片接置位 膠片而在输法精確定位’導致後續移除
電跡線的圖案化電凸塊端部之導 n τ 貝針對不同批次之複數黑H 保線路層與銲二=電裝結構及製法，俾能確 可靠度，並減少製程 【發明内容】 珉本，只為一重要課題。 有鑑於上述習知技術 -種於晶片級封袭41:::! 的係提供 接置於載具上之夂俾可於批次製程中’供 之各日日片相關位置皆相同。 "月又目的係提供一種晶片級封裝結構及其製 19806 8 200826207 相同俾Ύ於批_人製程中，於每一批次間之晶片相關位置皆 本發明再一目的 法，可同時針對不同批次之複種曰晶片級封裝結構及其製 本發明另一目的係提#_ ^片;"行圖案化線路作業。 法，可以低成本之方式=種:片級封裝結構及其製 為i隶卜、f Β甘 丁日日片、、及封裝結構之量產。 法，係包括：提供本發明之晶片級封裝結構之製 有複數之金屬墊’·將接置有^载具表面之預定位置形成 電凸塊對應銲接於哕 ^凸塊之複數晶片’以該導 定位於载具上於塾上’藉以將該晶片精準 電凸塊之封裝膠體；移㈣載且用"^覆該複數晶片與導 封裝膠體且與該封裳膠=載f金屬塾外露出該 線於該封褒膠體之^ 面齊平；形成複數導電跡 金屬墊該::::r線電性連接至該 該拒銲層之開孔，以外跡線上，亚開設複數貫穿 成複數導電預定部分;分別形 該封裝膠體，以形成:複;;上 风钹數具有日日片之晶片級封裝处 面形成有複數金屬塾之載具之製法係⑼：於 :;八：一阻層，該阻層中設有複數開孔以外露出該載 具心，俾於該開孔中電鑛沈積-金屬塾；移除該阻声， 以於該載純面財位置形成金屬墊。或者於载具上二 (sputtermg)沈積—金屬層，並利用圖案化方式 = 屬層部分，以於預定位置處形成金屬塾。 孟 19806 9 200826207 2過前述製法，本發明復揭示一種晶片級 係包括：晶片，具有一作用表面及一相對之非作;表1， 乍:J面上形成有複數導電凸塊，且各該導電凸塊 電凸：==塾;封麵，用以包覆該晶片及導 ^ 使電凸塊之端部金屬墊外露出該封穿膠雕 且與該封轉體之-表面齊平；第—導電跡線，形成= 封裝膠體之表面上並電性連接至該全屬墊.$ ρ 於嗲笛^ ^ <伐主忒I屬墊，拒銲層，敷設 j弟—導電跡線上並開設有複數開孔，以 =料部分π及導U件，係形成於該導電= 外露部分上。 』冰了只疋 ^外’本發明巾復可研磨該封裝膠體以外露出該晶片 θ間设可增§又至少一介電層及複數第二導電跡線， 以提昇封裝結構中導電跡線佈設的彈性。 、 因此，本發明之晶片級封裝結構及製法主要即先在載 具表面預定位置處形成位置精準之金屬墊，以使各該金屬 位置可精準得知，接著將複數個仙表面形成有 ^凸塊之晶片’透過其導電凸塊而對應銲接於該金 /蜀…’而得將各該晶片精準定位於該载具±，以利於進 :後續，製程’如此即可避免習知晶片級封裝結構之製法 於知批次方式（batch-type)將複數具導電凸塊之晶片呈 式黏置於膠片上’受限於機具之誤差或其它原因， ^ :片之相對接置位置無法精確控制，以及對應於一膠 上複數晶片接置位置不同於另一膠片上複數晶片接置位 19806 10 200826207 置，所造成彼此間之相對位置無法精確定位 除膠片而在封梦狀驊μ ; ¥致後、、、貝私 導+…：: 電性連接至該導電凸塊端部之 逐二光：化製程中’必須針對不同批次之複數晶片 上無法有效進行量產等問驟吳成本之提高及實務 ，趨rn?進行封裝作業’以於該載具上形成用以包覆 凸塊之封難，再移除該載具，以使 该至屬塾外路出該封裝膠體且與該封裝膠體之一表面齊 ΐ之二!Γ膠體之表面上形成複數電性連接至該金屬 墊之w跡線，以及於該導電跡線上敷設一 純數貫穿該拒銲層之開孔，料露出該導電跡線預定部 刀：以於该導電跡線預定外露部分上形成導電元件，最後 再封歸體’以形成複數晶片級封裝結構，達到 充分虿產目的。 【實施方式】 '以下係藉由特定的具體實施例說明本發明之實施方 式’熟悉此技藝之人士可由本說明書所揭示之内宏輕易地 瞭解本發明之其他優點與功效。 请翏閱第4A至41圖’係為本發明之晶片級封裝結構 及其製法之示意圖。 如第4A圖所示，提供一例如為鋼板之金屬材質載具 46，亚於該載具46上敷設一阻層47，且利用如黃光 (Photo-lithography)製程等曝光、顯影之圖案化方式，以於 該阻層47敎位置形成有外露出該載具46部分表面之開 19806 11 200826207 孑L 470。 以於外露出該阻層開 墊48，該金屬墊48之 如第4B圖所示，利用電鍍方式 孔47〇之该載具46表面沈積一金屬 材質係如為金（Au)或把（Pd)等。 如弟4C圖所示，移除該阻 面預定位置形成有複數之金屬墊48。（ 载具46表 !:第4D圖所示，將複數接置有導電凸塊41之晶片 =迴八銲::fl°w)以將該導電凸塊41而對應銲接於該載 ^ ^屬墊48上，藉以精準將該些晶片4〇定位 具^上。如此即可避免習知晶片級封裝結構之製法中^ ^ 切複數具導電凸塊之Μ呈㈣方絲置於勝 i:置具之誤差或其它原因，每-晶片之相對接 法精確控制，導致後續在封裝勝體上形成導電跡 線的圖*化製程中’必須針對不同批次之複數晶片逐_眠 問:造成製程步驟與成本之增加及實務上無法： 該晶片40具有一作用表面4〇〇及一相對之非 並於I晶片AG t作用表面400上形成有複數銲墊 4〇1。接著，進行一銲塊或拴塊形成（bumping orstud bUmPin㈣I以於晶片4〇之各銲墊401 i形成一導電凸 塊：1: δ亥導電凸塊41可為銲錫凸塊(solder bumP)、高錯 3里鲜錫凸塊作邮iead s〇ider bump)、金質鋅塊（g〇ld bUmP)、或金質栓塊（gold stud bump)等。 第4E圖所示，於該载具私上形成用以包覆該複數 12 19806 200826207 晶片40與導電凸塊41之封裝膠體45。 如第4F圖所示，利用如钱刻之方式移除該金屬材質 载具46(如銅板），以使該金屬墊48外露出該封裝膠體c 且與該封裝膠體45之一表面齊平。 如第4G圖所*，利用圖案化線路製程，以形成複數 導電跡線42於該封裝膠體45之表面上，並使該導電 42電性連接至該金屬墊。 、'1 如第4H圖所示，敷設一拒輝層43於該導電跡線仏 =開設複數貫穿該拒銲層43之開孔，以外露出該 ::之預定部分，而該導電跡線42之外露部分可為玖 立而部位（terminal)。 马、、 接著分別形成複數導電元件44 露部分上。哕導雷^ 々、忑V電跡線42之外 體封⑽：件44可例如為圖示之鋅球，作為半導 遐封I結構之輸入/輸出端 勺干¥ 1叫包塔扳寻）成電性連接關係。 第41圖所不，進行一切』 45，以形成複數晶片級封裝^膠體 衣、、口耩，以達i產目的。 構，传包括、，方法’本發明亦揭示一種尺寸級封裝处 再係包括·晶片40，且古一於士 衣、、、口 作用表面402,並㈣作用本 表面_及—相對之非 塊4卜且各該導電、凸Γ/面 400上形成有複數導電凸 裴膠體45,用以勺变‘ 1之端部形成有一金屬墊48;封 電凸… 覆該晶片4〇及導電凸㈣，並使4 凸塊4〗之端部金屬墊 卫使，亥導 裝膠體45之—8外路出該封裝膠體Μ且與該封 乂与平，導電跡線42，形成於該封裝膠 13 】9806 200826207 體45之表面上並電性連接至該金屬墊48;拒銲層u，敷 -°又於③導電跡線42上並開設有複數開孔，以使外露出該導 .電跡線42預定部分；以及導電元件44，係形成於該導電 跡線42之外露部分上，以供晶片4〇藉之與外界震置電性 連接。 八屬ΓΤ第5“5D圖’另外於本發明中形成有預定 載具之製法復可包括：提供一如玻璃之載具46, :^載具46上以難（sputtering)方式沈積一如金（Au)或 >纪㈣之金屬層(如第5A圖所 :除部分該金屬層’例如於該金屬層彻上敷設一 ^ 屬μ邱八女 有開孔470,以外露出欲移除之金 屬層口Ρ刀，亦即保留欲形成有 第 ,屬墊之位置上方的阻層（如 弟5Β圖所不）；钱刻移除未為該 480部分（如第5Γ同％一、 岍後皿之至屬層 弟C圖所不）；以及移除該剩餘之阻層47,， 以於載具46預定位置虐报士人ρ 刺饰您丨且層47 .— 置处形成金屬墊48(如第5D圖所示）。 设#茶閱第6圖，俜顯+士 ' 一电,H ^ 頌不本發明之晶片級封裝結構第 —貝靶例之剖面示意圖。 舟示 前述實施例所揭露者大二“晶片級封裝結構與 •封裝膠體45遮覆住曰曰片4〇 ，、不同處在於可研磨去除 使晶片4〇之非之”用表面402的部分，以 , 4〇2外露，俾有助於昔片 運作所產生之熱量至外衣 ，力於政逸曰曰片40 效率。 界或大氣中，增進封裴結構之散熱 請參閱第7圖，係_ - 實施例之剖面示咅圖。、^不本％明之晶片級封裝結構第三 丁-圖。如圖所示，該晶片級封裝結構與前 19806 14 200826207 &實=7揭露者大致相同，其不同處在於形成導電跡線 mr線”)於封㈣體45上後，錄設至少 .心二曰$於該乐—導電跡線42上’並開設複數貫穿介 貝孔（via)，以使第-導電跡線42之預定部分藉 '^22二接者’於該介電層49上形成複數第二導電跡 1外二第二導電跡線422舆至少-第-導電跡線 42之外路。卩分電性連接。 ，設複數=弟二導電跡線422上敷設拒鲜層43’並開 之預定：：Ε鋅層Γ之開孔’以外露出第二導電跡線422 邻位二：’而该第二導電跡線422之外露部分可為終端 i成二進行於各第二導電跡線422之外露部分（終端） =一：之導電元件44，以作為封裝結構之輸入/ 二:增層置，生連接。如此· 性，俾使曰ΐί 4而月b提升封襄結構中導電跡線佈設的彈 作。 更能有效地電性連接至外界裝置以進行運 且表本發明之晶片級封裝結構及製法主要即先在载 Γ 處形成位置精準之金屬墊，以使各該金屬 土之目對位置可精準得知，接著將複數 複數導電凸媸夕曰Η 、系、風*… W用表面形成有 屬執μ 曰曰片’透過其導電凸塊而對應鮮接於該金 上，進而將各該晶片精準定位於該 行後續之掣铲,L, 0 ^ /、上以利於進 中，於採太免習知晶片級封褒結構之製法 ==次方式師h_type)將複數具導電凸塊之 陣財式黏置於膠片上，受限於機具之誤 19806 15 200826207 每:片之相對接置位置無法精確控制，以及對應於一膠 片上複數晶片接置位置不同於另—膠片上複數晶片接置位 置调所'成纟此間之相對位置無法精確定位，導致後續移 片而在封裝膠體上形成電性連接至該導電凸塊端部之 2跡線的圖案化製程中，必須針對不同批次之複數晶片 \曝光、顯影情況，造成製程步驟與成本之提高及實務 上热法有效進行量產等問題。 =即可進行封裝作業，以於該載具上形成用以包覆 該：屬電凸塊之封裝谬體，再移除該載具，以使 :之=該封細之表面上形成複數電性連接L:屬 拒:::r跡… 分，以於該“二跡線預定部 充:量：裝膠體，以形成複數晶片級封裝結構，㈣ 一处員施例僅為例示性說明本發明之原理 與變：:因::明及範疇下，對上述實施例進行修飾 專利範圍二。本_利保護範圍，應如後述之申請
【圖式簡單說明J 二】：係為習知之尺寸級封裝結 弟2圖係為美國專利⑽W露之尺寸級封 J6 】9δ06 200826207 裝結構示意圖； 第3A至3D圖係為美國專利uS7,002,245所揭示之尺 寸級封裝結構及製法剖面示意圖； 第4 A至41圖係為本發明之晶片級封裝結構及其製法 示意圖； 制第5A至5D圖於為本發明中表面設有金屬墊之載具之 衣法示意圖； 圖 ;=圖係為本發明之晶片級封裝結構第二實施例示意 圖 第7圖係為本發明之曰Η έ 之曰曰片級封裝結構第三實施例示意 10 1〇0 1〇1 11 Π〇 12 13 13〇 14 20 2〇〇 2〇ι 主要元件符號說明 曰 y 曰曰月 作用表面 銲墊 介電層 貫孑L 線路層 拒鋒層 開孔 銲球 晶片 作用表面 鮮塾 19806 17 200826207 202 非作用表面 203 側面 22 第一線路層 23 拒銲層 230 開孔 24 鲜球 25 封裝膠體 250 封裝膠體的表面 26 第一介電層 27 第二介電層 260,270 貫孔 28 第二線路層 30 晶片 301 焊塾 31 導電凸塊 32 導電跡線 33 拒鮮層 34 鲜球 35 封裝膠體 36 膠片 40 晶片 400 作用表面 401 銲墊 402 非作用表面 18 19806 200826207 41 導電凸塊 . 42 導電跡線 422 第二導電跡線 43 拒銲層 44 導電元件 45 封裝膠體 46 載具 ， 47,475 阻層 . 470,470’ 開孔 48 金屬塾 480 金屬層 49 介電層 19 19806

Claims (1)

  1. 200826207 十、申請專利範圍： 係包括： 面之預定位置形成有複 1 · 一種晶片級封裝結構之製法， 提供一載具，於該载具表 數之金屬墊； 將複數接置有導電凸塊之晶片，以 應銲接於該載且之全屬執μ 〇 屯凸鬼對 於載具上； 藉以將該晶片精準定位 裝膠Γ线具上形成包⑽複數晶片與導電凸塊之封 體且 移除該載具，以使該金屬墊外露出該封裝膠 與該封裝膠體之一表面齊平； / 形成複數導電跡線於該封裝膠體之表面上，並使 該導電跡線電性連接至該金屬墊； 士敷設-拒銲層於該導電跡線上，並開設複數貫穿 该拒銲層之開孔’以外露出該導電跡線預定部分； 分別形成複數導電元件於該導電跡線預定外露 分上；以及 ° 切軎彳6亥封裝膠體，以形成複數晶片級封裝結構。 如申請專利範圍第1項之晶片級封裝結構之製法，其 中’於該載具表面之預定位置形成有複數金屬墊之製 法係包括： 於載具上形成一阻層，該阻層中設有複數開孔以 外露出該載具部分； 於該開孔中形成一金屬墊； 20 19806 200826207 墊 知除名阻層，以於該載具表面預定位置形成金屬 3. 專利範圍第2項之晶片級封衆結構之製法，其 成。/載具為金屬材質’且該金屬塾係以電鐘方式形 4. ^專利範圍第i項之晶片級封裳結構之製法，复 法係包=具表面之預定位置形成有複數金屬塾之製 於载具上沈積一金屬層； 孔以：=屬層上敷設一阻層，並使該阻層形成有開 卜路出欲移除之金屬層部分， 屬墊之位置上方的阻層； 乂保^人形成有金 料未為該阻層所覆蓋之金屬層部分；以及 屬墊移除該剩餘之阻層’以於載具預定位置處形成金 I 範圍第4項之晶片級封裂結構之製法，其 之其i者為玻璃材質，該金屬層為金（AU)及麵⑽ 中申:ίΓ乾圍第1項之晶片級封裳結構之製法，其 7 孟墊之材質為金（Au)及銳（Pd)之1中一者。 .中範圍第1項之晶片級封農結狀製法，其 分，研磨方式去除封鋒體遮覆住晶片之部 刀，以外露出該晶片。 8.如申請專利範圍第！項之晶片級封I结構之製法，其 19806 21 200826207 中，於該導電跡線與拒銲層間復設有至少一介電層及 複數第二導電跡線。 9·如申請專利範圍第8項之晶片級封裝結構之製法，其 中，於該導電跡線上敷設至少一介電層，並使該導電 跡線之預定部分外露出該介電層，接著，於該介電層 上形成複數第二導電跡線，並使第二導電跡線與至少 。亥&電跡線之外露部分電性連接，然後，於第二導 ^跡線上敷設拒銲層，並外露出第二導㈣線之預定 刀接著杰第一導電跡線之外露部分上形成導電 元件。 1〇. 一種晶片級封裝結構，係包括： 、，曰曰片，具有一作用表面及一相對之非作用表面， 亚於該作用表面上形成有複數導電凸塊，且各該導電 凸塊之端部形成有一金屬墊； 胃封裝膠體，用以包覆該晶片及導電凸塊，並使該 導電凸塊端部之金屬墊外露出該封裝膠體且與該封裝 膠體之一表面齊平； V電跡線，係形成於該封裝膠體之表面上並電性 連接至該金屬墊； 拒銲層，係敷設於該導電跡線上並開設有複數開 孔’以使外露出該導電跡線預定部分；以及 導電元件，係形成於該導電跡線之外露部分上。 11 ·如申请專利範圍第10項之晶片級封裝結構，其中，該 金屬墊之材質為金（Au)及鈀（pd)之其中一者。/、 22 19806 200826207 •明專利範圍第1〇項之晶片級封裝結構，其_，該 之非作用表面為封裝膠體所遮覆及外露出該封裝 膠體之其尹—者。 13.=請專利範圍第1()項之晶片級封裝結構，其中，於 一'導包跡線與拒銲層間復設有至少一介電層及複數第 二導電跡線。 14.=請專利範圍第13項之晶片級封裝結構，其中，該
    跡線上敷設有至少一 ^ ^ ^ ^ 〜 7丨电續並使该導電跡線之 外露出該介電層，且該介電層上形成有複數 弟一¥電跡線，並使該第二導電跡線與至少一 跡線之外露部分電性連接， 〆、 执右认十， K W玄弟一導電跡線上敷 ^外=出第二導電跡線預定部分之拒銲層，以及於 石亥弟―導電跡線之外露部分上形成有導電元件。 19806 23
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