200824052 九、發明說明： 【發明所屬之技術領域】 本發明是屬於電子裝置結構中與晶片結合的載板設計。 【先前技術】 如圖8所示，為美國專利編號第712 9 5 7 2號所揭示的 電子裝置剖視圖，其製造的程序如下··首先，提供一電路板9 〇， 電路板9 0具有上表面91及相對應的下表面9 2、多個導電端 9 5及多個導電通路9 6以供電性連接用；將一晶片5 〇設置在 電路板9 0上表面91，晶片5 0具有上表面51及相對應的下 表面5 2，其中，上表面51具有多個導電端5 5以供電性連接 用；再將-習式载板1設置在晶片5〇上表面51，載板工具有 絕緣體6及多個導電件7，絕緣體β及導電件7各具有側邊6 c、7 c、上表面6 a、7 a及相對應的下表面6b、7b，而 •導電件7受絕緣體6包封’其中，導電件7上表面7 a未受絕緣 體6包封賴電性連制；織提好條導魏4 Q，導電線々 0各具有二端點’並分顺晶片5 Q導電端5 5、載板i導電件 7及电路板9 0‘電端9 5接合，使晶片5⑽電性得以藉導電 線4 0傳輸至電路板9 〇 ;最後提供一封裝體（未綠示），將晶 片5 0、載板1及導電線4 〇包封。 再如圖9所示，是载板1在檢晶機内作業過程的示意圖，复 顯示多個載板1排列在姉帶8上，其中，中央的载板工置敎 200824052 作平台W上，一頂針E自底部向上移動，其穿過工作平台w表面， 並戳破黏膠帶8使載板1自黏膠帶8脫離，一機械手臂R移動到 载板1上表面la吸取自黏膠帶8脫離的載板i，在載板1脫離 黏膠帶8的過程中，絕緣體6與導電件7的接合處c會受移動速 度快的頂針E衝擊而產生裂縫，使導電件7自絕緣體6剝離而喪 失功此’尤其當絕緣體6的厚度τ是在小於零點一公厘時更容易 發生。200824052 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a carrier board design that is combined with a wafer in an electronic device structure. [Prior Art] As shown in Fig. 8, a sectional view of an electronic device disclosed in U.S. Patent No. 712 9 5 2 2 is manufactured as follows. First, a circuit board 9 〇 is provided, and the circuit board 90 has The surface 91 and the corresponding lower surface 9.2, the plurality of conductive ends 915 and the plurality of conductive paths 796 are electrically connected; a wafer 5 is disposed on the upper surface 91 of the circuit board 90, and the wafer 50 has a surface 51 and a corresponding lower surface 52, wherein the upper surface 51 has a plurality of conductive ends 55 for power supply connection; and the conventional carrier 1 is disposed on the upper surface 51 of the wafer 5, and the carrier tool has The insulator 6 and the plurality of conductive members 7, the insulator β and the conductive member 7 each have side edges 6 c, 7 c, upper surfaces 6 a, 7 a and corresponding lower surfaces 6b, 7b, and the conductive member 7 is insulated by the insulator 6 Encapsulation 'where the upper surface 7 a of the conductive member 7 is not covered by the insulator 6; the strip is guided by the lead 4 4, and the conductive lines 々 0 each have two end points 'and are divided into the wafer 5 Q conductive The terminal 5 5, the carrier i conductive member 7 and the circuit board 90 0' electrical terminal 9 5 are bonded, so that the wafer 5 (10) can be electrically transferred to the circuit board 9 through the conductive line 40. Finally, a package (not shown in green) is provided to encapsulate the wafer 50, the carrier 1 and the conductive line 4 . As shown in FIG. 9 , it is a schematic diagram of the operation process of the carrier 1 in the crystallizer. The plurality of carriers 1 are arranged on the sling 8 , wherein the central carrier is placed on the platform W, 200824052. The thimble E moves upward from the bottom, passes through the surface of the working platform w, and punctured the adhesive tape 8 to disengage the carrier 1 from the adhesive tape 8. A mechanical arm R moves to the upper surface of the carrier 1 and the self-adhesive tape 8 is detached. In the process of the carrier board i, when the carrier board 1 is detached from the adhesive tape 8, the joint c of the insulator 6 and the conductive member 7 is impacted by the ejector pin E having a fast moving speed to cause cracks, and the conductive member 7 is peeled off from the insulator 6 and loses work. This is more likely to occur especially when the thickness τ of the insulator 6 is less than zero mm.
【發明内容】 鐘於圖9習式載板會因外力衝擊而喪失功能，為提升載板的 品質，於載板絕緣體下表面設置一缓衝層用以提升载板承受外力 衝擊的能力。 【實施方式】 兹舉下列各剖視圖並說明本發明的特徵及功能·· 如圖1所示，一個具有本發明基本特徵的載板1〇剖視圖， 其包括：一絕緣體2 0，實施為樹脂（Re s i η)或膠片（？ r e p r eq)等適當的非導電材質，具有側邊2 3、上表面2 1 及相對應的下表面2 2 ;—導電件6 0，實施為銅或鋁等材料， 具有侧邊6 3、上表面61及相對應的下表面62，導電件6〇 文絕緣體2 0包封，其中，上表面61未受絕緣體2 0包封以供 電性連接用；一緩衝層3 0，可實施為膠片、陶瓷等適當的非導 200824052 電材質，亦可實施為銅或合金金屬等適當的導電材質，具有侧邊 3 3、上表面31及相對應的下表面3 2，其中，上表面31設 置在絕緣體2 0下表面2 2 ;本例中，因緩衝層3 0設置在絕緣 體2 0下表面2 2，使絕緣體2 0及導電件6 0不直接遭受檢晶 機頂針衝擊，使載板1〇不易產生裂縫而能提升載板1〇的品質。SUMMARY OF THE INVENTION The conventional carrier plate of Fig. 9 loses its function due to external impact. To improve the quality of the carrier, a buffer layer is disposed on the lower surface of the carrier insulator to enhance the ability of the carrier to withstand external impact. [Embodiment] The following cross-sectional views are taken to illustrate the features and functions of the present invention. As shown in Fig. 1, a cross-sectional view of a carrier board 1 having the essential features of the present invention includes an insulator 20 implemented as a resin ( A suitable non-conductive material such as Re si η) or film (? repr eq) has a side edge 2 3 , an upper surface 2 1 and a corresponding lower surface 2 2 ; the conductive member 60 is implemented as a material such as copper or aluminum , having a side edge 63, an upper surface 61 and a corresponding lower surface 62, the conductive member 6 is encapsulated by the insulator 20, wherein the upper surface 61 is not encapsulated by the insulator 20 for power supply connection; a buffer layer 30 can be implemented as a suitable non-conductive 200824052 electrical material such as film or ceramic, or as a suitable conductive material such as copper or alloy metal, having a side edge 3 3, an upper surface 31 and a corresponding lower surface 3 2, The upper surface 31 is disposed on the lower surface 2 2 of the insulator 20; in this example, since the buffer layer 30 is disposed on the lower surface 2 2 of the insulator 20, the insulator 20 and the conductive member 60 are not directly subjected to the ejector pin. Impact, so that the carrier plate 1 is less prone to cracks and can lift the carrier plate 1 quality.
如圖2所示，一載板10的剖視圖，其包括：一絕緣體 具有貫穿孔洞2 4、侧邊2 3、上表面2 1及相對應的下表面2 2 ,二導電件6 〇，各具有上表面61及相對應的下表面6 2、 凸部6 4、延伸部6 6及侧邊6 3，各導電件6 〇受絕緣體2 〇 包封，其中，上表面61、凸部6 4、延伸部6 6及侧邊6 3的 一部分未受絕緣體2 0包封以供電性連接用，且延伸部6 6是設 置在絕緣體2 0上表面2 1 ; —緩衝層3 〇，具有貫穿孔洞3 4、 侧邊3 3、上表面31及相對應的下表面3 2，其中，上表面3 1是設置在絕緣體2 0下表面2 2，且緩衝層3 q貫穿空洞3 與絕賴2 0貫穿孔洞2 4可連成-貫穿的孔洞；本例某= 晶片（未繪示）會依需求將導電端設置在晶片上表面的任何適; 位置，而载板1G的貫穿孔洞可依晶片導電端的位置而設置^龟 載板10設置在晶片上後，晶片的導電端即可裸露於載板^ 2 貫穿孔洞内以滿足產業的需求’同時，因延伸部66可在絕緣體 2 0上表面21自由的延伸，令導電件6 〇的電性傳輪可=達= 緣體2 0上表面2 1的任何位置，令载板1 〇更具實用性。 200824052 如圖3所示，-組合式載板！〇的剖視圖，其包含：_緩衝 層3 0，其特徵與圖工所示的緩衝層3 〇相同；二絕緣體2… 分別設置在緩衝層3⑽上表面3工及下表面3 2，各具有侧邊 2 3、上表面2 1及相對朗下表面22 ;二導電件㈢，各具 有侧邊6 3、上表面6i及相對應的下表面62，二導電件、 分別設置在緩衝層30的上表面3i及下表面32，各導半 0受絕緣體2 0包封，其中，上表面6工未受絕緣體2 ^封以 絲性連_，而位於緩衝層3 G上表面3 i側鱗電件㈢上 表面61的水平面是低於絕緣體2 〇上表面2工，同時，下表面 6 2未受絕緣體2 〇包封而與緩衝層3 〇上表面3丄接合；一導 電通路9 6，貝牙緩衝層3 〇並分別與二導電件6 〇接合，使二 導電件6 0得以電性連通；本例中，_衝層3 〇上、下表面3 1、3 2均具有導電件6 〇，且藉導電通路g 6電性連通，令載 板1〇成為-個具有兩層導電件的載板，且因緩衝層3 〇上表面 31與導電件6 〇下表面6 2間的絕緣體2㈣皮去除，令载板 1〇的厚度得以降低’同時，因導電件6 q上表面6丄的水平面 比絕緣體2 0上表面2 1低而具有一凹洞，在凹洞内的導電件6 0上表面61可⑨置至少—層導電層6 7，使導電件6 〇更利於 與其他物質賴合健，且導騎6 7是可設置在關内，令載 板1 0的厚度不會增加，以上所述各特點均使载板丄⑽設計更 具彈性及使用性。 200824052 如圖4所示，一組合式載板1〇的剖視圖，此載板1〇是以 圖1的特徵為基礎’在緩衝層3 0下表面3 2再設置一缓衝層3 〇，使載板10具有二層緩衝層3 0，令載板1Q能夠承受更大 的外力衝擊。 ' 如圖5所示，一組合式載板10的剖視圖，此載板丄〇是以 . 圖1的特徵為基礎，在絕緣體2 0上表面21再設置一上層的絕 緣體2 0及導電件6 〇，使二絕緣體6 〇呈堆疊狀，並以一導電 • 通路9 6連接二導電件6 0，使二導電件6 〇得以電性連通’令 載板10成為具二層導電件6 0而更具實用性。 如圖6所示，一載板1〇設置在電子裝置内的剖視圖，其包 含：一電路板9 〇及一晶片5 0，此電路板g 〇及晶片5 〇的特 徵與圖8所示的電路板9 〇及晶片50相同，其中，晶片50設 置在電路板9 0上；一間隔件S，設置在晶片5 〇上；一載板1 0 ’設置在間隔件s上，使載板1〇、間隔件s及晶片5 0呈堆 • 疊設置；本例中，藉一間隔件S將載板1〇墊高使载板1〇設置 在晶片5 0上，令導電線4 0可容置在載板10與晶片之間，使 載板10更具實用性。 如圖7所示，一載板1〇設置在電子裝置内的剖視圖，其包 含：一電路板9 0及一晶片5 0，此電路板9 〇及晶片5 0的特 徵與圖8所示的電路板9 〇及蟲片5 0相同；一載板10，設置 在電路板9 0上，而晶片5 0設置在載板1〇上，使載板10與 -10- 200824052 晶片5 0呈堆疊設置；本例中， 電路板90上，更利於產業應用 晶片5 0可藉載板1〇而設置在 上4各關林發明的較佳實補，t不能以 實施範園，例：^罔1 p ^ 圖1〜5所示，導電件β 〇上表面6 i可設置 g或夕層的^電層以利於金屬、線的接合作業，此導電層可實施 為鎳金銳或銀等其他適當的導電材料；再如圖工〜$所示， 1d e r ma s k)的材質’用以保護載板10不因外力衝擊 一貝壞並可提升載板工0表面與其他物質的接合能力；如圖6 所不’電子裝置中電路板的功能亦可用導線架（L e a d h 在絕緣體2 0上表面2 1峻制下表面可設置如轉層（s〇 a m e )取代；故舉凡數值變更鱗效元件置換，或依本發明申 請的權利要求範騎作_等變化與修飾，皆應仍屬本發明專利 涵蓋的範轉。 【圖式簡單說明】 圖1:载板具有緩衝層的剖視圖； 圖2·載板具有貫穿孔洞的剖視圖； 圖3 ·載板的緩衝層上、下表面均具絕緣體的剖視圖； 圖4:載板具有二堆疊設置的緩衝層剖視圖； 圖5·載板具有二堆疊設置的絕緣體剖視圖； 圖6 ··應用本發明載板的電子裝置，其中，載板下方具間隔件的 剖視圖； -11- 200824052 圖7 :翻本發__電子裝置，其巾，晶肢置 的剖視圖； 圖8·餐式载板設置在電子|肋的的剖視圖； 圖9:習式载板在檢晶機工作平台上的示意圖。As shown in FIG. 2, a cross-sectional view of a carrier 10 includes an insulator having a through hole 24, a side edge 23, an upper surface 2 1 and a corresponding lower surface 2 2 , and two conductive members 6 〇 each having The upper surface 61 and the corresponding lower surface 6.2, the convex portion 64, the extension portion 6 6 and the side edge 63, each of the conductive members 6 〇 are covered by the insulator 2 ,, wherein the upper surface 61, the convex portion 64, A portion of the extension portion 6 6 and the side edge 63 is not encapsulated by the insulator 20 for power supply connection, and the extension portion 6 6 is disposed on the upper surface 2 1 of the insulator 20; the buffer layer 3 〇 has the through hole 3 4, the side 3 3, the upper surface 31 and the corresponding lower surface 3 2, wherein the upper surface 31 is disposed on the lower surface 22 of the insulator 20, and the buffer layer 3 q runs through the cavity 3 and The hole 24 can be connected into a through hole; in this case, a wafer (not shown) can be placed at any suitable position on the upper surface of the wafer as required, and the through hole of the carrier 1G can be based on the conductive end of the wafer. After the location of the turtle carrier 10 is placed on the wafer, the conductive end of the wafer can be exposed to the carrier 2 through the hole to meet the needs of the industry. 'At the same time, because the extension portion 66 can freely extend on the upper surface 21 of the insulator 20, the electrical transmission wheel of the conductive member 6 可 can be up to = any position of the upper surface 2 1 of the edge body 20, so that the carrier board 1 〇 More practical. 200824052 As shown in Figure 3, - combined carrier! A cross-sectional view of the crucible, comprising: a buffer layer 30 having the same characteristics as the buffer layer 3 所示 shown in the drawing; two insulators 2... respectively disposed on the upper surface 3 and the lower surface 32 of the buffer layer 3 (10), each having a side The edge 2 3, the upper surface 2 1 and the relatively lower surface 22; the two conductive members (3) each having a side edge 63, an upper surface 6i and a corresponding lower surface 62, and two conductive members are respectively disposed on the buffer layer 30 The surface 3i and the lower surface 32, each of the guiding halves 0 are encapsulated by the insulator 20, wherein the upper surface 6 is not sealed by the insulator 2, and is located on the upper surface of the buffer layer 3G. (3) The horizontal surface of the upper surface 61 is lower than the upper surface of the insulator 2, and the lower surface 62 is not covered by the insulator 2 而 and is bonded to the upper surface 3 of the buffer layer 3; a conductive path 9 6, The buffer layer 3 is respectively connected to the two conductive members 6 , to electrically connect the two conductive members 60; in this example, the upper and lower surfaces 3 1 and 3 2 of the 冲 layer 3 have conductive members 6 〇, And the conductive path g 6 is electrically connected, so that the carrier board 1 becomes a carrier board having two layers of conductive members, and the upper surface 31 of the buffer layer 3 The insulator 2 (four) between the lower surface 62 of the conductive member 6 is removed, so that the thickness of the carrier 1 得以 is reduced. Meanwhile, since the horizontal surface of the upper surface 6 导电 of the conductive member 6 q is lower than the upper surface 21 of the insulator 20, a recess, the upper surface 61 of the conductive member 60 in the recess can be placed at least - the conductive layer 67, so that the conductive member 6 is more conducive to the health of other materials, and the guide 6 7 can be set in the closed Therefore, the thickness of the carrier 10 does not increase, and all of the above features make the carrier raft (10) more flexible and usable. 200824052 As shown in FIG. 4, a cross-sectional view of a combined carrier board 1B is based on the features of FIG. 1 and a buffer layer 3 再 is further disposed on the lower surface 3 2 of the buffer layer 30. The carrier 10 has two buffer layers 30 to enable the carrier 1Q to withstand greater external impact. As shown in FIG. 5, a cross-sectional view of a combined carrier 10 is based on the features of FIG. 1, and an upper insulator 20 and a conductive member 6 are disposed on the upper surface 21 of the insulator 20. 〇, the two insulators 6 〇 are stacked, and the two conductive members 60 are connected by a conductive path 96 to electrically connect the two conductive members 6 to make the carrier 10 become a two-layer conductive member 60. More practical. As shown in FIG. 6 , a cross-sectional view of a carrier 1 〇 disposed in an electronic device includes: a circuit board 9 〇 and a wafer 50 , the characteristics of the circuit board 〇 and the wafer 5 与 and the The circuit board 9 is the same as the wafer 50, wherein the wafer 50 is disposed on the circuit board 90; a spacer S is disposed on the wafer 5; a carrier 10' is disposed on the spacer s to enable the carrier 1 The 〇, the spacer s and the wafer 50 are stacked and stacked; in this example, the carrier 1 is padded by a spacer S so that the carrier 1 is placed on the wafer 50, so that the conductive line 40 can be accommodated. The carrier 10 is placed between the carrier 10 and the wafer to make the carrier 10 more practical. As shown in FIG. 7, a cross-sectional view of a carrier 1 is disposed in an electronic device, and includes: a circuit board 90 and a wafer 50. The characteristics of the circuit board 9 and the wafer 50 are as shown in FIG. The circuit board 9 is the same as the insect piece 50; a carrier board 10 is disposed on the circuit board 90, and the wafer 50 is disposed on the carrier board 1 to stack the carrier board 10 with the-10-200824052 wafer 50. In this example, on the circuit board 90, it is more advantageous for the industrial application chip 50 to be placed on the board 1 〇 and set in the upper 4 each of the Guanlin inventions, and t can not be implemented in the garden, for example: ^罔1 p ^ As shown in Figures 1 to 5, the upper surface 6 i of the conductive member β 可 may be provided with an electrical layer of g or a layer to facilitate the bonding operation of the metal or the wire. The conductive layer may be implemented as nickel gold sharp or silver or the like. Appropriate conductive material; as shown in Figure ~$, the material of '1d er ma sk) is used to protect the carrier 10 from impacting a ball due to external force and improving the bonding ability of the surface of the carrier 0 to other materials; As shown in Figure 6, the function of the circuit board in the electronic device can also be used as a lead frame (L eadh can be set on the upper surface of the insulator 2 0. 〇 〇 ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) Figure 1 is a cross-sectional view of the carrier having a buffer layer; Figure 2 is a cross-sectional view of the carrier having a through hole; Figure 3 is a cross-sectional view of the upper and lower surfaces of the buffer layer of the carrier with an insulator; Figure 4: The carrier has two stacked arrangements FIG. 5 is a cross-sectional view of the insulator having two stacked layers; FIG. 6 is a cross-sectional view of the electronic device using the carrier of the present invention, with a spacer under the carrier; -11- 200824052 __Electronic device, its towel, a cross-sectional view of the crystallographic device; Figure 8 is a cross-sectional view of the meal carrier plate placed on the electron | rib; Figure 9: Schematic diagram of the conventional carrier plate on the working platform of the crystallizer.
【主要元件符號說明】 1··*···*··載板 7 ········導電件 1〇··......載板 21、31 · · · ·上表面 2 3、3 3 · · · · ·侧邊 30·······緩衝層 5 0........晶片 5 2、6 2、9 2 ·下表面 6 0......•導電件 6 4...... ••凸部 6 7 ·······導電層 9 6 ······導電通路 6 b、7 b · · · ·下表面 C....... ••間隙 R · .....機械手臂 T .......•厚度 6 * · · * * •··絕緣體 8..... • · ·黏膠帶 2 0···· •··絕緣體 2 2、3 2 · •··下表面 24-34· ••貫穿孔洞 40···· •··導電線 5 1、6 1、 91·上表面 5 5、95· •••導電端 6 3···· • · · ·側邊 6 6···· •··延伸部 90···· •··電路板 6a、7a· • •上表面 6 c、7 c · • · · ·侧邊 E * * · * · • · · ·頂針 S · · · · · •··間隔件 W · · · · · ••工作平台 -12-[Description of main component symbols] 1··*···*··carrier board 7········Conductive parts 1〇···carrier board 21, 31 · · · · Upper surface 2 3, 3 3 · · · · · Side 30······· Buffer layer 5 0........ Wafer 5 2, 6 2, 9 2 · Lower surface 6 0.... ..•Conductive member 6 4... ••Protruding part 6 7 ·······Conductive layer 9 6 ······ Conductive path 6 b, 7 b · · · · Lower surface C ....... ••Gap R · ..... Robot arm T.......•Thickness 6 * · · * * •··Insulator 8..... • · · Adhesive tape 2 0····•··Insulator 2 2,3 2 ·•··Lower surface 24-34·••through hole 40·······Conductive wire 5 1、6 1、91·Upper surface 5 5, 95· ••• Conductive end 6 3···· • · · · Side 6 6·······Extension 90·······Board 6a, 7a· • • Upper surface 6 c, 7 c · • · · · Side E * * · * · • · · · Thimble S · · · · · ··· spacer W · · · · · •• Work platform-12-