JP2017228559A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of being miniaturized and improving a packaging property, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device comprises: a semiconductor element 11; a terminal 2 arranged so as to be separated from the semiconductor element 11, and having a terminal side face 23 facing a direction orthogonal to a thickness direction Z of the semiconductor element 11; and an encapsulation resin 4 that covers the semiconductor element 11, and that has a resin side face 43 facing a direction orthogonal to the thickness direction Z of the semiconductor element 11. The terminal side face 23 is exposed from the encapsulation resin 4. A terminal conductive layer 28 that covers the terminal side face 23 is formed on the terminal 2.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device in which a semiconductor element is a Hall element and is in a surface mount type resin package format and a method for manufacturing the same.

  A semiconductor device in which a semiconductor element is a Hall element is applied to various electronic devices such as a mobile phone. For example, when the light source of a display of a mobile phone is controlled, if the semiconductor device is applied, the light source can be turned on or off by opening and closing the main body of the mobile phone. The semiconductor device is required to be further miniaturized.

  Patent Document 1 discloses a semiconductor device in which a semiconductor element that is downsized is a Hall element. The semiconductor device includes a semiconductor element, a plurality of electrodes standing in the thickness direction from the semiconductor element, a solder ball disposed at the tip of each electrode, and a sealing resin that covers the semiconductor element and the electrode It has become. In the semiconductor device, a semiconductor element is not mounted on a lead frame or the like, a conductive path of the semiconductor element is formed only by electrodes and solder balls, and the substrate of the semiconductor element is exposed to the outside. For this reason, the semiconductor device has been reduced in size.

  However, since the semiconductor device disclosed in Patent Document 1 uses solder balls, when further miniaturization of the device is attempted, there is a limit to miniaturization of the semiconductor device because mutual solder balls interfere with each other. . In this case, if the solder balls are eliminated, it is possible to reduce the size of the semiconductor device. However, when the semiconductor device is surface-mounted on the circuit board, it becomes difficult to form a solder fillet on the semiconductor device. However, there is a problem that sufficient mounting strength cannot be obtained and mountability is lowered.

JP 2005-277034 A

  In view of the above circumstances, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that are reduced in size and improved in mountability.

  The semiconductor device provided by the first aspect of the present invention includes a semiconductor element and a terminal side face that is disposed away from the semiconductor element and faces in a direction perpendicular to the thickness direction of the semiconductor element. And a sealing resin having a resin side surface that covers the semiconductor element and has a resin side surface facing a direction perpendicular to the thickness direction of the semiconductor element. A terminal conductive layer that is exposed from the resin side surface and covers the terminal side surface is formed on the terminal.

  Preferably, in the embodiment of the present invention, the terminal is made of an alloy containing Cu as a main component.

  In the embodiment of the present invention, preferably, the terminal conductive layer includes an alloy layer containing Sn.

  In the embodiment of the present invention, preferably, the terminal conductive layer is composed of an Ni layer and an alloy layer containing Sn stacked on each other.

  In the embodiment of the present invention, preferably, the terminal conductive layer includes an Au layer.

  Preferably, in the embodiment of the present invention, the terminal conductive layer includes a Pd layer and an Au layer stacked on each other.

  Preferably, in the embodiment of the present invention, the terminal conductive layer is composed of a Ni layer, a Pd layer, and an Au layer stacked on each other.

  Preferably, in the embodiment of the present invention, the terminal includes a plurality of the terminal side surfaces, and the terminal side surface is a terminal first side surface facing a first direction perpendicular to the thickness direction of the semiconductor element. And a terminal second side face facing a second direction that is perpendicular to the thickness direction of the semiconductor element and the first direction, and the resin side face is a resin first face facing the first direction. The terminal conductive layer covers either the terminal first side surface or the terminal second side surface. The terminal conductive layer includes a side surface and a resin second side surface facing the second direction.

  In the embodiment of the present invention, preferably, the terminal conductive layer covers the terminal first side surface, and the terminal first side surface is flush with the resin first side surface.

  Preferably, in the embodiment of the present invention, the terminal has a terminal outer surface facing the first direction and projecting outward from the terminal first side surface, and the terminal conductive layer includes the terminal outer surface. Not covered.

  Preferably, in the embodiment of the present invention, the sealing resin has a resin first outer surface that faces the first direction and protrudes outward from the resin first side surface, and the resin first outer surface is , Flush with the outer surface of the terminal.

  Preferably, in the embodiment of the present invention, the terminal conductive layer covers the terminal second side surface, and the terminal second side surface is flush with the resin second side surface.

  In an embodiment of the present invention, preferably, the sealing resin has a resin second outer surface that faces the second direction and protrudes outward from the resin second side surface.

  In an embodiment of the present invention, preferably, the sealing resin has a resin inner side faced in the second direction and positioned closer to the semiconductor element than the resin second side face.

  Preferably, in the embodiment of the present invention, the terminal has a terminal back surface facing the thickness direction of the semiconductor element, and the terminal back surface is exposed from the sealing resin.

  In the embodiment of the present invention, preferably, the terminal conductive layer covers the terminal back surface.

  Preferably, in the embodiment of the present invention, the semiconductor device further includes a die pad having a pad surface and a pad back surface facing opposite sides in the thickness direction of the semiconductor element and made of the same material as the terminal, and the pad surface includes the die pad. A semiconductor element is mounted.

  In the embodiment of the present invention, preferably, the pad back surface is exposed from the sealing resin and is flush with the terminal back surface.

  Preferably, in the embodiment of the present invention, a pad conductive layer is formed on the die pad to cover the back surface of the pad.

  In an embodiment of the present invention, preferably, the configuration of the pad conductive layer is the same as the configuration of the terminal conductive layer.

  In an embodiment of the present invention, preferably, a bonding layer interposed between the semiconductor element and the pad surface is provided.

  In an embodiment of the present invention, preferably, a bonding wire for connecting the semiconductor element and the terminal is provided.

  Preferably, in the embodiment of the present invention, the terminal has a terminal surface facing away from the terminal back surface, and the bonding wire is connected to the terminal surface.

  Preferably, in the embodiment of the present invention, in the thickness direction of the semiconductor element, the pad surface is located between the terminal surface and the terminal back surface.

  In an embodiment of the present invention, preferably, an interior plating layer is provided to cover the terminal surface and the pad surface.

  In an embodiment of the present invention, preferably, the interior plating layer is an Ag layer.

  Preferably, in the embodiment of the present invention, the sealing resin is an epoxy resin containing glass frit.

  In an embodiment of the present invention, the semiconductor element is preferably a Hall element.

  A method of manufacturing a semiconductor device provided by the second aspect of the present invention includes a step of preparing a conductive base material having a back surface facing one side in the thickness direction and including a terminal portion and a pad portion spaced apart from each other. A step of mounting a semiconductor element on the pad portion, a step of forming a sealing resin covering the conductive base material and the semiconductor element so that the back surface of the conductive base material is exposed, and the conductive property Conductivity along either the first direction perpendicular to the thickness direction of the substrate or the second direction that is both perpendicular to the thickness direction of the conductive substrate and the first direction. A step of performing primary cutting for cutting at least part of the conductive substrate, a step of forming a conductive layer covering the terminal portion exposed from the sealing resin, the first direction, and the thickness of the conductive substrate. Both the vertical direction and the first direction A second direction which is angular along the is characterized by and a step of performing secondary cutting for dividing said electrically conductive substrate into pieces.

  In the embodiment of the present invention, preferably, the primary cutting and the secondary cutting are both performed using a dicing saw.

  In the embodiment of the present invention, preferably, in the step of forming the conductive layer, the conductive layer is formed by electrolytic plating.

  Preferably, in the embodiment of the present invention, in the step of performing the primary cutting, a part of the conductive substrate is cut in the thickness direction of the conductive substrate.

  In the embodiment of the present invention, preferably, the step of preparing the conductive substrate includes a step of removing a part of the conductive substrate from the back surface of the conductive substrate.

  Preferably, in the embodiment of the present invention, in the step of performing the primary cutting, all of the conductive substrate is cut in the thickness direction of the conductive substrate.

  Preferably, in the embodiment of the present invention, before the step of forming the sealing resin, a step of attaching an insulating base to the back surface of the conductive base, and a step of forming the sealing resin A step of peeling the insulating base material from the conductive base material between the step of performing the primary cutting.

  In an embodiment of the present invention, preferably, a bonding wire for connecting the semiconductor element and the terminal portion is formed by wire bonding between the step of mounting the semiconductor element and the step of forming the sealing resin. A process is provided.

  According to the semiconductor device of the present invention, the terminal having the terminal side surface exposed from the resin side surface of the sealing resin is provided, and the terminal conductive layer covering the terminal side surface is formed on the terminal. By adopting such a configuration, a solder fillet is formed on the side surface of the terminal when the semiconductor device is mounted, so that the semiconductor device can be reduced in size and mounted.

  Moreover, according to the manufacturing method of the semiconductor device concerning this invention, before the process of forming the conductive layer which covers the terminal part of the conductive base material exposed from sealing resin, with respect to the thickness direction of a conductive base material A step of performing primary cutting for cutting at least a part of the conductive substrate along either the first direction or the second direction that is perpendicular to each other. By performing primary cutting, a conductive layer can be formed on the side surface of the terminal portion by electrolytic plating, and thus the semiconductor device can be manufactured.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a top view (omission of sealing resin) of the semiconductor device concerning a 1st embodiment of the present invention. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 2 is a right side view of the semiconductor device shown in FIG. 1. FIG. 2 is a front view of the semiconductor device shown in FIG. 1. It is sectional drawing which follows the VV line of FIG. It is sectional drawing which follows the VI-VI line of FIG. It is the elements on larger scale of FIG. FIG. 10 is a partial cross-sectional enlarged view of a modification of the semiconductor device shown in FIG. 1. It is sectional drawing which follows the IX-IX line of FIG. FIG. 2 is a block diagram of a circuit to which the semiconductor device shown in FIG. 1 is applied. It is a top view explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing which follows the XII-XII line | wire of FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is a bottom view explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing which follows the XVII-XVII line of FIG. FIG. 9 is a cross-sectional view illustrating a manufacturing method of the semiconductor device shown in FIG. 8. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device shown in FIG. FIG. 9 is a cross-sectional view illustrating a manufacturing method of the semiconductor device shown in FIG. 8. It is a bottom view explaining the manufacturing method of the semiconductor device shown in FIG. It is a top view (a sealing resin is abbreviate | omitted) of the semiconductor device concerning 2nd Embodiment of this invention. FIG. 24 is a bottom view of the semiconductor device shown in FIG. 23. FIG. 24 is a right side view of the semiconductor device shown in FIG. 23. FIG. 24 is a front view of the semiconductor device shown in FIG. 23. It is sectional drawing which follows the XXVII-XXVII line of FIG. It is the elements on larger scale of FIG. FIG. 24 is a partial enlarged view of a first modification of the semiconductor device shown in FIG. 23. FIG. 24 is a partial enlarged view of a second modification of the semiconductor device shown in FIG. 23. FIG. 24 is a plan view illustrating the method for manufacturing the semiconductor device shown in FIG. 23. FIG. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG. 31. FIG. 24 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 23. FIG. 24 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 23. FIG. 24 is a bottom view for explaining the method for manufacturing the semiconductor device shown in FIG. 23. FIG. 36 is a cross-sectional view taken along line XXXVI-XXXVI in FIG. 35. FIG. 30 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 29. FIG. 24 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 23. FIG. 24 is a bottom view for explaining the method for manufacturing the semiconductor device shown in FIG. 23. FIG. 31 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 30.

  A mode for carrying out the present invention (hereinafter referred to as “embodiment”) will be described with reference to the accompanying drawings.

[First Embodiment]
A semiconductor device A10 according to the first embodiment of the present invention will be described with reference to FIGS. The semiconductor device A10 includes a semiconductor element 11, a bonding layer 12, a terminal 2, a die pad 3, a sealing resin 4, an interior plating layer 5, and a bonding wire 6.

  FIG. 1 is a plan view of the semiconductor device A10, and the sealing resin 4 is omitted for convenience of understanding. FIG. 2 is a bottom view of the semiconductor device A10. FIG. 3 is a right side view of the semiconductor device A10. FIG. 4 is a front view of the semiconductor device A10. FIG. 5 is a cross-sectional view taken along the line V-V in FIG. 1 (dashed line shown in FIG. 1). 6 is a cross-sectional view taken along the line VI-VI in FIG. FIG. 7 is a partially enlarged view of FIG. FIG. 8 is a partially enlarged cross-sectional view of a semiconductor device A11 which is a modification of the semiconductor device A10, and the cross-sectional position is the same as FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. Note that the sealing resin 4 omitted in FIG. 1 is indicated by an imaginary line (two-dot chain line).

  The semiconductor device A10 shown in these drawings is of a type that is surface-mounted on circuit boards of various electronic devices such as mobile phones. Here, for convenience of explanation, the left-right direction of the plan view perpendicular to the thickness direction Z of the semiconductor element 11 is either the first direction X or the thickness direction Z of the semiconductor element 11 and the first direction X. Are defined as the second direction Y, respectively. In the present embodiment, the shape of the semiconductor element 11 of the semiconductor device A10 in a plan view (hereinafter simply referred to as “plan view”) as viewed in the thickness direction Z is a rectangular shape.

  The semiconductor element 11 is a central part of the function of the semiconductor device A10. As shown in FIG. 1, the shape of the semiconductor element 11 in plan view is a rectangular shape. The semiconductor element 11 according to the present embodiment is a Hall element. For this reason, the semiconductor device A10 is a magnetic sensor. In the present embodiment, the Hall element is a GaAs Hall element. The GaAs Hall element has an advantage that it is excellent in the linearity of the Hall voltage with respect to a change in magnetic flux density and is hardly affected by a temperature change. As shown in FIGS. 5 and 9, the semiconductor element 11 has an element surface 111 and an element back surface 112 that face opposite sides in the thickness direction Z of the semiconductor element 11. The element surface 111 is a surface in contact with the sealing resin 4. In the present embodiment, a plurality of electrode pads 111 a made of, for example, Al are formed on the element surface 111. A bonding wire 6 is connected to each electrode pad 111a. The element back surface 112 is a surface in contact with the bonding layer 12. The element back surface 112 is used when the semiconductor element 11 is mounted on the die pad 3.

  As shown in FIGS. 1, 5, and 9, the bonding layer 12 is a portion interposed between the semiconductor element 11 and a pad surface 31 of a die pad 3 to be described later. The bonding layer 12 is in contact with both the element back surface 112 of the semiconductor element 11 and the interior plating layer 5 that covers the pad surface 31. The material of the bonding layer 12 according to the present embodiment may be either a conductive material or an electrically insulating material. In the case of a material having conductivity, for example, a synthetic resin (so-called Ag paste) containing an epoxy resin containing Ag as a main component can be given as the material. Moreover, in the case of the material which has electrical insulation, an epoxy resin and a polyimide are mentioned as the said material, for example. The semiconductor element 11 is mounted on the die pad 3 by bonding (die bonding) by the bonding layer 12.

  As shown in FIGS. 1 to 6, the terminal 2 is a portion that has conductivity and constitutes a conductive path between the semiconductor element 11 and the circuit board on which the semiconductor device A <b> 10 is mounted. There are four terminals 2 according to the present embodiment, and the four terminals 2 are arranged apart from each other and from the die pad 3 in the semiconductor device A10. The terminal 2 is made of an integrally formed conductive base material 81 shown in an example of a method for manufacturing the semiconductor device A10 described later. For this reason, the terminal 2 consists of an alloy which has Cu as a main component. As shown in FIGS. 1 to 4, 6 and 7, the terminal 2 has a terminal surface 21, a terminal back surface 22, a terminal side surface 23, a terminal outer surface 241 and a terminal intermediate surface 242. Among these, the terminal side surface 23 includes a terminal first side surface 231 and a terminal second side surface 232. As shown in FIGS. 6 and 7, the terminal 2 according to this embodiment has a terminal conductive layer 28 covering the terminal back surface 22, the terminal first side surface 231 and the terminal intermediate surface 242 exposed from the sealing resin 4. Is formed. The terminal conductive layer 28 according to the present embodiment is an alloy layer containing Sn. The alloy layer is a lead-free solder alloy such as a Sn—Sb alloy or a Sn—Ag alloy. Here, the terminal conductive layer 28 may be composed of an Ni layer and an alloy layer containing Sn stacked on each other. The terminal conductive layer 28 may be composed of a Ni layer, a Pd layer, and an Au layer that are stacked on each other. Further, the terminal conductive layer 28 may have a configuration including a Pd layer and an Au layer stacked on each other, or a configuration including an Au layer. In these terminal conductive layers 28, the Sn-containing alloy layer or Au layer is exposed to the outside.

  As shown in FIGS. 5 and 6, the terminal surface 21 and the terminal back surface 22 are surfaces facing opposite sides in the thickness direction Z of the semiconductor element 11. The terminal surface 21 and the terminal back surface 22 are both rectangular in shape. The terminal surface 21 is a surface facing in the same direction as the element surface 111 of the semiconductor element 11. A bonding wire 6 is connected to the terminal surface 21. The terminal surface 21 is covered with the interior plating layer 5 and further covered with the sealing resin 4 that covers the interior plating layer 5. The terminal back surface 22 is a surface facing the side opposite to the terminal surface 21. The terminal back surface 22 is a surface used when the semiconductor device A10 is mounted on a circuit board. The terminal back surface 22 according to the present embodiment is exposed from the sealing resin 4 and is covered with the terminal conductive layer 28.

  As shown in FIGS. 1 to 4, the terminal side surface 23 is a surface disposed between the terminal surface 21 and the terminal back surface 22. The terminal 2 has a plurality of terminal side surfaces 23, and the terminal side surface 23 includes the terminal first side surface 231 and the terminal second side surface 232 as described above.

  As shown in FIGS. 1 to 4, the terminal first side surface 231 is a surface facing the first direction X. In the thickness direction Z of the semiconductor element 11, one end of the terminal first side surface 231 is connected to the terminal back surface 22. The terminal first side surface 231 according to the present embodiment is exposed from the sealing resin 4 and is covered with the terminal conductive layer 28. 1 to 4, the terminal second side surface 232 is a surface facing the second direction Y. In the thickness direction Z of the semiconductor element 11, one end of the terminal second side surface 232 is connected to the terminal surface 21, and the other end is connected to the terminal back surface 22. The terminal second side surface 232 according to this embodiment is covered with the sealing resin 4.

  As shown in FIGS. 1, 3, 6, and 7, the terminal outer surface 241 is a surface that faces the first direction X and protrudes from the terminal first side surface 231 to the outside of the semiconductor device A10. One end of the terminal outer surface 241 is connected to the terminal surface 21 in the thickness direction Z of the semiconductor element 11. Although the terminal outer surface 241 according to the present embodiment is exposed from the sealing resin 4, it is not covered with the terminal conductive layer 28. As shown in FIGS. 6 and 7, the terminal intermediate surface 242 is a surface that faces the terminal back surface 22 side and connects the terminal first side surface 231 and the terminal outer surface 241. The terminal intermediate surface 242 according to the present embodiment is a curved surface. In the second direction Y, one end of the terminal intermediate surface 242 is connected to the terminal second side surface 232. The terminal intermediate surface 242 according to the present embodiment is exposed from the sealing resin 4 and is covered with the terminal conductive layer 28.

  Here, as shown in FIG. 8, the terminal intermediate surface 242 may be a flat surface facing the terminal back surface 22 side, as in a semiconductor device A <b> 11 that is a modification of the semiconductor device A <b> 10.

  As shown in FIGS. 1 to 5, the terminal 2 according to the present embodiment is formed with a terminal connecting portion 29 extending in the second direction Y from the terminal second side surface 232. The shape of the terminal connecting portion 29 according to the present embodiment is a rectangular parallelepiped shape. The terminal connecting portion 29 has a connecting portion surface 291, a connecting portion back surface 292, and a connecting portion end surface 293. The connecting portion front surface 291 and the connecting portion back surface 292 are surfaces that face each other in the thickness direction Z of the semiconductor element 11 and are flat. The connecting portion surface 291 is flush with the terminal surface 21 and is covered with the interior plating layer 5 like the terminal surface 21. The connecting portion back surface 292 is covered with the sealing resin 4. For this reason, in the thickness direction Z of the semiconductor element 11, the length from the connection portion surface 291 to the connection portion back surface 292 is shorter than the length from the terminal surface 21 to the terminal back surface 22. The connecting portion end surface 293 is a surface that intersects both the connecting portion front surface 291 and the connecting portion back surface 292 and faces the second direction Y. Although the connecting portion end surface 293 according to the present embodiment is exposed from the sealing resin 4, it is not covered with the terminal conductive layer 28.

  As shown in FIGS. 1 to 3, 5, and 9, the die pad 3 is a portion on which the semiconductor element 11 is mounted. The die pad 3 is made of the same conductive substrate 81 as the terminal 2. Therefore, the die pad 3 according to the present embodiment is made of an alloy whose main component is Cu, which is the same material as the terminal 2. For this reason, the die pad 3 has conductivity. However, since the electrode pad 111a is not formed on the element back surface 112 of the semiconductor element 11, the semiconductor element 11 and the die pad 3 are not electrically connected to each other even if the bonding layer 12 has conductivity. As shown in FIGS. 5 and 9, the die pad 3 has a pad surface 31 and a pad back surface 32.

  As shown in FIGS. 5 and 9, the pad surface 31 and the pad back surface 32 are surfaces that face opposite sides in the thickness direction Z of the semiconductor element 11. The pad surface 31 and the pad back surface 32 are both rectangular in shape. The pad surface 31 is a surface facing the element back surface 112 of the semiconductor element 11. The pad surface 31 is covered with the interior plating layer 5. In the interior plating layer 5 covering the pad surface 31, a portion not covered with the bonding layer 12 for mounting the semiconductor element 11 is covered with the sealing resin 4. In the present embodiment, the pad surface 31 is located between the terminal surface 21 and the terminal back surface 22 in the thickness direction Z of the semiconductor element 11. The pad back surface 32 is a surface facing the side opposite to the pad surface 31. The pad back surface 32 according to the present embodiment is exposed from the sealing resin 4 and is flush with the terminal back surface 22 of the terminal 2.

  As shown in FIGS. 2, 5, and 9, a pad conductive layer 38 that covers the pad back surface 32 is formed on the die pad 3. The configuration of the pad conductive layer 38 according to the present embodiment is the same as the configuration of the terminal conductive layer 28. 1, 2, and 9, the die pad 3 according to the present embodiment includes a die pad 3 that intersects both the pad surface 31 and the pad back surface 32 and faces the first direction X. A pair of pad connecting portions 39 extending in the first direction X is formed. The shape of the pad connecting portion 39 according to the present embodiment is a rectangular parallelepiped shape. The pad connecting part 39 has a connecting part surface 391, a connecting part back surface 392, and a connecting part end surface 393. The connection portion front surface 391 and the connection portion back surface 392 are surfaces that are opposite to each other in the thickness direction Z of the semiconductor element 11 and are flat. The connecting portion surface 391 is flush with the pad surface 31 and is covered with the interior plating layer 5 similarly to the pad surface 31. The connecting portion back surface 392 is covered with the sealing resin 4 and the pad conductive layer 38. In the thickness direction Z of the semiconductor element 11, the length from the connection portion surface 391 to the connection portion back surface 392 is shorter than the length from the pad surface 31 to the pad back surface 32. The connecting portion end surface 393 is a pair of surfaces that intersect both the connecting portion front surface 391 and the connecting portion back surface 392 and face the first direction X. Although the pair of connection portion end surfaces 393 according to the present embodiment are both exposed from the sealing resin 4, they are not covered with the pad conductive layer 38. Further, as shown in FIGS. 1, 6, and 9, each connecting portion end surface 393 is flush with the terminal outer surface 241.

  As shown in FIGS. 2 to 6 and 9, the sealing resin 4 is a portion that covers the semiconductor element 11 and a part of each of the terminal 2 and the die pad 3. The sealing resin 4 is a thermosetting synthetic resin having electrical insulation, and the synthetic resin according to the present embodiment is a black epoxy resin. The epoxy resin according to the present embodiment contains glass frit. As shown in FIGS. 2 to 6 and 9, the sealing resin 4 has a resin surface 41, a resin back surface 42, a resin side surface 43, a resin first outer surface 441 and a resin intermediate surface 442.

  As shown in FIGS. 2 to 4, the resin surface 41 and the resin back surface 42 are surfaces that face opposite sides in the thickness direction Z of the semiconductor element 11. The resin surface 41 is a surface facing in the same direction as the element surface 111 of the semiconductor element 11. The resin back surface 42 is a surface facing away from the resin surface 41. As shown in FIG. 2, in this embodiment, the terminal back surface 22 of the terminal 2 and the pad back surface 32 of the die pad 3 are exposed from the resin back surface 42. The resin back surface 42 is flush with the terminal back surface 22 and the pad back surface 32.

  As shown in FIGS. 2 to 4, the resin side surface 43 is a surface disposed between the resin surface 41 and the resin back surface 42. The resin side surface 43 includes a resin first side surface 431 facing the first direction X and a resin second side surface 432 facing the second direction Y.

  As shown in FIGS. 2 to 4, the first resin side surface 431 is a pair of surfaces that are separated from each other in the first direction X and face opposite sides in the first direction X. In the present embodiment, one end of each resin first side surface 431 is connected to the resin back surface 42. In the present embodiment, the terminal first side surface 231 of the terminal 2 is exposed from each resin first side surface 431.

  As shown in FIGS. 2 to 4, the resin second side surface 432 is a pair of surfaces that are separated from each other in the second direction Y and face opposite sides in the second direction Y. In the present embodiment, one end of each resin second side surface 432 is connected to the resin surface 41 and the other end is connected to the resin back surface 42. Moreover, in this embodiment, the connection part end surface 293 of the terminal 2 is exposed from each resin 2nd side surface 432. Each resin second side surface 432 is flush with the connecting portion end surface 293.

  As shown in FIGS. 2 to 4, 6, and 9, the resin first outer surface 441 is a surface that faces the first direction X and protrudes from the resin first side surface 431 to the outside of the semiconductor device A <b> 10. The resin first outer surface 441 according to the present embodiment is a pair of surfaces that are separated from each other in the first direction X and face opposite sides in the first direction X. One end of each resin first outer surface 441 is connected to the resin surface 41 in the thickness direction Z of the semiconductor element 11. Further, in the second direction Y, both ends of each resin first outer surface 441 are connected to a pair of resin second side surfaces 432. In the present embodiment, the terminal outer surface 241 of the terminal 2 and the connecting portion end surface 393 of the die pad 3 are exposed from each resin first outer surface 441. Each resin first outer surface 441 is flush with the terminal outer surface 241 and the connecting portion end surface 393.

  As shown in FIGS. 4 and 9, the resin intermediate surface 442 is a surface facing the resin back surface 42 side and connecting the resin first side surface 431 and the resin first outer surface 441. The resin intermediate surface 442 according to the present embodiment is a curved surface. In the second direction Y, both ends of the resin intermediate surface 442 are connected to the pair of resin second side surfaces 432.

  The interior plating layer 5 is a portion that covers the terminal surface 21 of the terminal 2 and the pad surface 31 of the die pad 3 as shown in FIGS. 1, 5, 6, and 9. In the present embodiment, the interior plating layer 5 also covers the connecting portion surface 291 of the terminal connecting portion 29 and the connecting portion surface 291 of the pad connecting portion 39. The interior plating layer 5 according to the present embodiment is an Ag layer.

  The bonding wire 6 is a part which has electroconductivity and connects the semiconductor element 11 and the terminal 2 as shown in FIGS. The bonding wire 6 according to this embodiment is composed of four wires, and each bonding wire 6 connects the semiconductor element 11 and one terminal 2. The bonding wire 6 according to the present embodiment is made of Au.

  Next, an example of a circuit to which the semiconductor device A10 in which the semiconductor element 11 is a Hall element is applied will be described with reference to FIG. FIG. 10 is a block diagram of a circuit to which the semiconductor device A10 is applied.

  As shown in FIG. 10, the circuit includes a semiconductor device A <b> 10, an integrated circuit 71, and a control target 72. Examples of the control object 72 include a light source of a mobile phone display and a DC motor. The integrated circuit 71 includes a device drive area 711, a voltage detection area 712, and a control area 713. The device drive region 711 is a region in which a hole current flows through the semiconductor element 11 of the semiconductor device A10. The voltage detection region 712 is a region for detecting an electromotive force (Hall voltage) that appears in the semiconductor element 11 due to the Hall effect. The control area 713 is an area for controlling the operation of the control object 72. Now, when the magnet 73 is brought close to the semiconductor device A10, the magnetic flux density changes, so that an electromotive force appears in the semiconductor element 11 due to the Hall effect. The electromotive force is detected by the voltage detection region 712. The voltage detection area 712 transmits this detection result to the control area 713. The control area 713 controls (starts, stops, etc.) the operation of the control target 72 based on the transmitted detection result.

  Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to FIGS.

  FIG. 11 is a plan view illustrating the method for manufacturing the semiconductor device A10. 12 is a cross-sectional view taken along line XII-XII in FIG. 13 to 15 and FIG. 19 are cross-sectional views illustrating a method for manufacturing the semiconductor device A10, and the cross-sectional positions thereof are the same as those in FIG. 16 and 22 are bottom views illustrating the method for manufacturing the semiconductor device A10. 17 is a cross-sectional view taken along line XVII-XVII in FIG. FIG. 20 is a cross-sectional view illustrating the method for manufacturing the semiconductor device A10, and the cross-sectional position thereof is the same as FIG. 18 and 21 are cross-sectional views illustrating a method for manufacturing a semiconductor device A11 that is a modification of the semiconductor device A10, and the cross-sectional positions thereof are the same as those in FIG. The definition of the thickness direction Z, the first direction X, and the second direction Y of the conductive substrate 81 shown in FIGS. 11 to 22 is the thickness direction Z of the semiconductor element 11 shown in FIGS. , Corresponding to the definition of the first direction X and the second direction Y.

  First, as shown in FIGS. 11 and 12, a conductive substrate 81 is prepared. The conductive substrate 81 has a back surface 810b facing one side in the thickness direction Z of the conductive substrate 81 and a front surface 810a facing the other. The conductive substrate 81 includes a terminal portion 811, a terminal first connecting portion 811a, a terminal second connecting portion 811b, a pad portion 812, a pad connecting portion 812a, a first tie bar 813, and a second tie bar 814. As described above, the conductive substrate 81 according to this embodiment is made of an alloy containing Cu as a main component. In the conductive base material 81, the thickness from the back surface 810b to the front surface 810a of the terminal portion 811 is 100 to 200 μm.

  The terminal portion 811 and the pad portion 812 are portions indicated by oblique lines in FIG. The terminal portion 811 is a portion that has a rectangular shape in plan view with the first direction X as a long side and serves as a base of the terminal 2 of the semiconductor device A10. The pad portion 812 is a portion having a substantially square shape in plan view and serving as a base of the die pad 3 of the semiconductor device A10. In the conductive substrate 81, the terminal portion 811 and the pad portion 812 are arranged to be separated from each other. A region 89 indicated by an imaginary line in FIG. 11 corresponds to a portion to be the semiconductor device A10. For this reason, in the conductive base material 81, the pad portion 812 and the four terminal portions 811 arranged around the pad portion 812 constitute a manufacturing unit of one semiconductor device A 10. The manufacturing unit of this one semiconductor device A10 is partitioned by a first tie bar 813 arranged in parallel in the second direction Y and a second tie bar 814 arranged in parallel in the first direction X. The terminal portion 811 is connected to the first tie bar 813 by a terminal first connecting portion 811 a extending in the first direction X. The terminal portion 811 is connected to the second tie bar 814 by a terminal second connecting portion 811b extending in the second direction Y. The pad portion 812 is connected to the first tie bar 813 by a pair of pad connecting portions 812a extending in the first direction X. In the present embodiment, the terminal second connecting portion 811b is a portion that becomes a base of the terminal connecting portion 29 of the semiconductor device A10. Further, the pad connecting portion 812a is a portion that becomes a base of the pad connecting portion 39 of the semiconductor device A10.

The surface 810a is a surface facing upward of the conductive substrate 81 shown in FIG. In the present embodiment, the surface 810 a of the pad portion 812 is positioned closer to the back surface 810 b than the surface 810 a of the terminal portion 811 in the thickness direction Z of the conductive base material 81. The surface 810a is covered with an interior plating layer 815 that is an Ag layer. The interior plating layer 815 corresponds to the interior plating layer 5 of the semiconductor device A10. The interior plating layer 815 is formed by electrolytic plating. The back surface 810b is a surface facing the opposite side to the front surface 810a in the terminal portion 811 and the pad portion 812. Also, as shown in FIG. 12, in the terminal second connecting portion 811b connected to the terminal portion 811, the back surface 810b does not appear, but instead has an inner surface 810c facing away from the front surface 810a. In the present embodiment, the back surface 810b does not appear in the terminal first connection portion 811a, the pad connection portion 812a, the first tie bar 813, and the second tie bar 814 in addition to the terminal second connection portion 811b. Have. The inner surface 810 c is located between the back surface 810 b and the front surface 810 a of the terminal portion 811 in the thickness direction Z of the conductive base material 81. The inner surface 810c is a surface that appears by removing a part of the conductive substrate 81 from the back surface 810b of the conductive substrate 81, for example, by wet etching. For this reason, the step of preparing the conductive substrate 81 includes a step of removing a part of the conductive substrate 81 from the back surface 810 b of the conductive substrate 81. Examples of the solution used for the wet etching include a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ).

  Next, as illustrated in FIG. 13, the semiconductor element 821 is mounted on the pad portion 812. The semiconductor element 821 corresponds to the semiconductor element 11 of the semiconductor device A10. In mounting the semiconductor element 821, first, the bonding material 822 is applied to the interior plating layer 815 formed on the surface 810 a of the pad portion 812. The bonding material 822 according to the present embodiment is a synthetic resin (so-called Ag paste) mainly composed of an epoxy resin containing Ag, and has conductivity. The bonding material 822 may be an electrically insulating material such as an epoxy resin or polyimide. Next, the semiconductor element 821 adsorbed by a collet or the like is transferred onto the pad portion 812 and bonded to the bonding material 822. Finally, the bonding material 822 is thermally cured in a curing furnace or the like. At this time, the thermosetting bonding material 822 corresponds to the bonding layer 12 of the semiconductor device A10.

  Next, as shown in FIG. 14, a bonding wire 83 that connects the semiconductor element 821 and the terminal portion 811 is formed. The bonding wire 83 corresponds to the bonding wire 6 of the semiconductor device A10. The bonding wire 83 is formed by wire bonding. The material of the bonding wire 83 according to the present embodiment is, for example, Au.

  Next, as shown in FIG. 15, a sealing resin 84 that covers the conductive substrate 81 and the semiconductor element 821 is formed. The sealing resin 84 corresponds to the sealing resin 4 of the semiconductor device A10. The sealing resin 84 according to the present embodiment is formed by thermally curing a black epoxy resin having electrical insulation and fluidity and containing glass frit by transfer molding. In the present embodiment, the sealing resin 84 is formed so that the back surface 810b of the conductive substrate 81 is exposed. At this time, the inner surface 810 c of the conductive substrate 81 is covered with the sealing resin 84.

  Next, primary cutting is performed to cut at least a part of the conductive substrate 81 along either the first direction X or the second direction Y. In the present embodiment, as shown in FIGS. 16 and 17, a part of each of the terminal portion 811 and the sealing resin 84 of the conductive base material 81 is cut along the second direction Y. At this time, the second tie bar 814 is not cut by the primary cutting. The primary cutting is performed using a dicing saw from the back surface 810b of the conductive substrate 81. A portion to be subjected to primary cutting is a primary cutting region 85 indicated by an imaginary line in FIG. FIG. 17 shows a state of the conductive substrate 81 when the primary cutting is performed. As the blade 859 of the dicing saw according to the present embodiment, a blade whose tip surface is a curved surface is applied. A base material primary cut surface 851 appears from a part of the terminal portion 811 removed by the blade 859 by the primary cutting. The base material primary cut surface 851 according to the present embodiment includes a pair of surfaces facing the first direction X and a curved surface connecting the pair of surfaces and facing the back surface 810b side. The substrate primary cut surface 851 has a shape along the tip surface of the blade 859.

  Further, in the manufacture of the semiconductor device A11 which is a modification of the semiconductor device A10, as shown in FIG. 18, primary cutting is performed using a dicing saw to which a blade 859 having a wedge-shaped tip surface is applied. At this time, the base material primary cut surface 851 that appears in the terminal portion 811 by the primary cutting is a V-shaped surface that connects the pair of surfaces facing the first direction X and the pair of surfaces to each other and faces the back surface 810b side. It consists of.

  Next, as shown in FIGS. 19 and 20, a conductive layer 86 covering the terminal portion 811 exposed from the sealing resin 84 is formed. The conductive layer 86 covering the terminal portion 811 corresponds to the terminal conductive layer 28 of the semiconductor device A10. In this embodiment, since the back surface 810b of the terminal portion 811 and the base material primary cut surface 851 are exposed from the sealing resin 84, the conductive layer 86 is formed so as to cover these surfaces. The conductive layer 86 according to this embodiment is formed by electrolytic plating. The conductive layer 86 according to this embodiment is formed by depositing an Sn-containing alloy layer, but may be deposited by an Ni layer and an Sn-containing alloy layer in this order. The conductive layer 86 may be deposited in the order of the Ni layer, the Pd layer, and the Au layer, and may further be deposited in the order of the Pd layer and the Au layer, or may be deposited from the Au layer. In these cases, the outermost layer of the conductive layer 86 is an alloy layer or an Au layer containing Sn. At this time, as shown in FIG. 19, since the back surface 810b of the pad portion 812 is also exposed from the sealing resin 84, a conductive layer 86 covering the back surface 810b is also formed. The conductive layer 86 covering the pad portion 812 corresponds to the pad conductive layer 38 of the semiconductor device A10. For this reason, the configuration of the pad conductive layer 38 is the same as the configuration of the terminal conductive layer 28.

  Also in the manufacture of the semiconductor device A11, which is a modification of the semiconductor device A10, as shown in FIG. 21, the conductive layer 86 along the base material primary cut surface 851 is formed.

  Next, as shown in FIG. 22, along the first direction X and the second direction Y, secondary cutting that divides the conductive substrate 81 into individual pieces is performed. In the secondary cutting, a dicing saw is used to cut from the back surface 810b of the conductive substrate 81 in the same manner as the primary cutting described above. The portion to be subjected to secondary cutting is a secondary cutting region 87 indicated by hatching in FIG. The individual pieces divided in this process become the semiconductor device A10. Further, when the primary cutting as shown in FIG. 18 is performed, the semiconductor device A11 in which the terminal intermediate surface 242 shown in FIG. 8 is a flat surface is obtained. The semiconductor device A10 is manufactured through the above steps.

  Next, functions and effects of the semiconductor device A10 and its manufacturing method will be described.

  The semiconductor device A <b> 10 includes a semiconductor element 11, a terminal 2 having a terminal side surface 23 facing a direction (first direction X and second direction Y) perpendicular to the thickness direction Z of the semiconductor element 11, and the semiconductor element 11. And a sealing resin 4 having a resin side surface 43 facing the first direction X and the second direction Y. The terminal side surface 23 (terminal first side surface 231 in the present embodiment) is exposed from the resin side surface 43 (resin first side surface 431 in the present embodiment), and the terminal 2 has a terminal conductive layer 28 covering the terminal side surface 23. Is formed. By adopting such a configuration, when the semiconductor device A10 is mounted on the circuit board by the reflow method, the terminal conductive layer 28 is melted and integrated with the cream solder, and a solder fillet can be formed on the terminal side surface 23. For this reason, the mounting strength of the semiconductor device A10 on the circuit board can be improved, and the occurrence of defects such as cracks in the solder joints can be suppressed. Therefore, according to the semiconductor device A10, it is possible to reduce the size of the device and improve the mountability.

  The terminal conductive layer 28 according to the present embodiment is an alloy layer containing Sn. In this case, when the semiconductor device A10 is mounted on the circuit board by the reflow method, the terminal conductive layer 28 is melted and integrated with the cream solder, so that a solder fillet can be formed on the terminal first side surface 231. In addition, by configuring the terminal conductive layer 28 to be an Ni layer and an Sn-containing alloy layer laminated on each other, the terminal 2 can be protected from thermal shock in mounting the semiconductor device A10. Further, the configuration of the terminal conductive layer 28 is made of the Ni layer, the Pd layer, and the Au layer stacked on each other, so that in the mounting of the semiconductor device A10, the terminal 2 is protected from the thermal shock and the cream solder for the terminal 2 is protected. The wettability can be improved.

  The terminal 2 according to the present embodiment has a terminal outer surface 241 that faces the first direction X and protrudes outward from the terminal first side surface 231 and is not covered with the terminal conductive layer 28. The resin side surface 43 is flush with the resin first side surface 431. By taking such a configuration, it is possible to prevent the occurrence of a problem that the conductive layer 86 is cut by secondary cutting of the conductive base material 81 in the manufacture of the semiconductor device A10.

  The pad surface 31 of the die pad 3 according to the present embodiment is located between the terminal surface 21 and the terminal back surface 22 of the terminal 2 in the thickness direction Z of the semiconductor element 11. By adopting such a configuration, since the position of the element surface 111 of the semiconductor element 11 is closer to the terminal surface 21 in the thickness direction Z of the semiconductor element 11, it is possible to reduce the height of the device. .

  The semiconductor device A <b> 10 includes an interior plating layer 5 that covers the terminal surface 21 of the terminal 2 and the pad surface 31 of the die pad 3. By providing the interior plating layer 5, the terminal 2 and the die pad 3 can be protected from thermal shock that occurs when the bonding wire 6 is connected to the terminal 2 or when the semiconductor element 11 is mounted on the die pad 3.

  The sealing resin 4 according to the present embodiment is an epoxy resin containing glass frit. By applying such a sealing resin 4, the strength of the sealing resin 4 can be increased and the occurrence of cracks in the sealing resin 4 can be suppressed.

  Moreover, according to the manufacturing method of the semiconductor device A10 according to the present embodiment, the first direction X is performed before the step of forming the conductive layer 86 that covers the terminal portion 811 of the conductive base material 81 exposed from the sealing resin 84. Or the process of performing the primary cutting | disconnection which cuts at least one part of the electroconductive base material 81 along either of the 2nd directions Y is provided. By performing the primary cutting, the conductive layer 86 can be formed on the side surface of the terminal portion 811 by electrolytic plating, and thus the semiconductor device A10 can be manufactured.

  In the step of performing the primary cutting according to the present embodiment, a part of the terminal portion 811 of the conductive substrate 81 is primarily cut along the second direction Y in the thickness direction Z of the conductive substrate 81. For this reason, the conductive substrate 81 is in a state in which conduction is ensured in both the first direction X and the second direction Y, and the conductive layer 86 can be formed by electrolytic plating.

  The step of preparing the conductive substrate 81 according to the present embodiment includes a step of removing a part of the cross section along the thickness direction Z of the conductive substrate 81 by, for example, wet etching. By performing such a process, when the sealing resin 84 is formed, the synthetic resin melted in the mold travels in the thickness direction Z of the conductive base material 81 without any problem. For this reason, the quality of the semiconductor device A10 can be ensured.

[Second Embodiment]
A semiconductor device A20 according to the second embodiment of the present invention will be described with reference to FIGS. In these drawings, the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 23 is a plan view of the semiconductor device A20, and the sealing resin 4 is omitted for convenience of understanding. FIG. 24 is a bottom view of the semiconductor device A20. FIG. 25 is a right side view of the semiconductor device A20. FIG. 26 is a front view of the semiconductor device A20. 27 is a cross-sectional view taken along the line XXVII-XXVII in FIG. 23 (the chain line shown in FIG. 23). FIG. 28 is a partially enlarged view of FIG. FIG. 29 is a partial enlarged cross-sectional view of a semiconductor device A21 that is a modification of the semiconductor device A20. FIG. 30 is a partial enlarged cross-sectional view of a semiconductor device A22 that is a modification of the semiconductor device A20. 29 and 30 are the same in cross-sectional position as FIG. Note that the sealing resin 4 omitted in FIG. 23 is indicated by an imaginary line.

  The semiconductor device A20 according to the present embodiment is different from the semiconductor device A10 described above in the configuration of the terminal 2, the die pad 3, and the sealing resin 4. The shape of the semiconductor device A20 according to the present embodiment in a plan view is a rectangular shape.

  As shown in FIGS. 23 to 27, the terminal outer surface 241 and the terminal intermediate surface 242 do not appear in the terminal 2 according to the present embodiment, and the terminal connecting portion 29 is not formed. The terminal 2 according to the present embodiment has a terminal surface 21, a terminal back surface 22, and a terminal side surface 23. Further, the terminal side surface 23 includes a terminal first side surface 231 and a terminal second side surface 232 in the same manner as the semiconductor device A10.

  As shown in FIGS. 24 to 26, the terminal first side surface 231 is exposed from the resin first side surface 431 of the resin side surface 43 and is flush with the resin first side surface 431. In the present embodiment, the terminal first side surface 231 is not covered with the terminal conductive layer 28. As shown in FIGS. 24 to 27, the terminal second side surface 232 is exposed from the resin second side surface 432 of the resin side surface 43 and is flush with the resin second side surface 432. In the present embodiment, the terminal second side surface 232 is covered with the terminal conductive layer 28.

  As shown in FIGS. 23 to 25, in the die pad 3 according to the present embodiment, the connecting portion back surface 392 of the pad connecting portion 39 is flush with the pad back surface 32. For this reason, in the thickness direction Z of the semiconductor element 11, the length from the connection portion surface 391 to the connection portion back surface 392 is equal to the length from the pad surface 31 to the pad back surface 32.

  As shown in FIGS. 24 to 27, the sealing resin 4 according to the present embodiment includes a resin second outer surface 443 and a resin intermediate surface 442 in addition to the resin surface 41, the resin back surface 42, and the resin side surface 43. As shown in FIGS. 24, 25, 27, and 28, the resin second outer side surface 443 faces the second direction Y and protrudes from the resin second side surface 432 of the resin side surface 43 to the outside of the semiconductor device A 20. Surface. The resin second outer side surface 443 according to the present embodiment is a pair of surfaces that are separated from each other in the second direction Y and face opposite sides in the second direction Y. One end of each resin second outer surface 443 is connected to the resin surface 41 in the thickness direction Z of the semiconductor element 11. Further, in the first direction X, both ends of each resin second outer side surface 443 are connected to a pair of resin first side surfaces 431. As shown in FIGS. 24, 25, 27, and 28, the resin intermediate surface 442 faces the resin back surface 42 and connects the resin second side surface 432 and the resin second outer surface 443. . The resin intermediate surface 442 according to the present embodiment is a curved surface. In the first direction X, both ends of the resin intermediate surface 442 are connected to the pair of resin first side surfaces 431.

  Here, as shown in FIG. 29, the resin intermediate surface 442 may be a flat surface facing the resin back surface 42 side, as in a semiconductor device A21 which is a modification of the semiconductor device A20.

  Further, as shown in FIG. 30, the sealing resin 4 may have a resin inner side surface 444 instead of the resin second outer side surface 443 as in a semiconductor device A22 which is a modified example of the semiconductor device A20. Good. The resin inner side surface 444 is a surface that faces the second direction Y and is located closer to the semiconductor element 11 than the resin second side surface 432. In this case, the resin intermediate surface 442 is a surface facing the resin surface 41 side and connecting the resin second side surface 432 and the resin inner side surface 444.

  Next, an example of a method for manufacturing the semiconductor device A20 will be described with reference to FIGS.

  FIG. 31 is a plan view for explaining the method for manufacturing the semiconductor device A20. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG. 33 and 34 are cross-sectional views illustrating a method for manufacturing the semiconductor device A20, and the cross-sectional positions thereof are the same as those in FIG. 35 and 39 are bottom views for explaining the method for manufacturing the semiconductor device A20. 36 is a cross-sectional view taken along line XXXVI-XXXVI in FIG. FIG. 37 is a cross-sectional view illustrating a method for manufacturing a semiconductor device A21 that is a modification of the semiconductor device A20. FIG. 38 is a cross-sectional view illustrating the method for manufacturing the semiconductor device A20. FIG. 40 is a cross-sectional view illustrating a method for manufacturing a semiconductor device A22 that is a modification of the semiconductor device A20. 37, FIG. 38 and FIG. 40 have the same cross-sectional position as FIG.

  First, as shown in FIGS. 31 and 32, a conductive substrate 81 is prepared. In FIG. 31, hatched portions are a terminal portion 811 and a pad portion 812. Further, a region 89 indicated by an imaginary line in FIG. 31 corresponds to a portion to be the semiconductor device A20. In the conductive base material 81 according to the present embodiment, the size of the terminal portion 811 is larger than the terminal portion 811 of the conductive base material 81 for manufacturing the semiconductor device A10, and the terminal second connecting portion 811b is omitted. Yes. The terminal portion 811 is directly connected to the second tie bar 814. Moreover, as shown in FIG. 32, the inner surface 810c does not appear in the conductive base material 81 according to the present embodiment. That is, the step of preparing the conductive substrate 81 according to the present embodiment does not include the step of removing a part of the conductive substrate 81 from the back surface 810b of the conductive substrate 81.

  Next, as shown in FIG. 33, an insulating base material 88 is attached to the back surface 810 b of the conductive base material 81. The insulating base 88 is, for example, a tape having electrical insulation. The insulating substrate 88 is preferably flat. At this time, the back surface 810 b of the conductive substrate 81 is covered with the insulating substrate 88.

  Next, the semiconductor element 821 is mounted on the pad portion 812. Since this process is the same as the process for manufacturing the semiconductor device A10 shown in FIG. 13, the description thereof is omitted here.

  Next, a bonding wire 83 that connects the semiconductor element 821 and the terminal portion 811 is formed. Since this process is the same as the process for manufacturing the semiconductor device A10 shown in FIG. 14, the description thereof is omitted here.

  Next, a sealing resin 84 that covers the conductive substrate 81 and the semiconductor element 821 is formed. Since this process is the same as the process for manufacturing the semiconductor device A10 shown in FIG. 15, the description thereof is omitted here.

  Next, as shown in FIG. 34, the insulating substrate 88 is peeled from the conductive substrate 81. At this time, the back surface 810 b of the conductive substrate 81 is exposed from the sealing resin 84.

  Next, primary cutting is performed to cut at least a part of the conductive substrate 81 along either the first direction X or the second direction Y. In the present embodiment, as shown in FIGS. 35 and 36, all of the terminal portions 811 and the first tie bars 813 of the conductive base material 81 and a part of the sealing resin 84 are arranged along the first direction X. Disconnect. The primary cutting is performed using a dicing saw from the back surface 810b of the conductive substrate 81. A portion to be subjected to primary cutting is a primary cutting region 85 indicated by an imaginary line in FIG. FIG. 36 shows a state of the conductive substrate 81 when the primary cutting is performed. As the blade 859 of the dicing saw according to the present embodiment, a blade whose tip surface is a curved surface is applied. A base material primary cut surface 851 and a resin primary cut surface 852 appear from a part of the terminal portion 811 and the sealing resin 84 removed by the blade 859 by the primary cutting. The base material primary cut surface 851 according to the present embodiment is a pair of surfaces facing the second direction Y appearing at the terminal portion 811. The resin primary cut surface 852 is composed of a pair of surfaces facing the second direction Y appearing on the sealing resin 84 and a curved surface facing the back surface 810b side, and connects the pair of base material primary cut surfaces 851 to each other. Yes.

  In the manufacture of the semiconductor device A21 which is a modification of the semiconductor device A20, as shown in FIG. 37, primary cutting is performed using a dicing saw to which a blade 859 having a wedge-shaped tip surface is applied. At this time, the resin primary cut surface 852 that appears in the sealing resin 84 by the primary cut is a V-shaped surface that connects the pair of surfaces facing the second direction Y and the pair of surfaces to each other and faces the back surface 810b. It consists of.

  Next, as shown in FIG. 38, a conductive layer 86 that covers the terminal portion 811 exposed from the sealing resin 84 is formed. In this embodiment, since the back surface 810b of the terminal portion 811 and the base material primary cut surface 851 are exposed from the sealing resin 84, the conductive layer 86 is formed so as to cover these surfaces. The configuration and formation method of the conductive layer 86 according to the present embodiment are the same as the configuration and formation method of the conductive layer 86 according to the manufacture of the semiconductor device A10. At this time, since the back surface 810b of the pad portion 812 is also exposed from the sealing resin 84, a conductive layer 86 covering the back surface 810b is formed together.

  Next, as shown in FIG. 39, secondary cutting that divides the conductive substrate 81 into individual pieces is performed along the first direction X and the second direction Y. In the secondary cutting, a dicing saw is used in the same manner as the primary cutting described above. The portion to be subjected to the secondary cutting is a secondary cutting region 87 indicated by hatching in FIG. In the present embodiment, secondary cutting is performed from the back surface 810 b of the conductive base material 81. The pieces separated by performing such secondary cutting become the semiconductor device A20 in which the resin second outer side surface 443 shown in FIG. Further, when the primary cutting as shown in FIG. 37 is performed, the semiconductor device A21 in which the resin intermediate surface 442 shown in FIG. 29 is a flat surface is obtained. Furthermore, after performing the primary cutting as shown in FIG. 36 and then performing the secondary cutting from the surface 810a of the conductive substrate 81 along the cutting line CL shown in FIG. 40, the resin shown in FIG. The inner surface 444 is the semiconductor device A22 formed in the sealing resin 4. The semiconductor device A20 is manufactured through the above steps.

  Next, functions and effects of the semiconductor device A20 will be described.

  Similarly to the semiconductor device A10 described above, the semiconductor device A20 has the semiconductor element 11 and the terminal side surface 23 facing the direction perpendicular to the thickness direction Z of the semiconductor element 11 (first direction X and second direction Y). And a sealing resin 4 that covers the semiconductor element 11 and has a resin side surface 43 facing the first direction X and the second direction Y. The terminal side surface 23 (terminal second side surface 232 in the present embodiment) is exposed from the resin side surface 43 (resin second side surface 432 in the present embodiment), and the terminal 2 has a terminal conductive layer 28 covering the terminal side surface 23. Is formed. Therefore, the semiconductor device A20 can also reduce the size of the device and improve the mountability.

  When the thickness of the conductive substrate 81 for manufacturing the semiconductor device A20 is the same as the thickness of the conductive substrate 81 for manufacturing the semiconductor device A10, the terminal second side surface 232 covered by the terminal conductive layer 28 is formed. The area is larger than the area of the terminal first side surface 231 covered with the terminal conductive layer 28 in the semiconductor device A10. For this reason, in the semiconductor device A20, the size of the solder fillet formed on the terminal second side surface 232 is larger than the size of the solder fillet formed on the semiconductor device A10, and the mountability can be further improved.

  In addition, even in the method for manufacturing the semiconductor device A20 according to the present embodiment, the first direction X or the first direction X or before the step of forming the conductive layer 86 covering the terminal portion 811 of the conductive base material 81 exposed from the sealing resin 84 is performed. A step of performing primary cutting for cutting at least a part of the conductive substrate 81 along any one of the second directions Y is provided. By performing the primary cutting, the conductive layer 86 can be formed on the side surface of the terminal portion 811 by electrolytic plating, and thus the semiconductor device A20 can be manufactured.

  In the step of performing the primary cutting according to the present embodiment, all of the terminal portions 811 of the conductive substrate 81 are primarily cut along the first direction X in the thickness direction Z of the conductive substrate 81. In this case, the conductive substrate 81 is in a state in which conduction is ensured in the first direction X, and the conductive layer 86 can be formed by electrolytic plating.

  In the method for manufacturing the semiconductor device A20 according to the present embodiment, before the step of forming the sealing resin 84, the step of attaching the insulating base 88 to the back surface 810b of the conductive base 81, and the sealing resin 84 The process of peeling the insulating base material 88 from the electroconductive base material 81 is provided between the process of forming and the process of performing primary cutting. By performing such a process, when the sealing resin 84 is formed, the synthetic resin melted in the mold travels in the thickness direction Z of the conductive base material 81 without any problem. For this reason, the quality of the semiconductor device A20 can be ensured.

  The present invention is not limited to the embodiment described above. The specific configuration of each part of the present invention can be changed in various ways.

A10, A11, A20, A21, A22: Semiconductor device 11: Semiconductor element (Hall element)
111: Element surface 111a: Electrode pad 112: Element back surface 12: Bonding layer 2: Terminal 21: Terminal surface 22: Terminal back surface 23: Terminal side surface 231: Terminal first side surface 232: Terminal second side surface 241: Terminal outer surface 242: Terminal intermediate surface 28: Terminal conductive layer 29: Terminal connecting portion 291: Connecting portion surface 292: Connecting portion back surface 293: Connecting portion end surface 3: Die pad 31: Pad surface 32: Pad back surface 38: Pad conductive layer 39: Pad connecting portion 391 : Connection part surface 392: Connection part back surface 393: Connection part end face 4: Sealing resin 41: Resin surface 42: Resin side face 43: Resin side face 431: Resin first side face 432: Resin second side face 441: Resin first outside face 442: Resin intermediate surface 443: Resin second outer surface 444: Resin inner surface 5: Interior plating layer 6: Bonding wire 71: Integrated circuit 7 1: Device drive region 712: Voltage detection region 713: Control region 72: Control target 73: Magnet 81: Conductive substrate 810a: Front surface 810b: Back surface 810c: Inner surface 811: Terminal portion 811a: Terminal first connecting portion 811b: Terminal 2nd connection part 812: Pad part 812a: Pad connection part 813: 1st tie bar 814: 2nd tie bar 815: Interior plating layer 821: Semiconductor element 822: Bonding material 83: Bonding wire 84: Sealing resin 85: Primary cutting area 851: Substrate primary cut surface 852: Resin primary cut surface 859: Blade 86: Conductive layer 87: Secondary cut region 88: Insulating substrate 89: Region Z: Thickness direction X: First direction Y: Second direction CL: Cutting line

Claims (36)

A semiconductor element;
A terminal having a terminal side surface that is disposed apart from the semiconductor element and faces a direction perpendicular to the thickness direction of the semiconductor element;
A sealing resin that covers the semiconductor element and has a resin side surface facing a direction perpendicular to the thickness direction of the semiconductor element,
The terminal side surface is exposed from the resin side surface,
A terminal device is provided with a terminal conductive layer that covers the terminal side surface.   The semiconductor device according to claim 1, wherein the terminal is made of an alloy containing Cu as a main component.   The semiconductor device according to claim 1, wherein the terminal conductive layer includes an alloy layer containing Sn.   The semiconductor device according to claim 3, wherein the terminal conductive layer is composed of an Ni layer and an alloy layer containing Sn stacked on each other.   The semiconductor device according to claim 1, wherein the terminal conductive layer includes an Au layer.   The semiconductor device according to claim 5, wherein the terminal conductive layer includes a Pd layer and an Au layer stacked on each other.   The semiconductor device according to claim 6, wherein the terminal conductive layer includes a Ni layer, a Pd layer, and an Au layer that are stacked on each other. The terminal has a plurality of terminal side surfaces,
The terminal side surface is a terminal first side surface facing a first direction that is perpendicular to the thickness direction of the semiconductor element, and the terminal side surface is perpendicular to both the thickness direction of the semiconductor element and the first direction. A terminal second side surface facing in two directions,
The resin side surface includes a resin first side surface facing the first direction and a resin second side surface facing the second direction,
The semiconductor device according to claim 1, wherein the terminal conductive layer covers either the terminal first side surface or the terminal second side surface.   The semiconductor device according to claim 8, wherein the terminal conductive layer covers the terminal first side surface, and the terminal first side surface is flush with the resin first side surface.   10. The terminal according to claim 9, wherein the terminal has a terminal outer surface facing the first direction and projecting outward from the terminal first side surface, and the terminal conductive layer does not cover the terminal outer surface. Semiconductor device.   The sealing resin has a resin first outer surface that faces the first direction and protrudes outward from the resin first side surface, and the resin first outer surface is flush with the terminal outer surface. The semiconductor device according to claim 10.   The semiconductor device according to claim 8, wherein the terminal conductive layer covers the terminal second side surface, and the terminal second side surface is flush with the resin second side surface.   The semiconductor device according to claim 12, wherein the sealing resin has a resin second outer surface that faces the second direction and protrudes outward from the resin second side surface.   The semiconductor device according to claim 12, wherein the sealing resin has a resin inner side faced in the second direction and positioned closer to the semiconductor element than the resin second side face.   The semiconductor device according to claim 1, wherein the terminal has a terminal back surface facing a thickness direction of the semiconductor element, and the terminal back surface is exposed from the sealing resin.   The semiconductor device according to claim 15, wherein the terminal conductive layer covers the terminal back surface. A pad surface having a pad surface and a pad back surface facing each other in the thickness direction of the semiconductor element, and a die pad made of the same material as the terminal;
The semiconductor device according to claim 15, wherein the semiconductor element is mounted on the pad surface.   The semiconductor device according to claim 17, wherein the pad back surface is exposed from the sealing resin and is flush with the terminal back surface.   The semiconductor device according to claim 18, wherein a pad conductive layer covering the back surface of the pad is formed on the die pad.   20. The semiconductor device according to claim 19, wherein the configuration of the pad conductive layer is the same as the configuration of the terminal conductive layer.   21. The semiconductor device according to claim 17, further comprising a bonding layer interposed between the semiconductor element and the pad surface.   The semiconductor device according to claim 17, further comprising a bonding wire that connects the semiconductor element and the terminal.   23. The semiconductor device according to claim 22, wherein the terminal has a terminal surface that faces away from the terminal back surface, and the bonding wire is connected to the terminal surface.   24. The semiconductor device according to claim 23, wherein the pad surface is located between the terminal surface and the terminal back surface in the thickness direction of the semiconductor element.   The semiconductor device of Claim 23 or 24 provided with the interior plating layer which covers the said terminal surface and the said pad surface.   The semiconductor device according to claim 25, wherein the interior plating layer is an Ag layer.   27. The semiconductor device according to claim 1, wherein the sealing resin is an epoxy resin containing glass frit.   28. The semiconductor device according to claim 1, wherein the semiconductor element is a Hall element. Providing a conductive substrate having a back surface facing one side in the thickness direction and including a terminal portion and a pad portion spaced apart from each other;
Mounting a semiconductor element on the pad portion;
Forming a sealing resin that covers the conductive substrate and the semiconductor element such that the back surface of the conductive substrate is exposed;
Along either the first direction perpendicular to the thickness direction of the conductive substrate or the second direction perpendicular to the thickness direction of the conductive substrate and the first direction. Performing a primary cutting to cut at least a part of the conductive base material,
Forming a conductive layer covering the terminal portion exposed from the sealing resin;
Secondary cutting that divides the conductive base material into pieces along the first direction and a second direction that is perpendicular to the thickness direction of the conductive base material and the first direction. And a method for manufacturing a semiconductor device.   30. The method of manufacturing a semiconductor device according to claim 29, wherein the primary cutting and the secondary cutting are both performed using a dicing saw.   31. The method for manufacturing a semiconductor device according to claim 29, wherein in the step of forming the conductive layer, the conductive layer is formed by electrolytic plating.   32. The method of manufacturing a semiconductor device according to claim 29, wherein in the step of performing the primary cutting, a part of the conductive base material is cut in a thickness direction of the conductive base material.   The method for manufacturing a semiconductor device according to claim 32, wherein the step of preparing the conductive substrate includes a step of removing a part of the conductive substrate from the back surface of the conductive substrate.   32. The method of manufacturing a semiconductor device according to claim 29, wherein, in the step of performing the primary cutting, the entire conductive base material is cut in a thickness direction of the conductive base material. Before the step of forming the sealing resin, a step of attaching an insulating substrate to the back surface of the conductive substrate;
35. The method of manufacturing a semiconductor device according to claim 34, further comprising a step of peeling the insulating base material from the conductive base material between the step of forming the sealing resin and the step of performing the primary cutting. Method.   36. The method according to claim 29, further comprising a step of forming a bonding wire for connecting the semiconductor element and the terminal portion by wire bonding between the step of mounting the semiconductor element and the step of forming the sealing resin. The manufacturing method of the semiconductor device in any one.

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