WO2021020456A1 - Semiconductor package and semiconductor device - Google Patents

Semiconductor package and semiconductor device Download PDF

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Publication number
WO2021020456A1
WO2021020456A1 PCT/JP2020/029099 JP2020029099W WO2021020456A1 WO 2021020456 A1 WO2021020456 A1 WO 2021020456A1 JP 2020029099 W JP2020029099 W JP 2020029099W WO 2021020456 A1 WO2021020456 A1 WO 2021020456A1
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WIPO (PCT)
Prior art keywords
solder
terminal portion
semiconductor package
mold resin
exposed
Prior art date
Application number
PCT/JP2020/029099
Other languages
French (fr)
Japanese (ja)
Inventor
俊浩 中村
耕佑 鈴木
幸一 安川
智史 細野
Original Assignee
株式会社デンソー
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Publication of WO2021020456A1 publication Critical patent/WO2021020456A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present disclosure relates to a semiconductor package in which a semiconductor chip is sealed with a mold resin and a semiconductor device using the same.
  • a semiconductor package in which a semiconductor chip is sealed with a mold resin has been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor package, a semiconductor chip is mounted on the island portion, and a terminal portion electrically connected to the semiconductor chip via a bonding wire or the like is arranged around the island portion. There is. The island portion, the semiconductor chip, and the terminal portion are sealed with a mold resin so that the island portion and a part of the terminal portion are exposed.
  • Such a semiconductor package constitutes a semiconductor device by being mounted on a member to be mounted such as a printed circuit board via solder.
  • An object of the present disclosure is to provide a semiconductor package and a semiconductor device capable of improving the reliability of solder.
  • the semiconductor package has one side and the other side opposite to one side, and the island portion on which the semiconductor chip is arranged on one side and one side, one side opposite to the other side. It has a side surface that connects the other surface and one surface to the other surface, and has a terminal portion that is connected to the semiconductor chip via a connecting member and a side surface that connects one surface, the other surface on the opposite side to the other surface, and one surface and the other surface. Then, the other surface of the island portion is exposed from one surface or the other surface, the other surface of the terminal portion is exposed from the other surface, and a part of the side surface of the terminal portion is exposed from the side surface to seal the semiconductor chip. , Is equipped.
  • the terminal portion is connected to the mounted member via solder, and when at least one of the island portion, the terminal portion, and the mold resin is arranged on the mounted member via solder, the solder A holding structure is formed that holds the thickness of the solder to a predetermined thickness or more.
  • the semiconductor package when the semiconductor package is placed on the mounted member via the solder, it is possible to prevent the solder from becoming thin due to the holding structure. That is, the thickness of the solder can be maintained at a predetermined thickness or more. Therefore, the reliability of the solder can be improved.
  • the semiconductor package has one side and the other side opposite to one side, and the island portion on which the semiconductor chip is arranged on one side and one side and the side opposite to one side.
  • a terminal portion having another surface and being connected to the semiconductor chip via a connecting member, and a mold resin for sealing the semiconductor chip while exposing the other surface of the island portion and the other surface of the terminal portion are provided.
  • At least the terminal portion is connected to the mounted member via solder, and the side of the semiconductor chip opposite to the island portion is composed of a material having a higher thermal conductivity than the mold resin, and the semiconductor chip and heat
  • a heat radiating member that is connected and sealed with a mold resin is arranged.
  • the heat of the semiconductor chip can be dissipated by the heat radiating member, the stress applied to the solder can be reduced when the semiconductor package is arranged on the mounted member via the solder. Therefore, the reliability of the solder can be improved.
  • the semiconductor package has one side and the other side opposite to one side, and the island portion on which the semiconductor chip is arranged on one side and one side and the side opposite to one side. It has a terminal portion that has another surface and is connected to the semiconductor chip via a connecting member, and has one surface and another surface on the opposite side to the one surface, while exposing the other surface of the island portion and the other surface of the terminal portion. It includes a mold resin for encapsulating a semiconductor chip. The other surface of the island portion is exposed from one surface of the mold resin, the other surface of the terminal portion is exposed from the other surface of the mold resin, and the terminal portion is connected to the mounted member via solder. ing.
  • the island portion and the terminal portion are exposed from different surfaces of the mold resin, when the semiconductor package is arranged on the mounted member via solder, for example, the island portion is placed in a metal housing or the like. Can be connected to. Therefore, the heat of the semiconductor chip can be dissipated from the island portion to the housing or the like, and the stress applied to the solder can be reduced. Therefore, the reliability of the solder can be improved.
  • the semiconductor device includes a semiconductor package and a mounted member.
  • the semiconductor package has one side and another side opposite to one side, and has an island portion on which the semiconductor chip is arranged on one side and another side on one side and the other side opposite to one side, and is connected to the semiconductor chip. It is provided with a terminal portion connected via a member, a mold resin that seals a semiconductor chip while exposing the other surface of the island portion and the other surface of the terminal portion, and the mounted portion is soldered to the terminal portion. It has a land connected via. An electronic component that is electrically connected to the terminal portion and the land is arranged between the terminal portion and the land.
  • the distance between the semiconductor package and the mounted member is at least the thickness of the electronic component or more. Therefore, it is possible to prevent the solder arranged between the semiconductor package and the mounted member from becoming thin, and it is possible to improve the reliability of the solder.
  • the semiconductor device includes a semiconductor package and a mounted member.
  • the semiconductor package has a semiconductor chip and another surface on one side and the other side opposite to one side, and connects an island portion on which the semiconductor chip is arranged on one side with one side, another side on the opposite side, and one side and another side. It has a side surface and has a terminal portion connected to the semiconductor chip via a connecting member, and a side surface connecting one surface, another surface on the opposite side to one surface, and one surface and the other surface, and the island portion from one surface or the other surface.
  • the mounted member includes a mold resin that exposes the other surface, exposes the other surface of the terminal portion from the other surface, exposes a part of the side surface of the terminal portion from the side surface, and seals the semiconductor chip. It has a land that is connected to the part via solder. Then, assuming that the portion of the side surface of the terminal portion exposed from the mold resin is the exposed side surface, the land has a slit formed in a portion different from the portion overlapping the exposed side surface in the stacking direction of the semiconductor package and the mounted member. There is.
  • the slit is formed in the portion of the land that overlaps with the exposed side surface, it is possible to suppress the formation of voids in the portion of the solder that overlaps with the exposed side surface. Therefore, when cracks are introduced into the solder, it is possible to prevent the growth of the cracks from being promoted, and it is possible to prevent the life of the solder from being shortened. Therefore, the reliability of the solder can be improved.
  • FIG. 5 is a plan view of the semiconductor package shown in FIG. 1 as viewed from the other surface side of the island portion. It is sectional drawing of the semiconductor device in 1st Embodiment. It is sectional drawing of the semiconductor package in 2nd Embodiment. It is sectional drawing of the semiconductor device in 2nd Embodiment. It is sectional drawing of the semiconductor device in the modification of 2nd Embodiment. It is sectional drawing of the semiconductor device in the modification of 2nd Embodiment. It is sectional drawing of the semiconductor package in 3rd Embodiment. 8 is an enlarged plan view of the semiconductor package shown in FIG. 8 as viewed from the other side of the island portion.
  • the semiconductor device of the first embodiment will be described with reference to the drawings.
  • the semiconductor device of this embodiment is preferably applied as a semiconductor device for driving and controlling parts mounted on a vehicle such as an automobile, for example.
  • the semiconductor device of the present embodiment has a configuration in which the semiconductor package 10 is mounted on the printed circuit board 100 as the mounted member via the solder 200.
  • the semiconductor package 10 is configured to include a lead frame 20 having an island portion 21 and a terminal portion 22, a semiconductor chip 30, a bonding wire 50, a mold resin 60, and the like.
  • the lead frame 20 has an island portion 21 and a plurality of terminal portions 22 separated from each other.
  • the island portion 21 and the terminal portion 22 are formed by, for example, pressing and punching a single metal plate made of a metal material such as copper.
  • the island portion 21 and the terminal portion 22 are integrated with a tie bar or the like before being sealed with the mold resin 60 described later, and are separated by being cut after being sealed with the mold resin 60.
  • the island portion 21 has a quadrangular plate shape having one side 211, another side 212 opposite to one side 211, and side surface 213 connecting one side 211 and the other side 212.
  • Each terminal portion 22 has a side surface 221 and a side surface 222 connecting the other surface 222 on the opposite side to the one surface 221 and a side surface 223 connecting the one surface 221 and the other surface 222, and has a quadrangular plate shape having a smaller flat area than the island portion 21.
  • a plurality of terminal portions 22 are arranged around the island portion 21 around the island portion 21.
  • the semiconductor chip 30 has one side 30a and another side 30b, and is configured to have a semiconductor element formed by a general semiconductor manufacturing process.
  • the semiconductor chip 30 is configured to have semiconductor elements such as MOSFET (abbreviation of Metal Oxide Semiconductor Field Effect Transistor) and IGBT (abbreviation of Insulated Gate Bipolar Transistor).
  • MOSFET abbreviation of Metal Oxide Semiconductor Field Effect Transistor
  • IGBT abbreviation of Insulated Gate Bipolar Transistor
  • the semiconductor chip 30 has an electrode pad (not shown) formed on one side 30a side. Then, in the semiconductor chip 30, the electrode pad is electrically connected to one side 221 of the terminal portion 22 via the bonding wire 50.
  • the bonding wire 50 is made of aluminum, gold, copper, or the like.
  • the mold resin 60 is made of, for example, an epoxy resin or the like. Then, the mold resin 60 exposes a part of the other surface 212 of the island portion 21, the other surface 222 of the terminal portion 22, and the side surface 223, while exposing the semiconductor chip 30, one surface 211 of the island portion 21, and one surface 211 of the terminal portion 22. , The semiconductor chip 30 and the like are arranged so as to be sealed.
  • the mold resin 60 is formed by compression molding or transfer molding using a mold, and in the present embodiment, the one side 61, the other side 62 opposite to the one side 61, the one side 61 and the other side 62. It has a substantially rectangular parallelepiped shape having side surfaces 63 connecting the two.
  • the mold resin 60 is arranged so that the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 are exposed from the other surface 62, and a part of the side surface 223 of the terminal portion 22 is exposed from the side surface 63.
  • the semiconductor package 10 of this embodiment is a so-called QFN (abbreviation of Quad For Non-Lead Package).
  • QFN abbreviation of Quad For Non-Lead Package
  • the side surface of the side surface 223 of the terminal portion 22 exposed from the mold resin 60 is also simply referred to as an exposed side surface 223a.
  • the other surface 62 of the mold resin 60, the other surface 212 of the island portion 21, and the other surface 222 of the terminal portion 22 are arranged so as to be located on the same plane. Further, the side surface 63 and the exposed side surface 223a of the mold resin 60 are arranged so as to be located on the same plane.
  • the mold resin 60 is formed with a convex portion 62a on the other surface 62 side.
  • a plurality of convex portions 62a are formed on the other surface 62 of the mold resin 60 at a portion located between the island portion 21 and the terminal portion 22. More specifically, the convex portion 62a is formed so as to surround the island portion 21 in the stacking direction of the island portion 21 and the semiconductor chip 30 (hereinafter, simply referred to as the stacking direction).
  • the convex portion 62a corresponds to the holding structure. Further, such a convex portion 62a is formed, for example, by preparing a mold on which the convex portion 62a is formed when molding the mold resin 60. In other words, the stacking direction can be said to be when viewed from the stacking direction of the island portion 21 and the semiconductor chip 30.
  • the printed circuit board 100 has a first land 111 and a second land 112 made of copper, aluminum, or the like formed on one side 101 side.
  • the first land 111 has a shape corresponding to the island portion 21 of the semiconductor package 10
  • the second land 112 has a shape corresponding to the terminal portion 22 of the semiconductor package 10.
  • a covering member such as a solder resist (not shown) is also formed on one surface 101 of the printed circuit board 100 so that the first land 111 and the second land 112 are exposed.
  • one side 101 of the printed circuit board 100 is connected so that the island portion 21 is connected to the first land 111 via the solder 200 and the terminal portion 22 is connected to the second land 112 via the solder 200. It is placed on top.
  • the convex portion 62a is formed on the mold resin 60, the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 and the first and second lands 111 and 112 The interval is secured. Therefore, it is possible to prevent the thickness of the solder 200 from becoming thin, and it is possible to prevent the solder 200 from being broken.
  • An underfill material (not shown) is arranged between the semiconductor package 10 and the printed circuit board 100. Further, as the solder 200, for example, tin silver copper solder or the like is used.
  • the semiconductor package 10 and the printed circuit board 100 are prepared.
  • the semiconductor package 10 is prepared as follows. First, the semiconductor chip 30 is arranged on the island portion 21 via the bonding member 40, and then the semiconductor chip 30 and the terminal portion 22 are electrically connected via the bonding wire 50. After that, the mold resin 60 is molded so that the other surface 212 of the island portion 21, the other surface 222 of the terminal portion 22, and the exposed side surface 223a are exposed.
  • the solder paste is placed on the first land 111 and the second land 112 of the printed circuit board 100 by a printing method or the like.
  • the semiconductor package 10 is arranged on the solder paste so that the island portion 21 and the terminal portion 22 come into contact with the solder paste. After that, by performing reflow, the island portion 21 and the first land 111 are connected via the solder 200, and the terminal portion 22 and the second land 112 are connected via the solder 200. As a result, the semiconductor package 10 is connected to the printed circuit board 100 to manufacture the semiconductor device.
  • the convex portion 62a is formed on the other surface 62 of the mold resin 60, the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22, and the first and first surfaces.
  • the distance between the two lands 111 and 112 is secured. Therefore, it is possible to prevent the thickness of the solder 200 from becoming thin, and the solder 200 can be held at a predetermined thickness or more. Therefore, it is possible to suppress the destruction of the solder 200 and improve the reliability of the solder 200.
  • the convex portion 62a is formed so as to surround the island portion 21 in the stacking direction. Therefore, it is possible to prevent the semiconductor package 10 from tilting with respect to one surface 101 of the printed circuit board 100.
  • convex portion 62a may be formed between the island portion 21 and the terminal portion 22 on the other surface 62 of the mold resin 60.
  • the convex portion 62a may be frame-shaped so as to surround the island portion 21 on the other surface 62 of the mold resin 60. Further, the convex portion 62a may be formed between the adjacent terminal portions 22 on the other surface 62 of the island portion 21.
  • a protrusion 222a protruding from the other surface 62 of the mold resin 60 is formed on the other surface 222 of the terminal portion 22.
  • the protrusion 222a corresponds to the holding structure.
  • Such a protrusion 222a is formed, for example, as follows. That is, first, the mold resin 60 is molded so that the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 are exposed. After that, the other surface 212 of the island portion 21, the portion of the other surface 222 of the terminal portion 22 different from the portion to be the protrusion 222a, and the other surface 62 of the mold resin 60 are totally removed by etching or the like. As a result, the semiconductor package 10 in which the protrusion 222a protruding from the other surface 62 of the mold resin 60 is formed is formed.
  • the island portion 21 is connected to the first land 111 via the solder 200
  • the terminal portion 22 is connected to the second land 112 via the solder 200.
  • the protrusion 222a is formed on the terminal portion 22, the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 and the first and second lands 111 and 112 The interval is secured. Therefore, it is possible to prevent the solder 200 from becoming thin.
  • the protrusion 222a is formed on the terminal portion 22, the other surface 212 of the island portion 21, the other surface 222 of the terminal portion 22, and the first and second lands 111, The distance from 112 is secured. Therefore, it is possible to prevent the thickness of the solder 200 from becoming thin, and it is possible to improve the reliability of the solder 200.
  • the protrusion 222a may be formed on the island portion 21 in addition to the terminal portion 22, or may be formed only on the island portion 21.
  • the protrusion 222a may be formed by wire bonding to the other surface 222 of the terminal 22.
  • the protrusion 112a may be formed by wire bonding also on the second land 112.
  • the inhibitory film is arranged on the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 with respect to the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
  • the semiconductor package 10 of the present embodiment has a terminal portion 22 that is more solder wettable than the terminal portion 22 at the boundary portion between the other surface 222 and the exposed side surface 223a.
  • An inhibitory membrane 70 made of a low material is arranged.
  • the inhibitory membrane 70 is made of, for example, a solder resist or the like. Further, in the present embodiment, the inhibitory membrane 70 corresponds to the holding structure. Then, in FIG. 9, the solder ball 201, which will be described later, is omitted.
  • the inhibitory film 70 is arranged so as to surround the outer edge portion on the other surface 222 of the terminal portion 22. Further, the inhibitory film 70 is arranged on the other surface 222 of the terminal portion 22 so that two regions exposed from the inhibitory film 70 are partitioned. Specifically, the inhibitory film 70 is arranged so as to cover the outer edge portion and the substantially central portion of the other surface 222 of the terminal portion 22.
  • the inhibitory film 70 is arranged on the other surface 212 of the island portion 21 so that a plurality of regions exposed from the inhibitory film 70 are partitioned.
  • the solder balls 201 are arranged on the portion of the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 that is exposed from the inhibitory film 70. That is, the semiconductor package 10 of this embodiment is a so-called BGA (abbreviation of Ball Grid Array).
  • the inhibitory film 70 provided on the other surface 222 of the terminal portion 22 is arranged so that two regions are exposed from the inhibitory film 70. Therefore, two solder balls 201 are arranged on the terminal portion 22.
  • the printed circuit board 100 has an inhibitory film 120 formed at a position facing the inhibitory film 70 formed on the island portion 21 and the terminal portion 22.
  • the inhibitory film 120 is formed at a position facing the inhibitory film 70 formed on the other surface 212 of the island portion 21.
  • the inhibitory film 120 is formed at a position facing the inhibitory film 70 formed on the other surface 222 of the terminal portion 22.
  • the inhibitor film 120 is made of a solder resist or the like having a lower solder wettability than the first and second lands 111 and 112, similarly to the inhibitor film 70.
  • one side 101 of the printed circuit board 100 is connected so that the island portion 21 is connected to the first land 111 via the solder 200 and the terminal portion 22 is connected to the second land 112 via the solder 200. It is placed on top.
  • the terminal portion 22 and the second land 112 are connected via two solders 200. Further, the island portion 21 and the first land 111 are connected via a plurality of solders 200.
  • the inhibitory film 70 is arranged at the boundary portion of the other surface 222 of the terminal portion 22 with the exposed side surface 223a, it is possible to prevent the solder 200 from creeping up to the exposed side surface 223a of the terminal portion 22. Therefore, it is possible to prevent the solder 200 from becoming thin.
  • the inhibitory film 70 is arranged at the boundary portion between the other surface 222 of the terminal portion 22 and the exposed side surface 223a. Therefore, it is possible to prevent the solder 200 from creeping up to the exposed side surface 223a of the terminal portion 22. Therefore, it is possible to prevent the thickness of the solder 200 from becoming thin, and it is possible to improve the reliability.
  • the solder balls 201 are arranged in the semiconductor package 10. Therefore, in the semiconductor device, the solder 200 is composed of the solder balls 201 of the semiconductor package 10 and the solder pastes arranged on the first and second lands 111 and 112 when the semiconductor package 10 is arranged on the printed circuit board 100. Will be done. As a result, in the semiconductor device of the present embodiment, when the solder 200 arranged between the island portion 21 and the first land 111 and between the terminal portion 22 and the second land 112 is composed of only solder paste. The solder 200 can be made thicker than the above. Therefore, the reliability can be further improved.
  • the semiconductor package 10 two regions are formed in the terminal portion 22 by the inhibitory film 70, and the solder balls 201 are arranged in each region. Further, on the second land 112 of the printed circuit board 100, the inhibitory film 120 is formed at a position facing the inhibitory film 70 formed on the other surface 222 of the terminal portion 22. The terminal portion 22 and the second land 112 in the semiconductor package 10 are connected via two solders 200. Therefore, even if one of the solders 200 is destroyed, the other solders 200 can secure an electrical connection and improve the durability.
  • the island portion 21 and the first land 111 are connected via a plurality of solders 200. Therefore, even if a part of the solder 200 is broken between the island portion 21 and the first land 111, the remaining solder 200 can secure the connection, and the durability can be improved.
  • the inhibitory film 70 may be arranged only at the boundary portion between the other surface 222 and the exposed side surface 223a. Further, the inhibitory film 70 may be formed on the other surface 222 of the terminal portion 22 so as to expose only one region, or may be formed so as to expose three or more regions.
  • the semiconductor package 10 may be configured not to include the solder balls 201. Even with such a configuration, since the inhibitory film 70 is arranged on the terminal portion 22, it is possible to prevent the solder 200 from climbing up to the exposed side surface 223a, so that it is possible to prevent the solder 200 from becoming thin. ..
  • inhibitory film 70 may be formed only on a part of the plurality of terminal portions 22.
  • a plating film 80 is formed on the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22.
  • the plating film 80 is partially formed on the other surface 212 of the island portion 21, and the inhibitory film 81 is formed at a portion different from the portion where the plating film 80 is formed.
  • a plating film 80 is formed on the entire surface of the other surface 222 of the terminal portion 22.
  • the plating film 80 is formed by laminating nickel (Ni), palladium (Pd), and gold (Au) from the other surface 212 and 222 sides, for example.
  • the inhibitory film 81 is made of a material having a lower solder wettability than the plating film 80, and is made of an oxide film. Such an inhibitory film 81 is formed, for example, by forming a plating film 80 on a predetermined portion of the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22, and then performing thermal oxidation or the like. Further, in the present embodiment, the plating film 80 and the inhibitory film 81 correspond to the holding structure.
  • the printed circuit board 100 has an inhibitory film 120 formed on the first land 111.
  • the inhibitory film 120 is formed so as to expose a portion of the first land 111 facing the plating film 80. That is, the inhibitory membrane 120 is formed so as to face the inhibitory membrane 81.
  • one side 101 of the printed circuit board 100 is connected so that the island portion 21 is connected to the first land 111 via the solder 200 and the terminal portion 22 is connected to the second land 112 via the solder 200. It is placed on top.
  • the solder 200 is unlikely to get wet and spread on the portion where the plating film 80 is not formed, so that it is possible to prevent the solder 200 from becoming thin.
  • the other surface 212 of the island portion 21 is formed with a plating film 80 having a high solder wettability and an inhibitory film 81 having a low solder wettability. Therefore, the solder 200 located between the island portion 21 and the first land 111 is less likely to get wet and spread in the portion where the plating film 80 is not formed. Therefore, it is possible to suppress the thinning of the solder 200 in this portion, and it is possible to suppress the thinning of the solder 200 as a whole. As a result, the reliability of the solder 200 can be improved.
  • the inhibitor film 120 is formed on the first land 111 on the printed circuit board 100, the same effect as that of the third embodiment can be obtained.
  • the other surface 222 of the terminal portion 22 may be formed with the plating film 80 and the inhibition film 81.
  • the plating film 80 may be formed on the entire surface of the other surface 212 of the island portion 21.
  • the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 are in a state of protruding from the other surface 62 of the mold resin 60. That is, the other surface 62 of the mold resin 60 is recessed from the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22.
  • the transfer solder 202 is arranged on the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22.
  • the transfer solder 202 is formed by a transfer method in which the solder is transferred by immersing the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 in a processing tank in which the molten solder is arranged. Further, in the present embodiment, the transfer solder 202 corresponds to the holding structure.
  • the solder 200 is composed of the transfer solder 202 of the semiconductor package 10 and the solder pastes arranged on the first and second lands 111 and 112 when the semiconductor package 10 is arranged on the printed circuit board 100. It is composed. Therefore, in the semiconductor device of the present embodiment, when the solder 200 arranged between the island portion 21 and the first land 111 and between the terminal portion 22 and the second land 112 is composed of only solder paste.
  • the solder 200 can be made thicker than the above.
  • a lead frame 20 having an island portion 21 and a terminal portion 22 and in which the island portion 21 and the terminal portion 22 are connected is prepared. Then, half-etching is performed on the portion located between the island portion 21 and the terminal portion 22 to form the recess 23.
  • the semiconductor chip 30 is arranged on one surface 211 of the island portion 21 via the bonding member 40, and the semiconductor chip 30 and the terminal portion 22 are electrically connected via the bonding wire 50.
  • the mold resin 60 is molded so as to seal the semiconductor chip 30 or the like by compression molding, transfer molding, or the like.
  • etching is performed from the other surface 212 side of the island portion 21 and the other surface 222 side of the terminal portion 22 to penetrate the recess 23.
  • the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 are in a state of protruding from the other surface 62 of the mold resin 60.
  • the semiconductor package 10 of the present embodiment is manufactured by arranging the transfer solder 202 on the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22.
  • the transfer solder 202 is arranged on the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 in the semiconductor package 10. Then, in the semiconductor device, the solder 200 is composed of the transfer solder 202 of the semiconductor package 10 and the solder pastes arranged on the first and second lands 111 and 112 when the semiconductor package 10 is arranged on the printed circuit board 100. Ru. Therefore, in the semiconductor device, as compared with the case where the solder 200 arranged between the island portion 21 and the first land 111 and between the terminal portion 22 and the second land 112 is composed of only the solder paste. , The solder 200 can be thickened. Therefore, the reliability can be further improved.
  • an intermediate lead frame 24 is arranged on the lead frame 20 via the high temperature solder 203.
  • the intermediate lead frame 24 has an intermediate island portion 25 and an intermediate terminal portion 26 separated from each other.
  • the intermediate lead frame 24 is formed by, for example, pressing and punching a single metal plate made of a metal material such as copper, like the lead frame 20.
  • the intermediate island portion 25 has a shape corresponding to the island portion 21, and the intermediate terminal portion 26 has a shape corresponding to the terminal portion 22.
  • the intermediate island portion 25 is arranged on the other surface 212 of the island portion 21 via the high temperature solder 203.
  • the intermediate terminal portion 26 is arranged on the other surface 222 of the terminal portion 22 via the high temperature solder 203.
  • the high temperature solder 203 is made of a material having a melting point higher than that of the solder 200 arranged between the semiconductor package 10 and the printed circuit board 100. More specifically, the high temperature solder 203 is composed of solder having a melting point at a temperature at which it does not melt when the solder 200 is reflowed, and for example, tin lead solder or antimony solder having a melting point at about 260 ° C. is used. Further, in the present embodiment, the intermediate island portion 25 and the intermediate terminal portion 26 correspond to the intermediate members, and the intermediate island portion 25, the intermediate terminal portion 26, and the high temperature solder 203 correspond to the holding structure.
  • the intermediate island portion 25 is connected to the first land 111 via the solder 200, and the intermediate terminal portion 26 is connected to the second land 112 via the solder 200. As such, it is arranged on one side 101 of the printed circuit board 100.
  • the total amount of solder arranged between the semiconductor package 10 and the printed circuit board 100 is large (that is, the thickness is thick), and the thickness of the solder can be increased.
  • the high temperature solder 203 is arranged on the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 in the semiconductor package 10. Therefore, the total amount of solder arranged between the semiconductor package 10 and the printed circuit board 100 is increased, and the reliability of the solder can be improved.
  • the high temperature solder 203 also functions as a stress relaxation unit, it is possible to suppress the application of stress due to the difference in thermal expansion coefficient between the semiconductor package 10 and the printed circuit board 100 to the solder 200. Therefore, the reliability of the solder 200 can be further improved.
  • the high temperature solder 203 may be provided on one of the island portion 21 and the terminal portion 22.
  • the intermediate island portion 25 may be arranged only on the island portion 21 via the high temperature solder 203, and the terminal portion 22 may be connected to the second land 112 via the solder 200.
  • the terminal portion 22 has a recessed portion 222b formed on the other surface 222.
  • the recessed portion 222b is formed, for example, by molding the mold resin 60 and then etching the other surface 222 of the terminal portion 22. Further, in the present embodiment, the recessed portion 222b corresponds to the holding structure.
  • the semiconductor package 10 is arranged on one surface 101 of the printed circuit board 100 with the solder 200 in the recessed portion 222b of the terminal portion 22.
  • the recessed portion 222b is formed on the other surface 222 of the terminal portion 22. Then, in the semiconductor device, the solder 200 is in a state of entering the recessed portion 222b. Therefore, the solder 200 arranged between the semiconductor package 10 and the printed circuit board 100 becomes thicker by the amount of the solder 200 entering the recessed portion 222b. Therefore, the reliability of the solder 200 can be improved.
  • the recessed portion 222b may be formed in the island portion 21 as well, or may be formed only in the island portion 21.
  • the terminal portion 22 is made thinner than the island portion 21 by being made thinner from the other surface 222 side. That is, the terminal portion 22 has the other surface 222 recessed from the other surface 212 of the island portion 21. That is, in the present embodiment, the other surface 222 of the terminal portion 22 is located closer to one surface 61 of the mold resin 60 than the other surface 62 of the mold resin 60 and the other surface 212 of the island portion 21. In the present embodiment, the structure in which the other surface 222 of the terminal portion 22 is located on the one surface 61 side of the mold resin 60 with respect to the other surface 212 of the island portion 21 corresponds to the holding structure.
  • Such a semiconductor package 10 is formed by molding the mold resin 60 and then thinning the terminal portion 22 from the other surface 222 side by etching or the like.
  • the semiconductor package 10 is connected so that the island portion 21 is connected to the first land 111 via the solder 200 and the terminal portion 22 is connected to the second land 112 via the solder 200.
  • the solder 200 between the terminal portion 22 and the second land 112 is thicker than the solder 200 between the island portion 21 and the first land 111. Therefore, the solder 200 between the terminal portion 22 and the second land 112 can be thickened.
  • the other surface 222 of the terminal portion 22 is located on one surface 61 side of the mold resin 60 with respect to the other surface 212 of the island portion 21. Therefore, the solder 200 arranged between the terminal portion 22 and the second land 112 is compared with the case where the terminal portion 22, the other surface 212, and the other surface 212 of the island portion 21 are located on the same plane. Can be thickened. Therefore, the reliability of the solder 200 can be improved.
  • the island portion 21 may be made thinner instead of the terminal portion 22. Further, the island portion 21 and the terminal portion 22 have the same thickness, for example, if the other surface 222 of the terminal portion 22 is located on the one surface 61 side of the mold resin 60 with respect to the other surface 212 of the island portion 21. May be good.
  • the terminal portion 22 is in a state where the other surface 222 and the exposed side surface 223a are separated from each other as compared with the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
  • the terminal portion 22 is formed with a recess 224 for removing the connecting portion between the other surface 222 and the exposed side surface 223a. Then, the mold resin 60 is arranged in the recess 224.
  • the exposed side surface 223a of the terminal portion 22 is exposed from a portion of the side surface 63 of the mold resin 60 that is different from the boundary portion with the other surface 62. That is, the terminal portion 22 is in a state in which the other surface 222 and the exposed side surface 223a are separated.
  • the structure in which the other surface 222 and the exposed side surface 223a are separated corresponds to the holding structure.
  • the island portion 21 is connected to the first land 111 via the solder 200, and the terminal portion 22 is connected to the second land 112 via the solder 200.
  • the other surface 222 and the exposed side surface 223a are separated from each other in the terminal portion 22, it is possible to prevent the solder 200 from creeping up from the other surface 222 to the exposed side surface 223a. Therefore, it is possible to prevent the solder 200 from becoming thin.
  • a recess 224 is formed on the other surface 222 of the terminal portion 22. After that, when the mold resin 60 is molded, the mold resin 60 is also arranged in the recess 224, so that the semiconductor package 10 in which the other surface 222 of the terminal portion 22 and the exposed side surface 223a are separated is manufactured.
  • a lead frame 20 is prepared in a state where the portions constituting the terminal portions 22 of the adjacent semiconductor packages 10 are connected via the dicing line DL. Then, a temporary recess 224a is formed on the other surface 222 side of the terminal portion 22 so as to include a portion serving as a dicing line DL. The width of the opening of the temporary recess 224a is made wider than that of the dicing line DL.
  • the resin is also allowed to enter the temporary recess 224a.
  • the semiconductor package 10 is manufactured by cutting along the dicing line DL. At this time, since the width of the opening of the temporary recess 224a is wider than that of the dicing line DL, when the temporary recess 224a is cut, the other surface 222 and the exposed side surface 223a are separated from each other.
  • the terminal portion 22 is in a state in which the other surface 222 and the exposed side surface 223a are separated. Therefore, it is possible to prevent the solder 200 from creeping up from the other surface 222 to the exposed side surface 223a. Therefore, it is possible to prevent the thickness of the solder 200 from becoming thin, and it is possible to improve the reliability of the solder 200.
  • an inhibitory film 90 is formed on the exposed side surface 223a of the terminal portion 22.
  • the inhibitory film 90 is made of a film having a lower solder wettability than the terminal portion 22, and is formed of, for example, an oxide film.
  • the inhibitory film 90 is formed around the recessed portion 223b by, for example, irradiating the exposed side surface 223a with a laser beam so that the recessed portion 223b is formed.
  • the inhibitory membrane 90 corresponds to the holding structure.
  • the island portion 21 is connected to the first land 111 via the solder 200, and the terminal portion 22 is connected to the second land 112 via the solder 200.
  • the inhibitory film 90 is formed on the exposed side surface 223a of the terminal portion 22, it is possible to prevent the solder 200 from creeping up from the other surface 222 to the exposed side surface 223a. Therefore, it is possible to prevent the solder 200 from becoming thin.
  • the inhibitory film 90 is formed on the exposed side surface 223a of the terminal portion 22. Therefore, it is possible to prevent the solder 200 from creeping up from the other surface 222 to the exposed side surface 223a. Therefore, it is possible to prevent the thickness of the solder 200 from becoming thin, and it is possible to improve the reliability of the solder 200.
  • the eleventh embodiment will be described.
  • the heat radiating member is arranged on the semiconductor chip 30 as compared with the first embodiment.
  • Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
  • a heat radiating member 31 thermally connected to the semiconductor chip 30 is arranged on one side 30a side of the semiconductor chip 30.
  • the heat radiating member 31 is sealed with the mold resin 60 together with the semiconductor chip 30 and the like.
  • the heat radiating member 31 is made of a material having a higher thermal conductivity than the mold resin 60, and is made of, for example, copper.
  • the lead frame 20 is arranged in one region and the heat radiating member 31 is mainly in the other region with respect to the virtual line K that passes through the center in the thickness direction and is along the plane direction of the island portion 21. It is designed to be placed in.
  • the fact that the heat radiating member 31 is mainly arranged in the other region means that 50% or more of the total product of the heat radiating member 31 is located in the other region.
  • the heat radiating member 31 is arranged so as to be connected to the semiconductor chip 30 and also to the terminal portion 22.
  • the heat radiating member 31 is made of the same material as the lead frame 20 and is made of copper.
  • the island portion 21 is connected to the first land 111 via the solder 200, and the terminal portion 22 is connected to the second land 112 via the solder 200. Is arranged on one side 101 of the printed circuit board 100.
  • the heat radiating member 31 is arranged on the one side 30a side of the semiconductor chip 30. Therefore, heat is easily dissipated from the semiconductor chip 30 via the heat radiating member 31, and the stress applied to the solder 200 can be reduced. Therefore, it is possible to suppress the destruction of the solder 200 and improve the reliability of the solder 200.
  • the heat radiating member 31 is made of the same material as the lead frame 20. Then, in the semiconductor package 10, the lead frame 20 is arranged in one region and the heat radiating member 31 is mainly arranged in the other region with respect to the virtual line K. Therefore, it is possible to suppress the warping of the semiconductor package 10 due to heat, and further reduce the stress applied to the solder 200.
  • the heat radiating member 31 is connected to the terminal portion 22. Therefore, the heat radiating member 31 can also function as a connecting member.
  • the heat radiating member 31 does not have to be electrically connected to the terminal portion 22. That is, the semiconductor chip 30 and the terminal portion 22 may be connected by the bonding wire 50. Further, when connecting the semiconductor chip 30 and the plurality of terminal portions 22, a part of the connection may be made by the heat radiating member 31, and the remaining connection may be made by the bonding wire 50.
  • the terminal portion 22 is arranged so that the other surface 222 is exposed from the other surface 62 of the mold resin 60.
  • the island portion 21 is arranged so that the other surface 212 is exposed from one surface 61 of the mold resin 60. That is, the island portion 21 and the terminal portion 22 are arranged so as to be exposed from different surfaces of the mold resin 60.
  • the terminal portion 22 is provided with an extension portion 221a extending toward the semiconductor chip 30 on one side 221.
  • the semiconductor chip 30 is connected to the extension portion 221a via the bonding wire 50.
  • the semiconductor package 10 is arranged on one side 101 of the printed circuit board 100 so that the terminal portion 22 is connected to the second land 112 via the solder 200. Further, in the semiconductor package 10, the housing 300 and the island portion 21 are connected via the solder 200.
  • the housing 300 is made of, for example, metal or the like.
  • the island portion 21 and the terminal portion 22 are exposed from different surfaces of the mold resin 60. That is, the island portion 21 and the terminal portion 22 can be connected to different members.
  • the semiconductor package 10 is such that the island portion 21 is connected to the housing 300 and the terminal portion 22 is connected to the printed circuit board 100. Therefore, since heat can be dissipated from the island portion 21 to the housing 300, the stress applied to the solder 200 from the semiconductor package 10 can be reduced. Therefore, it is possible to suppress the destruction of the solder 200 and improve the reliability of the solder 200.
  • the semiconductor chip 30 is flip-chip mounted on the terminal portion 22 with respect to the twelfth embodiment. Others are the same as those in the twelfth embodiment, and thus the description thereof will be omitted here.
  • a plurality of terminal portions 22 are arranged side by side on the other surface 62 side of the mold resin 60.
  • the other surface 222 of the terminal portion 22 is exposed from the other surface 62 of the mold resin 60.
  • the semiconductor chip 30 is connected to the terminal portion 22 on the one side 30a side via the solder 32. That is, the semiconductor chip 30 is flip-chip mounted on the terminal portion 22.
  • the island portion 21 is arranged so that the other surface 212 is exposed from one surface 61 of the mold resin 60.
  • the island portion 21 is joined to the other surface 30b of the semiconductor chip 30 via the joining member 40.
  • the semiconductor package 10 is arranged on one side 101 of the printed circuit board 100 so that the terminal portion 22 is connected to the second land 112 via the solder 200. Further, in the semiconductor package 10, the housing 300 and the island portion 21 are connected via the solder 200.
  • a modified example of the thirteenth embodiment will be described.
  • another conductive member such as a lead frame is laminated on a part of the terminal portions 22 among the plurality of terminal portions 22, and the conductive member is exposed from one surface 61 of the mold resin 60. You may try to do it. Then, the conductive member exposed from one side 61 of the mold resin 60 is electrically connected to the electronic component arranged on the one side 61 side of the mold resin 60, and the terminal is electrically connected to the conductive member.
  • the portion 22 may not be connected to the printed circuit board 100 via the solder 200. That is, a part of the terminal portions 22 may function as wiring for connecting the electronic components arranged on the one side 61 side of the mold resin 60 and the semiconductor chip 30. According to this, the degree of freedom of wiring can be improved.
  • an electronic component 400 is arranged between the semiconductor package 10 and the printed circuit board 100.
  • 33 is a cross-sectional view taken along the line XXXII-XXXII in FIG.
  • the electronic component 400 is a chip capacitor having a pair of electrodes 401. Then, in the electronic component 400, one surface of the printed circuit board 100 is connected via the solder 200 so that one electrode 401 is connected to one of the adjacent terminal portions 22 and the second land 112 facing the terminal portion 22. It is arranged on 101. Further, in the electronic component 400, one surface of the printed circuit board 100 is connected via the solder 200 so that the other electrode 401 is connected to the other of the adjacent terminal portions 22 and the second land 112 facing the terminal portion 22. It is arranged on 101.
  • the electronic component 400 is arranged between the semiconductor package 10 and the printed circuit board 100. That is, the electronic component 400 as a spacer is arranged between the semiconductor package 10 and the printed circuit board 100. Therefore, it is possible to prevent the thickness of the solder 200 arranged between the semiconductor package 10 and the printed circuit board 100 from becoming thinner than the thickness of the electronic component 400, and it is possible to improve the reliability of the solder 200.
  • the space of the portion of the printed circuit board 100 different from the portion on which the semiconductor package 10 is mounted can be effectively utilized or the space can be reduced. Can be planned.
  • a slit 112b is formed in the second land 112. Specifically, the slit 112b is formed in a portion different from the portion overlapping the exposed side surface 223a in the stacking direction. In the present embodiment, the slit 112b is formed in a portion facing the other surface 222 of the terminal portion 22, and is formed so as to separate the second land 112 into two regions.
  • FIG. 35 is a plan view of the second land 112 located on the left side of the paper surface in FIG. 34. Further, in FIG. 35, a portion of the second land 112 that overlaps the exposed side surface 223a in the stacking direction is shown by a dotted line.
  • one side 101 of the printed circuit board 100 is connected so that the island portion 21 is connected to the first land 111 via the solder 200 and the terminal portion 22 is connected to the second land 112 via the solder 200. It is placed on top.
  • the slit 112b is formed in the second land 112, a void 130 including the slit 112b is formed between the printed circuit board 100 and the solder 200.
  • the slit 112b is formed in the second land 112
  • the second land 112 is formed with a slit 112b in a portion different from the portion overlapping the exposed side surface 223a in the stacking direction.
  • a void 130 is formed between the solder 200 and the printed circuit board 100 in a portion different from the portion overlapping the exposed side surface 223a in the stacking direction. That is, by forming the slit 112b, the void 130 including the slit 112b is intentionally formed in a portion different from the portion overlapping the exposed side surface 223a in the stacking direction. Therefore, it is possible to prevent the void 130 from being formed in the portion of the solder 200 that overlaps the crack growing direction. As a result, it is possible to prevent the life of the solder 200 from being shortened, and it is possible to improve the reliability of the solder 200.
  • the shape of the slit 112b can be changed as appropriate.
  • the slit 112b may be formed so as not to divide the second land 112.
  • FIG. 36 is a plan view of the second land 112 located on the left side of the paper surface in FIG. 34.
  • the slit 112b may not be formed in a portion facing the other surface 222 of the terminal portion 22 as long as it is formed in a portion different from the portion overlapping the exposed side surface 223a in the stacking direction.
  • the mounted member may be a ceramic wiring board or the like instead of the printed circuit board 100.
  • each of the above embodiments can be combined as appropriate.
  • the second embodiment may be combined with each embodiment as appropriate to form a protrusion 222a on the terminal portion 22.
  • the inhibitory film 70 may be formed on the terminal portion 22 by appropriately combining the third embodiment with each embodiment.
  • the fourth embodiment may be appropriately combined with each embodiment to form a plating film 80 and an inhibitory film 81 on the island portion 21 and the terminal portion 22.
  • the fifth embodiment may be appropriately combined with each embodiment, and the transfer solder 202 may be arranged on the island portion 21 and the terminal portion 22.
  • the sixth embodiment may be appropriately combined with each embodiment, and the intermediate lead frame 24 may be arranged on the island portion 21 and the terminal portion 22 via the high temperature solder 203.
  • the seventh embodiment may be appropriately combined with each embodiment to form a recessed portion 222b in the terminal portion 22.
  • the eighth embodiment may be combined with each embodiment as appropriate to make the terminal portion 22 thinner.
  • the ninth embodiment may be appropriately combined with each embodiment so that the other surface 222 of the terminal portion 22 and the exposed side surface 223a are separated from each other.
  • the tenth embodiment may be appropriately combined with each embodiment to form an inhibitory film 90 on the exposed side surface 223a of the terminal portion 22.
  • the eleventh embodiment may be combined with each embodiment as appropriate, and the heat radiating member 31 may be arranged.
  • the twelfth embodiment may be appropriately combined with each embodiment so that the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 are exposed from different surfaces of the mold resin 60.
  • the semiconductor chip 30 may be flip-chip mounted on the terminal portion 22 as in the thirteenth embodiment.
  • the 14th embodiment may be appropriately combined with each embodiment, and the electronic component 400 may be arranged between the semiconductor package 10 and the printed circuit board 100.
  • the fifteenth embodiment may be appropriately combined with each embodiment to form a slit 112b in the second land 112.

Abstract

A semiconductor package according to the present invention is provided with: a semiconductor chip (30); an island part (21) on which is disposed the semiconductor chip (30) on one surface (211); a terminal part (22) connected to the semiconductor chip (30) via a connecting member (50); and a molded resin (60) exposing another surface (212) of the island part (21) from one surface (61) or another surface (62), exposing another surface (222) of the terminal part (22) from the other surface (62), exposing a portion of a side surface (223) of the terminal part (22) from a side surface (63), and sealing the semiconductor chip (30). Moreover, a holding structure (62a) is formed at least at one of the island part (21), the terminal part (22), and the molded resin (60), and holds the thickness of a solder (200) to a prescribed thickness or greater when the semiconductor package is disposed on a member (100) to be mounted via the solder (200).

Description

半導体パッケージおよび半導体装置Semiconductor packages and semiconductor devices 関連出願への相互参照Cross-reference to related applications
　本出願は、２０１９年７月３０日に出願された日本特許出願番号２０１９－１３９９２３号に基づくもので、ここにその記載内容が参照により組み入れられる。 This application is based on Japanese Patent Application No. 2019-139923 filed on July 30, 2019, the contents of which are incorporated herein by reference.
　本開示は、半導体チップがモールド樹脂で封止された半導体パッケージおよびそれを用いた半導体装置に関する。 The present disclosure relates to a semiconductor package in which a semiconductor chip is sealed with a mold resin and a semiconductor device using the same.
　従来より、半導体チップがモールド樹脂で封止された半導体パッケージが提案されている（例えば、特許文献１参照）。具体的には、この半導体パッケージでは、アイランド部上に半導体チップが搭載されており、アイランド部の周囲には、半導体チップとボンディングワイヤ等を介して電気的に接続される端子部が配置されている。そして、アイランド部、半導体チップ、端子部は、アイランド部および端子部の一部が露出するように、モールド樹脂で封止されている。
　このような半導体パッケージは、プリント基板等の被実装部材にはんだを介して実装されることで半導体装置を構成する。 Conventionally, a semiconductor package in which a semiconductor chip is sealed with a mold resin has been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor package, a semiconductor chip is mounted on the island portion, and a terminal portion electrically connected to the semiconductor chip via a bonding wire or the like is arranged around the island portion. There is. The island portion, the semiconductor chip, and the terminal portion are sealed with a mold resin so that the island portion and a part of the terminal portion are exposed.
Such a semiconductor package constitutes a semiconductor device by being mounted on a member to be mounted such as a printed circuit board via solder.
特開２００８－１６４６９号公報Japanese Unexamined Patent Publication No. 2008-16469
　ところで、近年では、半導体パッケージと被実装部材との間に配置されるはんだの信頼性を向上させたいという要望がある。 By the way, in recent years, there has been a demand for improving the reliability of solder placed between a semiconductor package and a member to be mounted.
　本開示は、はんだの信頼性の向上を図ることができる半導体パッケージおよび半導体装置を提供することを目的とする。 An object of the present disclosure is to provide a semiconductor package and a semiconductor device capable of improving the reliability of solder.
　本開示の１つの観点によれば、半導体パッケージは、半導体チップと、一面および一面と反対側の他面を有し、一面に半導体チップが配置されるアイランド部と、一面、一面と反対側の他面、一面と他面とを繋ぐ側面を有し、半導体チップと接続部材を介して接続される端子部と、一面、一面と反対側の他面、一面と他面とを繋ぐ側面を有し、一面または他面からアイランド部の他面を露出させ、他面から端子部の他面を露出させると共に側面から端子部の側面の一部を露出させ、半導体チップを封止するモールド樹脂と、を備えている。そして、少なくとも端子部は、はんだを介して被実装部材と接続されており、アイランド部、端子部、およびモールド樹脂の少なくとも１つには、はんだを介して被実装部材に配置された際、はんだの厚さを所定以上の厚さに保持する保持構造が形成されている。 According to one aspect of the present disclosure, the semiconductor package has one side and the other side opposite to one side, and the island portion on which the semiconductor chip is arranged on one side and one side, one side opposite to the other side. It has a side surface that connects the other surface and one surface to the other surface, and has a terminal portion that is connected to the semiconductor chip via a connecting member and a side surface that connects one surface, the other surface on the opposite side to the other surface, and one surface and the other surface. Then, the other surface of the island portion is exposed from one surface or the other surface, the other surface of the terminal portion is exposed from the other surface, and a part of the side surface of the terminal portion is exposed from the side surface to seal the semiconductor chip. , Is equipped. Then, at least the terminal portion is connected to the mounted member via solder, and when at least one of the island portion, the terminal portion, and the mold resin is arranged on the mounted member via solder, the solder A holding structure is formed that holds the thickness of the solder to a predetermined thickness or more.
　これによれば、半導体パッケージを被実装部材にはんだを介して配置した際、保持構造によってはんだが薄くなることを抑制できる。つまり、はんだの厚さを所定以上の厚さに保持できる。このため、はんだの信頼性の向上を図ることができる。 According to this, when the semiconductor package is placed on the mounted member via the solder, it is possible to prevent the solder from becoming thin due to the holding structure. That is, the thickness of the solder can be maintained at a predetermined thickness or more. Therefore, the reliability of the solder can be improved.
　本開示の別の観点によれば、半導体パッケージは、半導体チップと、一面および一面と反対側の他面を有し、一面に半導体チップが配置されるアイランド部と、一面および一面と反対側の他面を有し、半導体チップと接続部材を介して接続される端子部と、アイランド部の他面および端子部の他面を露出させつつ、半導体チップを封止するモールド樹脂と、を備えている。そして、少なくとも端子部は、はんだを介して被実装部材と接続されており、半導体チップのうちのアイランド部と反対側には、モールド樹脂より熱伝導率が高い材料で構成され、半導体チップと熱的に接続されると共にモールド樹脂で封止された放熱部材が配置されている。 According to another aspect of the present disclosure, the semiconductor package has one side and the other side opposite to one side, and the island portion on which the semiconductor chip is arranged on one side and one side and the side opposite to one side. A terminal portion having another surface and being connected to the semiconductor chip via a connecting member, and a mold resin for sealing the semiconductor chip while exposing the other surface of the island portion and the other surface of the terminal portion are provided. There is. At least the terminal portion is connected to the mounted member via solder, and the side of the semiconductor chip opposite to the island portion is composed of a material having a higher thermal conductivity than the mold resin, and the semiconductor chip and heat A heat radiating member that is connected and sealed with a mold resin is arranged.
　これによれば、放熱部材によって半導体チップの熱を放熱できるため、半導体パッケージを被実装部材にはんだを介して配置した際、はんだに印加される応力を低減できる。したがって、はんだの信頼性の向上を図ることができる。 According to this, since the heat of the semiconductor chip can be dissipated by the heat radiating member, the stress applied to the solder can be reduced when the semiconductor package is arranged on the mounted member via the solder. Therefore, the reliability of the solder can be improved.
　本開示の別の観点によれば、半導体パッケージは、半導体チップと、一面および一面と反対側の他面を有し、一面に半導体チップが配置されるアイランド部と、一面および一面と反対側の他面を有し、半導体チップと接続部材を介して接続される端子部と、一面および一面と反対側の他面を有し、アイランド部の他面および端子部の他面を露出させつつ、半導体チップを封止するモールド樹脂と、を備えている。そして、アイランド部の他面は、モールド樹脂の一面から露出しており、端子部の他面は、モールド樹脂の他面から露出しており、端子部がはんだを介して被実装部材と接続されている。 According to another aspect of the present disclosure, the semiconductor package has one side and the other side opposite to one side, and the island portion on which the semiconductor chip is arranged on one side and one side and the side opposite to one side. It has a terminal portion that has another surface and is connected to the semiconductor chip via a connecting member, and has one surface and another surface on the opposite side to the one surface, while exposing the other surface of the island portion and the other surface of the terminal portion. It includes a mold resin for encapsulating a semiconductor chip. The other surface of the island portion is exposed from one surface of the mold resin, the other surface of the terminal portion is exposed from the other surface of the mold resin, and the terminal portion is connected to the mounted member via solder. ing.
　これによれば、アイランド部と端子部とがモールド樹脂の異なる面から露出しているため、半導体パッケージを被実装部材にはんだを介して配置した際、例えば、アイランド部を金属製の筐体等に接続できる。このため、半導体チップの熱をアイランド部から筐体等に放熱でき、はんだに印加される応力を低減できる。したがって、はんだの信頼性の向上を図ることができる。 According to this, since the island portion and the terminal portion are exposed from different surfaces of the mold resin, when the semiconductor package is arranged on the mounted member via solder, for example, the island portion is placed in a metal housing or the like. Can be connected to. Therefore, the heat of the semiconductor chip can be dissipated from the island portion to the housing or the like, and the stress applied to the solder can be reduced. Therefore, the reliability of the solder can be improved.
　本開示の別の観点によれば、半導体装置は、半導体パッケージと被実装部材とを備えている。半導体パッケージは、半導体チップと、一面および一面と反対側の他面を有し、一面に半導体チップが配置されるアイランド部と、一面および一面と反対側の他面を有し、半導体チップと接続部材を介して接続される端子部と、アイランド部の他面および端子部の他面を露出させつつ、半導体チップを封止するモールド樹脂と、を備え、被実装部は、端子部とはんだを介して接続されるランドを備えている。そして、端子部とランドとの間には、端子部およびランドと電気的に接続される電子部品が配置されている。 According to another aspect of the present disclosure, the semiconductor device includes a semiconductor package and a mounted member. The semiconductor package has one side and another side opposite to one side, and has an island portion on which the semiconductor chip is arranged on one side and another side on one side and the other side opposite to one side, and is connected to the semiconductor chip. It is provided with a terminal portion connected via a member, a mold resin that seals a semiconductor chip while exposing the other surface of the island portion and the other surface of the terminal portion, and the mounted portion is soldered to the terminal portion. It has a land connected via. An electronic component that is electrically connected to the terminal portion and the land is arranged between the terminal portion and the land.
　これによれば、半導体パッケージと被実装部材との間隔は、少なくとも電子部品の厚さ以上となる。このため、半導体パッケージと被実装部材との間に配置されるはんだが薄くなることを抑制でき、はんだの信頼性の向上を図ることができる。 According to this, the distance between the semiconductor package and the mounted member is at least the thickness of the electronic component or more. Therefore, it is possible to prevent the solder arranged between the semiconductor package and the mounted member from becoming thin, and it is possible to improve the reliability of the solder.
　本開示の別の観点によれば、半導体装置は、半導体パッケージと被実装部材とを備えている。半導体パッケージは、半導体チップと、一面および一面と反対側の他面を有し、一面に半導体チップが配置されるアイランド部と、一面、一面と反対側の他面、一面と他面とを繋ぐ側面を有し、半導体チップと接続部材を介して接続される端子部と、一面、一面と反対側の他面、一面と他面とを繋ぐ側面を有し、一面または他面からアイランド部の他面を露出させ、他面から端子部の他面を露出させると共に側面から端子部の側面の一部を露出させ、半導体チップを封止するモールド樹脂と、を備え、被実装部材は、端子部とはんだを介して接続されるランドを備えている。そして、端子部の側面のうちのモールド樹脂から露出する部分を露出側面とすると、ランドは、半導体パッケージと被実装部材との積層方向において、露出側面と重なる部分と異なる部分にスリットが形成されている。 According to another aspect of the present disclosure, the semiconductor device includes a semiconductor package and a mounted member. The semiconductor package has a semiconductor chip and another surface on one side and the other side opposite to one side, and connects an island portion on which the semiconductor chip is arranged on one side with one side, another side on the opposite side, and one side and another side. It has a side surface and has a terminal portion connected to the semiconductor chip via a connecting member, and a side surface connecting one surface, another surface on the opposite side to one surface, and one surface and the other surface, and the island portion from one surface or the other surface. The mounted member includes a mold resin that exposes the other surface, exposes the other surface of the terminal portion from the other surface, exposes a part of the side surface of the terminal portion from the side surface, and seals the semiconductor chip. It has a land that is connected to the part via solder. Then, assuming that the portion of the side surface of the terminal portion exposed from the mold resin is the exposed side surface, the land has a slit formed in a portion different from the portion overlapping the exposed side surface in the stacking direction of the semiconductor package and the mounted member. There is.
　これによれば、ランドのうちの露出側面と重なる部分と異なる部分にスリットが形成されているため、はんだのうちの露出側面と重なる部分にボイドが形成されることを抑制できる。このため、はんだにクラックが導入された際に当該クラックの進展が促進されることを抑制でき、はんだの寿命が短くなることを抑制できる。したがって、はんだの信頼性の向上を図ることができる。 According to this, since the slit is formed in the portion of the land that overlaps with the exposed side surface, it is possible to suppress the formation of voids in the portion of the solder that overlaps with the exposed side surface. Therefore, when cracks are introduced into the solder, it is possible to prevent the growth of the cracks from being promoted, and it is possible to prevent the life of the solder from being shortened. Therefore, the reliability of the solder can be improved.
　なお、各構成要素等に付された括弧付きの参照符号は、その構成要素等と後述する実施形態に記載の具体的な構成要素等との対応関係の一例を示すものである。 Note that the reference reference numerals in parentheses attached to each component or the like indicate an example of the correspondence between the component or the like and the specific component or the like described in the embodiment described later.
第１実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in 1st Embodiment. 図１に示す半導体パッケージをアイランド部の他面側から視た平面図である。FIG. 5 is a plan view of the semiconductor package shown in FIG. 1 as viewed from the other surface side of the island portion. 第１実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in 1st Embodiment. 第２実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in 2nd Embodiment. 第２実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in 2nd Embodiment. 第２実施形態の変形例における半導体装置の断面図である。It is sectional drawing of the semiconductor device in the modification of 2nd Embodiment. 第２実施形態の変形例における半導体装置の断面図である。It is sectional drawing of the semiconductor device in the modification of 2nd Embodiment. 第３実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in 3rd Embodiment. 図８に示す半導体パッケージをアイランド部の他面側から視た平面拡大図である。8 is an enlarged plan view of the semiconductor package shown in FIG. 8 as viewed from the other side of the island portion. 第３実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in 3rd Embodiment. 第４実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in 4th Embodiment. 第４実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in 4th Embodiment. 第５実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in 5th Embodiment. 第５実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in 5th Embodiment. 図１３に示す半導体パッケージの製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor package shown in FIG. 図１５Ａに続く半導体パッケージの製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor package following FIG. 15A. 図１５Ｂに続く半導体パッケージの製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor package following FIG. 15B. 第６実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in 6th Embodiment. 第６実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in 6th Embodiment. 第７実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in 7th Embodiment. 第７実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in 7th Embodiment. 第８実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in 8th Embodiment. 第８実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in 8th Embodiment. 第９実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in 9th Embodiment. 第９実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in 9th Embodiment. 図２２に示す半導体パッケージの製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor package shown in FIG. 図２４Ａに続く半導体パッケージの製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor package following FIG. 24A. 第１０実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in tenth embodiment. 第１０実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in tenth embodiment. 第１１実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in 11th Embodiment. 第１１実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in eleventh embodiment. 第１２実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in 12th Embodiment. 第１２実施形態における半導体装置を筐体に接続した状態を示す断面図である。It is sectional drawing which shows the state which connected the semiconductor device in 12th Embodiment to a housing. 第１３実施形態における半導体パッケージの断面図である。It is sectional drawing of the semiconductor package in 13th Embodiment. 第１３実施形態における半導体装置を筐体に接続した状態を示す断面図である。It is sectional drawing which shows the state which connected the semiconductor device in 13th Embodiment to a housing. 第１４実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in 14th Embodiment. 第１５実施形態における半導体装置の断面図である。It is sectional drawing of the semiconductor device in 15th Embodiment. 図３４に示す第２ランドの平面図である。It is a top view of the second land shown in FIG. 34. 第１５実施形態の変形例における第２ランドの平面図である。It is a top view of the 2nd land in the modification of 15th Embodiment.
　以下、本開示の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。 Hereinafter, embodiments of the present disclosure will be described with reference to the figures. In each of the following embodiments, parts that are the same or equal to each other will be described with the same reference numerals.
　（第１実施形態）
　第１実施形態の半導体装置について、図面を参照しつつ説明する。なお、本実施形態の半導体装置は、例えば、自動車等の車両に搭載される部品を駆動制御するための半導体装置として適用されると好適である。 (First Embodiment)
The semiconductor device of the first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is preferably applied as a semiconductor device for driving and controlling parts mounted on a vehicle such as an automobile, for example.
　本実施形態の半導体装置は、図１～図３に示されるように、半導体パッケージ１０が被実装部材としてのプリント基板１００にはんだ２００を介して実装された構成とされている。 As shown in FIGS. 1 to 3, the semiconductor device of the present embodiment has a configuration in which the semiconductor package 10 is mounted on the printed circuit board 100 as the mounted member via the solder 200.
　まず、本実施形態の半導体パッケージ１０の構成について、図１および図２を参照しつつ説明する。半導体パッケージ１０は、アイランド部２１および端子部２２を有するリードフレーム２０、半導体チップ３０、ボンディングワイヤ５０、モールド樹脂６０等を有する構成とされている。 First, the configuration of the semiconductor package 10 of the present embodiment will be described with reference to FIGS. 1 and 2. The semiconductor package 10 is configured to include a lead frame 20 having an island portion 21 and a terminal portion 22, a semiconductor chip 30, a bonding wire 50, a mold resin 60, and the like.
　リードフレーム２０は、互いに分離されたアイランド部２１および複数の端子部２２を有している。アイランド部２１および端子部２２は、例えば、銅等の金属材料を用いて構成される１枚の金属板がプレス打ち抜き等されることによって形成されている。なお、アイランド部２１および端子部２２は、後述するモールド樹脂６０で封止される前はタイバー等によって一体化されており、モールド樹脂６０で封止された後にカットされることで分離される。 The lead frame 20 has an island portion 21 and a plurality of terminal portions 22 separated from each other. The island portion 21 and the terminal portion 22 are formed by, for example, pressing and punching a single metal plate made of a metal material such as copper. The island portion 21 and the terminal portion 22 are integrated with a tie bar or the like before being sealed with the mold resin 60 described later, and are separated by being cut after being sealed with the mold resin 60.
　アイランド部２１は、本実施形態では、一面２１１、一面２１１と反対側の他面２１２、一面２１１と他面２１２とを繋ぐ側面２１３を有する四角形板状とされている。各端子部２２は、一面２２１、一面２２１と反対側の他面２２２、一面２２１と他面２２２とを繋ぐ側面２２３を有し、アイランド部２１より平面積が小さい四角形板状とされている。そして、各端子部２２は、アイランド部２１を中心としてアイランド部２１の周囲に複数配置されている。 In the present embodiment, the island portion 21 has a quadrangular plate shape having one side 211, another side 212 opposite to one side 211, and side surface 213 connecting one side 211 and the other side 212. Each terminal portion 22 has a side surface 221 and a side surface 222 connecting the other surface 222 on the opposite side to the one surface 221 and a side surface 223 connecting the one surface 221 and the other surface 222, and has a quadrangular plate shape having a smaller flat area than the island portion 21. A plurality of terminal portions 22 are arranged around the island portion 21 around the island portion 21.
　半導体チップ３０は、一面３０ａおよび他面３０ｂを有し、一般的な半導体製造プロセスによって形成された半導体素子を有する構成とされている。例えば、半導体チップ３０は、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistorの略）やＩＧＢＴ（Insulated Gate Bipolar Transistorの略）等の半導体素子を有する構成とされている。そして、半導体チップ３０は、他面３０ｂがアイランド部２１と対向するように、アイランド部２１の一面２１１上に接合部材４０を介して配置されている。接合部材４０は、例えば、はんだ、銀ペースト、導電性接着剤等が用いられる。 The semiconductor chip 30 has one side 30a and another side 30b, and is configured to have a semiconductor element formed by a general semiconductor manufacturing process. For example, the semiconductor chip 30 is configured to have semiconductor elements such as MOSFET (abbreviation of Metal Oxide Semiconductor Field Effect Transistor) and IGBT (abbreviation of Insulated Gate Bipolar Transistor). The semiconductor chip 30 is arranged on one surface 211 of the island portion 21 via a joining member 40 so that the other surface 30b faces the island portion 21. For the joining member 40, for example, solder, silver paste, a conductive adhesive, or the like is used.
　また、半導体チップ３０は、一面３０ａ側に図示しない電極パッドが形成されている。そして、半導体チップ３０は、電極パッドが端子部２２の一面２２１とボンディングワイヤ５０を介して電気的に接続されている。なお、ボンディングワイヤ５０は、アルミニウム、金、銅等で構成される。 Further, the semiconductor chip 30 has an electrode pad (not shown) formed on one side 30a side. Then, in the semiconductor chip 30, the electrode pad is electrically connected to one side 221 of the terminal portion 22 via the bonding wire 50. The bonding wire 50 is made of aluminum, gold, copper, or the like.
　モールド樹脂６０は、例えば、エポキシ樹脂等で構成されている。そして、モールド樹脂６０は、アイランド部２１の他面２１２、端子部２２の他面２２２および側面２２３の一部を露出させつつ、半導体チップ３０、アイランド部２１の一面２１１、端子部２２の一面２１１、半導体チップ３０等を封止するように配置されている。 The mold resin 60 is made of, for example, an epoxy resin or the like. Then, the mold resin 60 exposes a part of the other surface 212 of the island portion 21, the other surface 222 of the terminal portion 22, and the side surface 223, while exposing the semiconductor chip 30, one surface 211 of the island portion 21, and one surface 211 of the terminal portion 22. , The semiconductor chip 30 and the like are arranged so as to be sealed.
　具体的には、モールド樹脂６０は、金型を用いたコンプレッション成形やトランスファー成形等で形成され、本実施形態では、一面６１、一面６１と反対側の他面６２、一面６１と他面６２とを繋ぐ側面６３を有する略直方体形状とされている。そして、モールド樹脂６０は、他面６２からアイランド部２１の他面２１２および端子部２２の他面２２２が露出すると共に、側面６３から端子部２２の側面２２３の一部が露出するように配置されている。つまり、本実施形態の半導体パッケージ１０は、いわゆるＱＦＮ（Quad For Non-Lead Packageの略）とされている。なお、以下では、端子部２２の側面２２３のうちのモールド樹脂６０から露出する側面を単に露出側面２２３ａともいう。 Specifically, the mold resin 60 is formed by compression molding or transfer molding using a mold, and in the present embodiment, the one side 61, the other side 62 opposite to the one side 61, the one side 61 and the other side 62. It has a substantially rectangular parallelepiped shape having side surfaces 63 connecting the two. The mold resin 60 is arranged so that the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 are exposed from the other surface 62, and a part of the side surface 223 of the terminal portion 22 is exposed from the side surface 63. ing. That is, the semiconductor package 10 of this embodiment is a so-called QFN (abbreviation of Quad For Non-Lead Package). In the following, the side surface of the side surface 223 of the terminal portion 22 exposed from the mold resin 60 is also simply referred to as an exposed side surface 223a.
　本実施形態では、モールド樹脂６０の他面６２、アイランド部２１の他面２１２、端子部２２の他面２２２は、同一平面上に位置するように配置されている。また、モールド樹脂６０の側面６３および露出側面２２３ａは、同一平面上に位置するように配置されている。 In the present embodiment, the other surface 62 of the mold resin 60, the other surface 212 of the island portion 21, and the other surface 222 of the terminal portion 22 are arranged so as to be located on the same plane. Further, the side surface 63 and the exposed side surface 223a of the mold resin 60 are arranged so as to be located on the same plane.
　以上が本実施形態における半導体パッケージ１０の基本的な構成である。そして、本実施形態では、モールド樹脂６０には、他面６２側に凸部６２ａが形成されている。本実施形態では、凸部６２ａは、モールド樹脂６０の他面６２において、アイランド部２１と端子部２２との間に位置する部分に複数形成されている。より詳しくは、凸部６２ａは、アイランド部２１と半導体チップ３０との積層方向において（以下では、単に積層方向という）、アイランド部２１を囲むように形成されている。 The above is the basic configuration of the semiconductor package 10 in this embodiment. Then, in the present embodiment, the mold resin 60 is formed with a convex portion 62a on the other surface 62 side. In the present embodiment, a plurality of convex portions 62a are formed on the other surface 62 of the mold resin 60 at a portion located between the island portion 21 and the terminal portion 22. More specifically, the convex portion 62a is formed so as to surround the island portion 21 in the stacking direction of the island portion 21 and the semiconductor chip 30 (hereinafter, simply referred to as the stacking direction).
　なお、本実施形態では、凸部６２ａが保持構造に相当している。また、このような凸部６２ａは、例えば、モールド樹脂６０を成形する際、凸部６２ａが形成される金型を用意することによって形成される。そして、上記積層方向においてとは、言い換えると、アイランド部２１と半導体チップ３０との積層方向から視たとき、ということもできる。 In the present embodiment, the convex portion 62a corresponds to the holding structure. Further, such a convex portion 62a is formed, for example, by preparing a mold on which the convex portion 62a is formed when molding the mold resin 60. In other words, the stacking direction can be said to be when viewed from the stacking direction of the island portion 21 and the semiconductor chip 30.
　プリント基板１００は、図３に示されるように、一面１０１側に、銅やアルミニウム等で構成される第１ランド１１１および第２ランド１１２が形成されている。第１ランド１１１は、半導体パッケージ１０のアイランド部２１に対応する形状とされ、第２ランド１１２は、半導体パッケージ１０の端子部２２に対応する形状とされている。また、プリント基板１００の一面１０１には、第１ランド１１１および第２ランド１１２が露出するように、図示しないソルダーレジスト等の被覆部材も形成されている。 As shown in FIG. 3, the printed circuit board 100 has a first land 111 and a second land 112 made of copper, aluminum, or the like formed on one side 101 side. The first land 111 has a shape corresponding to the island portion 21 of the semiconductor package 10, and the second land 112 has a shape corresponding to the terminal portion 22 of the semiconductor package 10. Further, a covering member such as a solder resist (not shown) is also formed on one surface 101 of the printed circuit board 100 so that the first land 111 and the second land 112 are exposed.
　そして、半導体パッケージ１０は、アイランド部２１が第１ランド１１１とはんだ２００を介して接続され、端子部２２が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。この場合、本実施形態では、モールド樹脂６０に凸部６２ａが形成されているため、アイランド部２１の他面２１２および端子部２２の他面２２２と、第１、第２ランド１１１、１１２との間隔が確保される。このため、はんだ２００の厚さが薄くなることを抑制でき、はんだ２００が破壊されることを抑制できる。なお、半導体パッケージ１０とプリント基板１００との間には、図示しないアンダーフィル材が配置されている。また、はんだ２００は、例えば、スズ銀銅はんだ等が用いられる。 Then, in the semiconductor package 10, one side 101 of the printed circuit board 100 is connected so that the island portion 21 is connected to the first land 111 via the solder 200 and the terminal portion 22 is connected to the second land 112 via the solder 200. It is placed on top. In this case, in this embodiment, since the convex portion 62a is formed on the mold resin 60, the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 and the first and second lands 111 and 112 The interval is secured. Therefore, it is possible to prevent the thickness of the solder 200 from becoming thin, and it is possible to prevent the solder 200 from being broken. An underfill material (not shown) is arranged between the semiconductor package 10 and the printed circuit board 100. Further, as the solder 200, for example, tin silver copper solder or the like is used.
　以上が本実施形態における半導体装置の構成である。次に、上記半導体装置における半導体パッケージ１０をプリント基板１００に配置する方法について、簡単に説明する。 The above is the configuration of the semiconductor device in this embodiment. Next, a method of arranging the semiconductor package 10 in the semiconductor device on the printed circuit board 100 will be briefly described.
　まず、上記半導体パッケージ１０およびプリント基板１００を用意する。なお、半導体パッケージ１０は、次のように用意される。まず、アイランド部２１上に半導体チップ３０を接合部材４０を介して配置した後、半導体チップ３０と端子部２２とをボンディングワイヤ５０を介して電気的に接続する。その後、アイランド部２１の他面２１２、端子部２２の他面２２２および露出側面２２３ａが露出するように、モールド樹脂６０を成形する。 First, the semiconductor package 10 and the printed circuit board 100 are prepared. The semiconductor package 10 is prepared as follows. First, the semiconductor chip 30 is arranged on the island portion 21 via the bonding member 40, and then the semiconductor chip 30 and the terminal portion 22 are electrically connected via the bonding wire 50. After that, the mold resin 60 is molded so that the other surface 212 of the island portion 21, the other surface 222 of the terminal portion 22, and the exposed side surface 223a are exposed.
　そして、プリント基板１００の第１ランド１１１および第２ランド１１２上に、印刷法等によってはんだペーストを配置する。次に、アイランド部２１および端子部２２がはんだペーストと接触するように、はんだペースト上に上記半導体パッケージ１０を配置する。その後、リフローを行うことにより、アイランド部２１と第１ランド１１１とがはんだ２００を介して接続されると共に、端子部２２と第２ランド１１２とがはんだ２００を介して接続されるようにする。これにより、半導体パッケージ１０がプリント基板１００と接続されて上記半導体装置が製造される。 Then, the solder paste is placed on the first land 111 and the second land 112 of the printed circuit board 100 by a printing method or the like. Next, the semiconductor package 10 is arranged on the solder paste so that the island portion 21 and the terminal portion 22 come into contact with the solder paste. After that, by performing reflow, the island portion 21 and the first land 111 are connected via the solder 200, and the terminal portion 22 and the second land 112 are connected via the solder 200. As a result, the semiconductor package 10 is connected to the printed circuit board 100 to manufacture the semiconductor device.
　以上説明したように、本実施形態では、モールド樹脂６０の他面６２に凸部６２ａが形成されているため、アイランド部２１の他面２１２および端子部２２の他面２２２と、第１、第２ランド１１１、１１２との間隔が確保される。このため、はんだ２００の厚さが薄くなることを抑制でき、はんだ２００を所定以上の厚さに保持することができる。したがって、はんだ２００が破壊されることを抑制でき、はんだ２００の信頼性の向上を図ることができる。 As described above, in the present embodiment, since the convex portion 62a is formed on the other surface 62 of the mold resin 60, the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22, and the first and first surfaces. The distance between the two lands 111 and 112 is secured. Therefore, it is possible to prevent the thickness of the solder 200 from becoming thin, and the solder 200 can be held at a predetermined thickness or more. Therefore, it is possible to suppress the destruction of the solder 200 and improve the reliability of the solder 200.
　また、本実施形態では、凸部６２ａは、積層方向において、アイランド部２１を囲むように形成されている。このため、半導体パッケージ１０がプリント基板１００の一面１０１に対して傾くことを抑制できる。 Further, in the present embodiment, the convex portion 62a is formed so as to surround the island portion 21 in the stacking direction. Therefore, it is possible to prevent the semiconductor package 10 from tilting with respect to one surface 101 of the printed circuit board 100.
　（第１実施形態の変形例）
　第１実施形態の変形例について説明する。凸部６２ａは、モールド樹脂６０の他面６２において、アイランド部２１と端子部２２との間に１つのみ形成されていてもよい。この場合、凸部６２ａは、モールド樹脂６０の他面６２において、アイランド部２１を囲むように枠状とされていてもよい。さらに、凸部６２ａは、アイランド部２１の他面６２において、隣合う端子部２２の間に形成されていてもよい。 (Modified example of the first embodiment)
A modified example of the first embodiment will be described. Only one convex portion 62a may be formed between the island portion 21 and the terminal portion 22 on the other surface 62 of the mold resin 60. In this case, the convex portion 62a may be frame-shaped so as to surround the island portion 21 on the other surface 62 of the mold resin 60. Further, the convex portion 62a may be formed between the adjacent terminal portions 22 on the other surface 62 of the island portion 21.
　（第２実施形態）
　第２実施形態について説明する。本実施形態は、第１実施形態に対し、端子部２２に突起部を形成したものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (Second Embodiment)
The second embodiment will be described. In this embodiment, a protrusion is formed on the terminal portion 22 as compared with the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体パッケージ１０は、図４に示されるように、端子部２２の他面２２２に、モールド樹脂６０の他面６２から突出する突起部２２２ａが形成されている。なお、本実施形態では、突起部２２２ａが保持構造に相当している。 In the semiconductor package 10 of the present embodiment, as shown in FIG. 4, a protrusion 222a protruding from the other surface 62 of the mold resin 60 is formed on the other surface 222 of the terminal portion 22. In this embodiment, the protrusion 222a corresponds to the holding structure.
　このような突起部２２２ａは、例えば、次のように形成される。すなわち、まず、アイランド部２１の他面２１２および端子部２２の他面２２２が露出するようにモールド樹脂６０を成形する。その後、アイランド部２１の他面２１２、端子部２２の他面２２２のうちの突起部２２２ａとなる部分と異なる部分、およびモールド樹脂６０の他面６２をエッチング等で全体的に除去する。これにより、モールド樹脂６０の他面６２から突出する突起部２２２ａが構成された半導体パッケージ１０が形成される。 Such a protrusion 222a is formed, for example, as follows. That is, first, the mold resin 60 is molded so that the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 are exposed. After that, the other surface 212 of the island portion 21, the portion of the other surface 222 of the terminal portion 22 different from the portion to be the protrusion 222a, and the other surface 62 of the mold resin 60 are totally removed by etching or the like. As a result, the semiconductor package 10 in which the protrusion 222a protruding from the other surface 62 of the mold resin 60 is formed is formed.
　以上が本実施形態における半導体パッケージ１０の構成である。そして、半導体パッケージ１０は、図５に示されるように、アイランド部２１が第１ランド１１１とはんだ２００を介して接続され、端子部２２が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。この場合、本実施形態では、端子部２２に突起部２２２ａが形成されているため、アイランド部２１の他面２１２および端子部２２の他面２２２と、第１、第２ランド１１１、１１２との間隔が確保される。このため、はんだ２００の厚さが薄くなることを抑制できる。 The above is the configuration of the semiconductor package 10 in this embodiment. Then, as shown in FIG. 5, in the semiconductor package 10, the island portion 21 is connected to the first land 111 via the solder 200, and the terminal portion 22 is connected to the second land 112 via the solder 200. Is arranged on one side 101 of the printed circuit board 100. In this case, in the present embodiment, since the protrusion 222a is formed on the terminal portion 22, the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 and the first and second lands 111 and 112 The interval is secured. Therefore, it is possible to prevent the solder 200 from becoming thin.
　以上説明したように、本実施形態では、端子部２２に突起部２２２ａが形成されているため、アイランド部２１の他面２１２および端子部２２の他面２２２と、第１、第２ランド１１１、１１２との間隔が確保される。このため、はんだ２００の厚さが薄くなることを抑制でき、はんだ２００の信頼性の向上を図ることができる。 As described above, in the present embodiment, since the protrusion 222a is formed on the terminal portion 22, the other surface 212 of the island portion 21, the other surface 222 of the terminal portion 22, and the first and second lands 111, The distance from 112 is secured. Therefore, it is possible to prevent the thickness of the solder 200 from becoming thin, and it is possible to improve the reliability of the solder 200.
　（第２実施形態の変形例）
　第２実施形態の変形例について説明する。突起部２２２ａは、端子部２２に加えてアイランド部２１に形成されていてもよいし、アイランド部２１のみに形成されていてもよい。 (Modified example of the second embodiment)
A modified example of the second embodiment will be described. The protrusion 222a may be formed on the island portion 21 in addition to the terminal portion 22, or may be formed only on the island portion 21.
　また、突起部２２２ａは、図６に示されるように、端子部２２の他面２２２にワイヤボンディングを行うことによって形成するようにしてもよい。この場合、図７に示されるように、第２ランド１１２にもワイヤボンディングを行うことによって突起部１１２ａを形成するようにしてもよい。そして、半導体パッケージ１０をプリント基板１００に配置する際、端子部２２の突起部２２２ａと第２ランド１１２の突起部１１２ａとが当接するように配置することにより、さらにはんだ２００の厚さが薄くなることを抑制できる。 Further, as shown in FIG. 6, the protrusion 222a may be formed by wire bonding to the other surface 222 of the terminal 22. In this case, as shown in FIG. 7, the protrusion 112a may be formed by wire bonding also on the second land 112. When the semiconductor package 10 is arranged on the printed circuit board 100, the thickness of the solder 200 is further reduced by arranging the protrusions 222a of the terminal portion 22 and the protrusions 112a of the second land 112 so as to be in contact with each other. Can be suppressed.
　（第３実施形態）
　第３実施形態について説明する。本実施形態は、第１実施形態に対し、アイランド部２１の他面２１２および端子部２２の他面２２２に阻害膜を配置したものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (Third Embodiment)
The third embodiment will be described. In this embodiment, the inhibitory film is arranged on the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 with respect to the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体パッケージ１０は、図８および図９に示されるように、端子部２２には、他面２２２のうちの露出側面２２３ａとの境界部分に、端子部２２よりもはんだ濡れ性の低い材料で構成された阻害膜７０が配置されている。なお、阻害膜７０は、例えば、ソルダーレジスト等で構成される。また、本実施形態では、阻害膜７０が保持構造に相当している。そして、図９では、後述するはんだボール２０１を省略して示してある。 As shown in FIGS. 8 and 9, the semiconductor package 10 of the present embodiment has a terminal portion 22 that is more solder wettable than the terminal portion 22 at the boundary portion between the other surface 222 and the exposed side surface 223a. An inhibitory membrane 70 made of a low material is arranged. The inhibitory membrane 70 is made of, for example, a solder resist or the like. Further, in the present embodiment, the inhibitory membrane 70 corresponds to the holding structure. Then, in FIG. 9, the solder ball 201, which will be described later, is omitted.
　本実施形態では、阻害膜７０は、端子部２２の他面２２２における外縁部を囲むように配置されている。また、阻害膜７０は、端子部２２の他面２２２に、阻害膜７０から露出する２つの領域が区画形成されるように配置されている。具体的には、阻害膜７０は、端子部２２の他面２２２の外縁部および略中央部を被覆するように配置されている。 In the present embodiment, the inhibitory film 70 is arranged so as to surround the outer edge portion on the other surface 222 of the terminal portion 22. Further, the inhibitory film 70 is arranged on the other surface 222 of the terminal portion 22 so that two regions exposed from the inhibitory film 70 are partitioned. Specifically, the inhibitory film 70 is arranged so as to cover the outer edge portion and the substantially central portion of the other surface 222 of the terminal portion 22.
　同様に、アイランド部２１の他面２１２には、阻害膜７０から露出する複数の領域が区画形成されるように、阻害膜７０が配置されている。 Similarly, the inhibitory film 70 is arranged on the other surface 212 of the island portion 21 so that a plurality of regions exposed from the inhibitory film 70 are partitioned.
　そして、アイランド部２１の他面２１２および端子部２２の他面２２２のうちの阻害膜７０から露出する部分には、はんだボール２０１が配置されている。つまり、本実施形態の半導体パッケージ１０は、いわゆるＢＧＡ（Ball Grid Arrayの略）とされている。なお、本実施形態では、端子部２２の他面２２２に備えられる阻害膜７０は、阻害膜７０から２つの領域が露出するように配置されている。このため、端子部２２には、２つのはんだボール２０１が配置されている。 Then, the solder balls 201 are arranged on the portion of the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 that is exposed from the inhibitory film 70. That is, the semiconductor package 10 of this embodiment is a so-called BGA (abbreviation of Ball Grid Array). In the present embodiment, the inhibitory film 70 provided on the other surface 222 of the terminal portion 22 is arranged so that two regions are exposed from the inhibitory film 70. Therefore, two solder balls 201 are arranged on the terminal portion 22.
　以上が本実施形態における半導体パッケージ１０の構成である。 The above is the configuration of the semiconductor package 10 in this embodiment.
　プリント基板１００は、図１０に示されるように、アイランド部２１および端子部２２に形成された阻害膜７０と対向する位置に阻害膜１２０が形成されている。具体的には、第１ランド１１１には、アイランド部２１の他面２１２に形成された阻害膜７０と対向する位置に阻害膜１２０が形成されている。第２ランド１１２には、端子部２２の他面２２２に形成された阻害膜７０と対向する位置に阻害膜１２０が形成されている。なお、阻害膜１２０は、阻害膜７０と同様に、第１、第２ランド１１１、１１２よりはんだ濡れ性の低いソルダーレジスト等で構成される。 As shown in FIG. 10, the printed circuit board 100 has an inhibitory film 120 formed at a position facing the inhibitory film 70 formed on the island portion 21 and the terminal portion 22. Specifically, in the first land 111, the inhibitory film 120 is formed at a position facing the inhibitory film 70 formed on the other surface 212 of the island portion 21. In the second land 112, the inhibitory film 120 is formed at a position facing the inhibitory film 70 formed on the other surface 222 of the terminal portion 22. The inhibitor film 120 is made of a solder resist or the like having a lower solder wettability than the first and second lands 111 and 112, similarly to the inhibitor film 70.
　そして、半導体パッケージ１０は、アイランド部２１が第１ランド１１１とはんだ２００を介して接続され、端子部２２が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。なお、端子部２２と第２ランド１１２とは、２つのはんだ２００を介して接続されている。また、アイランド部２１と第１ランド１１１とは、複数のはんだ２００を介して接続されている。 Then, in the semiconductor package 10, one side 101 of the printed circuit board 100 is connected so that the island portion 21 is connected to the first land 111 via the solder 200 and the terminal portion 22 is connected to the second land 112 via the solder 200. It is placed on top. The terminal portion 22 and the second land 112 are connected via two solders 200. Further, the island portion 21 and the first land 111 are connected via a plurality of solders 200.
　この場合、端子部２２の他面２２２のうちの露出側面２２３ａとの境界部分に阻害膜７０が配置されているため、はんだ２００が端子部２２の露出側面２２３ａに這い上がることを抑制できる。したがって、はんだ２００の厚さが薄くなることを抑制できる。 In this case, since the inhibitory film 70 is arranged at the boundary portion of the other surface 222 of the terminal portion 22 with the exposed side surface 223a, it is possible to prevent the solder 200 from creeping up to the exposed side surface 223a of the terminal portion 22. Therefore, it is possible to prevent the solder 200 from becoming thin.
　以上説明したように、本実施形態では、端子部２２の他面２２２のうちの露出側面２２３ａとの境界部分に阻害膜７０が配置されている。このため、はんだ２００が端子部２２の露出側面２２３ａに這い上がることを抑制できる。したがって、はんだ２００の厚さが薄くなることを抑制でき、信頼性の向上を図ることができる。 As described above, in the present embodiment, the inhibitory film 70 is arranged at the boundary portion between the other surface 222 of the terminal portion 22 and the exposed side surface 223a. Therefore, it is possible to prevent the solder 200 from creeping up to the exposed side surface 223a of the terminal portion 22. Therefore, it is possible to prevent the thickness of the solder 200 from becoming thin, and it is possible to improve the reliability.
　また、本実施形態では、半導体パッケージ１０にはんだボール２０１が配置されている。このため、半導体装置では、はんだ２００は、半導体パッケージ１０のはんだボール２０１と、半導体パッケージ１０をプリント基板１００に配置する際に第１、第２ランド１１１、１１２に配置されるはんだペーストとによって構成される。これにより、本実施形態の半導体装置では、アイランド部２１と第１ランド１１１との間、および端子部２２と第２ランド１１２との間に配置されるはんだ２００がはんだペーストのみで構成される場合と比較して、はんだ２００を厚くできる。したがって、さらに信頼性の向上を図ることができる。 Further, in the present embodiment, the solder balls 201 are arranged in the semiconductor package 10. Therefore, in the semiconductor device, the solder 200 is composed of the solder balls 201 of the semiconductor package 10 and the solder pastes arranged on the first and second lands 111 and 112 when the semiconductor package 10 is arranged on the printed circuit board 100. Will be done. As a result, in the semiconductor device of the present embodiment, when the solder 200 arranged between the island portion 21 and the first land 111 and between the terminal portion 22 and the second land 112 is composed of only solder paste. The solder 200 can be made thicker than the above. Therefore, the reliability can be further improved.
　さらに、半導体パッケージ１０は、端子部２２に阻害膜７０によって２つの領域が区画形成されており、各領域にはんだボール２０１が配置されている。また、プリント基板１００の第２ランド１１２には、端子部２２の他面２２２に形成された阻害膜７０と対向する位置に阻害膜１２０が形成されている。そして、半導体パッケージ１０における端子部２２と第２ランド１１２とは、２つのはんだ２００を介して接続されている。このため、一方のはんだ２００が破壊されたとしても、他方のはんだ２００で電気的な接続を確保でき、耐久性の向上を図ることができる。 Further, in the semiconductor package 10, two regions are formed in the terminal portion 22 by the inhibitory film 70, and the solder balls 201 are arranged in each region. Further, on the second land 112 of the printed circuit board 100, the inhibitory film 120 is formed at a position facing the inhibitory film 70 formed on the other surface 222 of the terminal portion 22. The terminal portion 22 and the second land 112 in the semiconductor package 10 are connected via two solders 200. Therefore, even if one of the solders 200 is destroyed, the other solders 200 can secure an electrical connection and improve the durability.
　同様に、半導体パッケージ１０は、アイランド部２１と第１ランド１１１とが複数のはんだ２００を介して接続されている。このため、アイランド部２１と第１ランド１１１との間において、一部のはんだ２００が破壊されたとしても残りのはんだ２００で接続を確保でき、耐久性の向上を図ることができる。 Similarly, in the semiconductor package 10, the island portion 21 and the first land 111 are connected via a plurality of solders 200. Therefore, even if a part of the solder 200 is broken between the island portion 21 and the first land 111, the remaining solder 200 can secure the connection, and the durability can be improved.
　（第３実施形態の変形例）
　第３実施形態の変形例について説明する。例えば、端子部２２には、他面２２２のうちの露出側面２２３ａとの境界部分にのみ阻害膜７０が配置されるようにしてもよい。また、阻害膜７０は、端子部２２の他面２２２において、１つの領域のみを露出させるように形成されていてもよいし、３つ以上の領域を露出させるように形成されていてもよい。 (Modified example of the third embodiment)
A modified example of the third embodiment will be described. For example, in the terminal portion 22, the inhibitory film 70 may be arranged only at the boundary portion between the other surface 222 and the exposed side surface 223a. Further, the inhibitory film 70 may be formed on the other surface 222 of the terminal portion 22 so as to expose only one region, or may be formed so as to expose three or more regions.
　さらに、半導体パッケージ１０は、はんだボール２０１を備えない構成としてもよい。このような構成としても、端子部２２に阻害膜７０が配置されていることにより、はんだ２００が露出側面２２３ａへ這い上がることが抑制されるため、はんだ２００の厚さが薄くなることを抑制できる。 Further, the semiconductor package 10 may be configured not to include the solder balls 201. Even with such a configuration, since the inhibitory film 70 is arranged on the terminal portion 22, it is possible to prevent the solder 200 from climbing up to the exposed side surface 223a, so that it is possible to prevent the solder 200 from becoming thin. ..
　さらに、阻害膜７０は、複数の端子部２２のうちの一部のみに形成されていてもよい。 Further, the inhibitory film 70 may be formed only on a part of the plurality of terminal portions 22.
　（第４実施形態）
　第４実施形態について説明する。本実施形態は、第１実施形態に対し、アイランド部２１の他面２１２の一部および端子部２２の他面２２２にメッキ膜を配置したものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (Fourth Embodiment)
A fourth embodiment will be described. In this embodiment, the plating film is arranged on a part of the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 with respect to the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体パッケージ１０は、図１１に示されるように、アイランド部２１の他面２１２および端子部２２の他面２２２にメッキ膜８０が形成されている。本実施形態では、アイランド部２１の他面２１２は、部分的にメッキ膜８０が形成され、メッキ膜８０が形成されている部分と異なる部分に阻害膜８１が形成されている。端子部２２の他面２２２には、全面にメッキ膜８０が形成されている。 In the semiconductor package 10 of the present embodiment, as shown in FIG. 11, a plating film 80 is formed on the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22. In the present embodiment, the plating film 80 is partially formed on the other surface 212 of the island portion 21, and the inhibitory film 81 is formed at a portion different from the portion where the plating film 80 is formed. A plating film 80 is formed on the entire surface of the other surface 222 of the terminal portion 22.
　なお、メッキ膜８０は、例えば、他面２１２、２２２側からニッケル（Ｎｉ）、パラジウム（Ｐｄ）、金（Ａｕ）が積層されて構成されている。阻害膜８１は、メッキ膜８０よりもはんだ濡れ性の低い材料で構成され、酸化膜で構成される。このような阻害膜８１は、例えば、アイランド部２１の他面２１２の所定箇所および端子部２２の他面２２２にメッキ膜８０を形成した後、熱酸化等することで形成される。また、本実施形態では、メッキ膜８０および阻害膜８１が保持構造に相当している。 The plating film 80 is formed by laminating nickel (Ni), palladium (Pd), and gold (Au) from the other surface 212 and 222 sides, for example. The inhibitory film 81 is made of a material having a lower solder wettability than the plating film 80, and is made of an oxide film. Such an inhibitory film 81 is formed, for example, by forming a plating film 80 on a predetermined portion of the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22, and then performing thermal oxidation or the like. Further, in the present embodiment, the plating film 80 and the inhibitory film 81 correspond to the holding structure.
　以上が本実施形態における半導体パッケージ１０の構成である。 The above is the configuration of the semiconductor package 10 in this embodiment.
　プリント基板１００は、図１２に示されるように、第１ランド１１１に阻害膜１２０が形成されている。具体的には、阻害膜１２０は、第１ランド１１１のうちのメッキ膜８０と対向する部分を露出させるように形成されている。つまり、阻害膜１２０は、阻害膜８１と対向するように形成されている。 As shown in FIG. 12, the printed circuit board 100 has an inhibitory film 120 formed on the first land 111. Specifically, the inhibitory film 120 is formed so as to expose a portion of the first land 111 facing the plating film 80. That is, the inhibitory membrane 120 is formed so as to face the inhibitory membrane 81.
　そして、半導体パッケージ１０は、アイランド部２１が第１ランド１１１とはんだ２００を介して接続され、端子部２２が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。この場合、半導体パッケージ１０側では、メッキ膜８０が形成されていない部分にはんだ２００が濡れ広がり難いため、はんだ２００の厚さが薄くなることを抑制できる。 Then, in the semiconductor package 10, one side 101 of the printed circuit board 100 is connected so that the island portion 21 is connected to the first land 111 via the solder 200 and the terminal portion 22 is connected to the second land 112 via the solder 200. It is placed on top. In this case, on the semiconductor package 10 side, the solder 200 is unlikely to get wet and spread on the portion where the plating film 80 is not formed, so that it is possible to prevent the solder 200 from becoming thin.
　以上説明したように、本実施形態では、アイランド部２１の他面２１２は、はんだ濡れ性が高いメッキ膜８０とはんだ濡れ性が低い阻害膜８１とが形成されている。このため、アイランド部２１と第１ランド１１１との間に位置するはんだ２００は、メッキ膜８０が形成されていない部分に濡れ広がり難くなる。したがって、この部分のはんだ２００の厚さが薄くなることを抑制することができ、全体的にはんだ２００の厚さが薄くなることを抑制できる。これにより、はんだ２００の信頼性の向上を図ることができる。 As described above, in the present embodiment, the other surface 212 of the island portion 21 is formed with a plating film 80 having a high solder wettability and an inhibitory film 81 having a low solder wettability. Therefore, the solder 200 located between the island portion 21 and the first land 111 is less likely to get wet and spread in the portion where the plating film 80 is not formed. Therefore, it is possible to suppress the thinning of the solder 200 in this portion, and it is possible to suppress the thinning of the solder 200 as a whole. As a result, the reliability of the solder 200 can be improved.
　また、プリント基板１００には、第１ランド１１１に阻害膜１２０が形成されているため、上記第３実施形態と同様の効果を得ることもできる。 Further, since the inhibitor film 120 is formed on the first land 111 on the printed circuit board 100, the same effect as that of the third embodiment can be obtained.
　（第４実施形態の変形例）
　第４実施形態の変形例について説明する。端子部２２の他面２２２は、アイランド部２１と同様に、メッキ膜８０および阻害膜８１が形成されるようにしてもよい。この場合、アイランド部２１の他面２１２は、全面にメッキ膜８０が形成されていてもよい。 (Modified example of the fourth embodiment)
A modified example of the fourth embodiment will be described. Similar to the island portion 21, the other surface 222 of the terminal portion 22 may be formed with the plating film 80 and the inhibition film 81. In this case, the plating film 80 may be formed on the entire surface of the other surface 212 of the island portion 21.
　（第５実施形態）
　第５実施形態について説明する。本実施形態は、第１実施形態に対し、アイランド部２１および端子部２２に転写はんだを配置したものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (Fifth Embodiment)
A fifth embodiment will be described. In this embodiment, the transfer solder is arranged on the island portion 21 and the terminal portion 22 as compared with the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体パッケージ１０は、図１３に示されるように、アイランド部２１の他面２１２および端子部２２の他面２２２は、モールド樹脂６０の他面６２から突出した状態となっている。つまり、モールド樹脂６０は、他面６２がアイランド部２１の他面２１２および端子部２２の他面２２２よりも凹んだ状態となっている。 In the semiconductor package 10 of the present embodiment, as shown in FIG. 13, the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 are in a state of protruding from the other surface 62 of the mold resin 60. That is, the other surface 62 of the mold resin 60 is recessed from the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22.
　そして、アイランド部２１の他面２１２、および端子部２２の他面２２２には、転写はんだ２０２が配置されている。なお、この転写はんだ２０２は、溶融はんだが配置された処理槽に、アイランド部２１の他面２１２および端子部２２の他面２２２を浸すことによってはんだを転写する転写法によって形成される。また、本実施形態では、転写はんだ２０２が保持構造に相当している。 Then, the transfer solder 202 is arranged on the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22. The transfer solder 202 is formed by a transfer method in which the solder is transferred by immersing the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 in a processing tank in which the molten solder is arranged. Further, in the present embodiment, the transfer solder 202 corresponds to the holding structure.
　以上が本実施形態における半導体パッケージ１０の構成である。そして、半導体パッケージ１０は、図１４に示されるように、アイランド部２１が第１ランド１１１とはんだ２００を介して接続され、端子部２２が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。この場合、本実施形態では、はんだ２００は、半導体パッケージ１０の転写はんだ２０２と、半導体パッケージ１０をプリント基板１００に配置する際に第１、第２ランド１１１、１１２に配置されるはんだペーストとによって構成される。このため、本実施形態の半導体装置では、アイランド部２１と第１ランド１１１との間、および端子部２２と第２ランド１１２との間に配置されるはんだ２００がはんだペーストのみで構成される場合と比較して、はんだ２００を厚くできる。 The above is the configuration of the semiconductor package 10 in this embodiment. Then, as shown in FIG. 14, in the semiconductor package 10, the island portion 21 is connected to the first land 111 via the solder 200, and the terminal portion 22 is connected to the second land 112 via the solder 200. Is arranged on one side 101 of the printed circuit board 100. In this case, in the present embodiment, the solder 200 is composed of the transfer solder 202 of the semiconductor package 10 and the solder pastes arranged on the first and second lands 111 and 112 when the semiconductor package 10 is arranged on the printed circuit board 100. It is composed. Therefore, in the semiconductor device of the present embodiment, when the solder 200 arranged between the island portion 21 and the first land 111 and between the terminal portion 22 and the second land 112 is composed of only solder paste. The solder 200 can be made thicker than the above.
　次に、本実施形態の半導体パッケージ１０の製造方法について説明する。 Next, the manufacturing method of the semiconductor package 10 of the present embodiment will be described.
　まず、図１５Ａに示されるように、アイランド部２１および端子部２２を有し、アイランド部２１と端子部２２との間が連結されたリードフレーム２０を用意する。そして、アイランド部２１と端子部２２との間に位置する部分に対してハーフエッチングを行い、凹部２３を形成する。 First, as shown in FIG. 15A, a lead frame 20 having an island portion 21 and a terminal portion 22 and in which the island portion 21 and the terminal portion 22 are connected is prepared. Then, half-etching is performed on the portion located between the island portion 21 and the terminal portion 22 to form the recess 23.
　次に、アイランド部２１の一面２１１上に半導体チップ３０を接合部材４０を介して配置すると共に、半導体チップ３０と端子部２２とをボンディングワイヤ５０を介して電気的に接続する。その後、コンプレッション成形やトランスファー成形等により、半導体チップ３０等を封止するようにモールド樹脂６０を成形する。 Next, the semiconductor chip 30 is arranged on one surface 211 of the island portion 21 via the bonding member 40, and the semiconductor chip 30 and the terminal portion 22 are electrically connected via the bonding wire 50. After that, the mold resin 60 is molded so as to seal the semiconductor chip 30 or the like by compression molding, transfer molding, or the like.
　次に、図１５Ｂに示されるように、アイランド部２１の他面２１２側および端子部２２の他面２２２側からエッチングを行い、凹部２３を貫通させる。これにより、アイランド部２１の他面２１２および端子部２２の他面２２２がモールド樹脂６０の他面６２から突出した状態となる。 Next, as shown in FIG. 15B, etching is performed from the other surface 212 side of the island portion 21 and the other surface 222 side of the terminal portion 22 to penetrate the recess 23. As a result, the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 are in a state of protruding from the other surface 62 of the mold resin 60.
　その後、図１５Ｃに示されるように、アイランド部２１の他面２１２および端子部２２の他面２２２に転写はんだ２０２を配置することにより、本実施形態の半導体パッケージ１０が製造される。 After that, as shown in FIG. 15C, the semiconductor package 10 of the present embodiment is manufactured by arranging the transfer solder 202 on the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22.
　以上説明したように、本実施形態では、半導体パッケージ１０には、アイランド部２１の他面２１２および端子部２２の他面２２２に転写はんだ２０２が配置されている。そして、半導体装置では、はんだ２００は、半導体パッケージ１０の転写はんだ２０２と、半導体パッケージ１０をプリント基板１００に配置する際に第１、第２ランド１１１、１１２に配置されるはんだペーストとによって構成される。このため、半導体装置では、アイランド部２１と第１ランド１１１との間、および端子部２２と第２ランド１１２との間に配置されるはんだ２００がはんだペーストのみで構成される場合と比較して、はんだ２００を厚くできる。したがって、さらに信頼性の向上を図ることができる。 As described above, in the present embodiment, the transfer solder 202 is arranged on the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 in the semiconductor package 10. Then, in the semiconductor device, the solder 200 is composed of the transfer solder 202 of the semiconductor package 10 and the solder pastes arranged on the first and second lands 111 and 112 when the semiconductor package 10 is arranged on the printed circuit board 100. Ru. Therefore, in the semiconductor device, as compared with the case where the solder 200 arranged between the island portion 21 and the first land 111 and between the terminal portion 22 and the second land 112 is composed of only the solder paste. , The solder 200 can be thickened. Therefore, the reliability can be further improved.
　（第６実施形態）
　第６実施形態について説明する。本実施形態は、第１実施形態に対し、端子部２２の他面２２２の一部に高温はんだを介して中間リードフレームを配置したものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (Sixth Embodiment)
The sixth embodiment will be described. In this embodiment, an intermediate lead frame is arranged on a part of the other surface 222 of the terminal portion 22 via high temperature solder as compared with the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体パッケージ１０は、図１６に示されるように、リードフレーム２０には、高温はんだ２０３を介して、中間リードフレーム２４が配置されている。具体的には、中間リードフレーム２４は、互いに分離された中間アイランド部２５および中間端子部２６を有している。 In the semiconductor package 10 of the present embodiment, as shown in FIG. 16, an intermediate lead frame 24 is arranged on the lead frame 20 via the high temperature solder 203. Specifically, the intermediate lead frame 24 has an intermediate island portion 25 and an intermediate terminal portion 26 separated from each other.
　なお、中間リードフレーム２４は、リードフレーム２０と同様に、例えば、銅等の金属材料を用いて構成される１枚の金属板がプレス打ち抜き等されることによって形成されている。中間アイランド部２５は、アイランド部２１に対応する形状とされ、中間端子部２６は、端子部２２に対応する形状とされている。 The intermediate lead frame 24 is formed by, for example, pressing and punching a single metal plate made of a metal material such as copper, like the lead frame 20. The intermediate island portion 25 has a shape corresponding to the island portion 21, and the intermediate terminal portion 26 has a shape corresponding to the terminal portion 22.
　そして、中間アイランド部２５は、アイランド部２１の他面２１２に高温はんだ２０３を介して配置されている。中間端子部２６は、端子部２２の他面２２２に高温はんだ２０３を介して配置されている。 Then, the intermediate island portion 25 is arranged on the other surface 212 of the island portion 21 via the high temperature solder 203. The intermediate terminal portion 26 is arranged on the other surface 222 of the terminal portion 22 via the high temperature solder 203.
　なお、高温はんだ２０３は、半導体パッケージ１０とプリント基板１００との間に配置されるはんだ２００よりも融点が高い材料で構成されている。より詳しくは、高温はんだ２０３は、はんだ２００をリフローする際に溶融しない温度に融点を有するはんだで構成され、例えば、約２６０℃に融点を有するスズ鉛はんだやアンチモンはんだ等が用いられる。また、本実施形態では、中間アイランド部２５および中間端子部２６が中間部材に相当しており、中間アイランド部２５、中間端子部２６、および高温はんだ２０３が保持構造に相当している。 The high temperature solder 203 is made of a material having a melting point higher than that of the solder 200 arranged between the semiconductor package 10 and the printed circuit board 100. More specifically, the high temperature solder 203 is composed of solder having a melting point at a temperature at which it does not melt when the solder 200 is reflowed, and for example, tin lead solder or antimony solder having a melting point at about 260 ° C. is used. Further, in the present embodiment, the intermediate island portion 25 and the intermediate terminal portion 26 correspond to the intermediate members, and the intermediate island portion 25, the intermediate terminal portion 26, and the high temperature solder 203 correspond to the holding structure.
　以上が本実施形態における半導体パッケージ１０の構成である。そして、半導体パッケージ１０は、図１７に示されるように、中間アイランド部２５が第１ランド１１１とはんだ２００を介して接続され、中間端子部２６が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。この場合、半導体パッケージ１０とプリント基板１００との間に配置されるはんだの総量が多く（すなわち、厚さが厚く）なり、はんだの厚さを厚くできる。 The above is the configuration of the semiconductor package 10 in this embodiment. Then, as shown in FIG. 17, in the semiconductor package 10, the intermediate island portion 25 is connected to the first land 111 via the solder 200, and the intermediate terminal portion 26 is connected to the second land 112 via the solder 200. As such, it is arranged on one side 101 of the printed circuit board 100. In this case, the total amount of solder arranged between the semiconductor package 10 and the printed circuit board 100 is large (that is, the thickness is thick), and the thickness of the solder can be increased.
　以上説明したように、本実施形態では、半導体パッケージ１０には、アイランド部２１の他面２１２および端子部２２の他面２２２に高温はんだ２０３が配置されている。このため、半導体パッケージ１０とプリント基板１００との間に配置されるはんだの総量が多くなり、はんだの信頼性の向上を図ることができる。 As described above, in the present embodiment, the high temperature solder 203 is arranged on the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 in the semiconductor package 10. Therefore, the total amount of solder arranged between the semiconductor package 10 and the printed circuit board 100 is increased, and the reliability of the solder can be improved.
　また、本実施形態では、高温はんだ２０３が応力緩和部としても機能するため、半導体パッケージ１０とプリント基板１００との熱膨張係数差による応力がはんだ２００に印加されることを抑制できる。このため、さらにはんだ２００の信頼性の向上を図ることができる。 Further, in the present embodiment, since the high temperature solder 203 also functions as a stress relaxation unit, it is possible to suppress the application of stress due to the difference in thermal expansion coefficient between the semiconductor package 10 and the printed circuit board 100 to the solder 200. Therefore, the reliability of the solder 200 can be further improved.
　（第６実施形態の変形例）
　第６実施形態の変形例について説明する。高温はんだ２０３は、アイランド部２１および端子部２２の一方に備えられるようにしてもよい。例えば、アイランド部２１のみに高温はんだ２０３を介して中間アイランド部２５を配置し、端子部２２は、第２ランド１１２とはんだ２００を介して接続されるようにしてもよい。 (Modified example of the sixth embodiment)
A modified example of the sixth embodiment will be described. The high temperature solder 203 may be provided on one of the island portion 21 and the terminal portion 22. For example, the intermediate island portion 25 may be arranged only on the island portion 21 via the high temperature solder 203, and the terminal portion 22 may be connected to the second land 112 via the solder 200.
　（第７実施形態）
　第７実施形態について説明する。本実施形態は、第１実施形態に対し、端子部２２の他面２２２に窪み部を形成したものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (7th Embodiment)
A seventh embodiment will be described. In this embodiment, a recess is formed on the other surface 222 of the terminal portion 22 as compared with the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体パッケージ１０は、図１８に示されるように、端子部２２は、他面２２２に窪み部２２２ｂが形成されている。なお、この窪み部２２２ｂは、例えば、モールド樹脂６０を成形した後、端子部２２の他面２２２にエッチング等を行うことによって形成される。また、本実施形態では、窪み部２２２ｂが保持構造に相当している。 In the semiconductor package 10 of the present embodiment, as shown in FIG. 18, the terminal portion 22 has a recessed portion 222b formed on the other surface 222. The recessed portion 222b is formed, for example, by molding the mold resin 60 and then etching the other surface 222 of the terminal portion 22. Further, in the present embodiment, the recessed portion 222b corresponds to the holding structure.
　以上が本実施形態における半導体パッケージ１０の構成である。そして、半導体パッケージ１０は、図１９に示されるように、端子部２２の窪み部２２２ｂ内にはんだ２００が入り込んだ状態でプリント基板１００の一面１０１上に配置されている。 The above is the configuration of the semiconductor package 10 in this embodiment. Then, as shown in FIG. 19, the semiconductor package 10 is arranged on one surface 101 of the printed circuit board 100 with the solder 200 in the recessed portion 222b of the terminal portion 22.
　以上説明したように、本実施形態では、端子部２２の他面２２２に窪み部２２２ｂが形成されている。そして、半導体装置では、はんだ２００が窪み部２２２ｂ内に入り込んだ状態となっている。このため、半導体パッケージ１０とプリント基板１００との間に配置されるはんだ２００は、窪み部２２２ｂ内に入り込んだ分だけ厚くなる。したがって、はんだ２００の信頼性の向上を図ることができる。 As described above, in the present embodiment, the recessed portion 222b is formed on the other surface 222 of the terminal portion 22. Then, in the semiconductor device, the solder 200 is in a state of entering the recessed portion 222b. Therefore, the solder 200 arranged between the semiconductor package 10 and the printed circuit board 100 becomes thicker by the amount of the solder 200 entering the recessed portion 222b. Therefore, the reliability of the solder 200 can be improved.
　（第７実施形態の変形例）
　第７実施形態の変形例について説明する。窪み部２２２ｂは、アイランド部２１にも形成されていてもよいし、アイランド部２１のみに形成されていてもよい。 (Modified example of the seventh embodiment)
A modified example of the seventh embodiment will be described. The recessed portion 222b may be formed in the island portion 21 as well, or may be formed only in the island portion 21.
　（第８実施形態）
　第８実施形態について説明する。本実施形態は、第１実施形態に対し、端子部２２を薄くしたものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (8th Embodiment)
An eighth embodiment will be described. In this embodiment, the terminal portion 22 is thinner than that in the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体パッケージ１０は、図２０に示されるように、端子部２２は、他面２２２側から薄くされることでアイランド部２１より薄くされている。つまり、端子部２２は、他面２２２がアイランド部２１の他面２１２よりも凹んだ状態となっている。すなわち、本実施形態では、端子部２２は、他面２２２がモールド樹脂６０の他面６２およびアイランド部２１の他面２１２よりも、モールド樹脂６０の一面６１側に位置した状態となっている。なお、本実施形態では、端子部２２の他面２２２がアイランド部２１の他面２１２よりもモールド樹脂６０の一面６１側に位置する構造が保持構造に相当する。 In the semiconductor package 10 of the present embodiment, as shown in FIG. 20, the terminal portion 22 is made thinner than the island portion 21 by being made thinner from the other surface 222 side. That is, the terminal portion 22 has the other surface 222 recessed from the other surface 212 of the island portion 21. That is, in the present embodiment, the other surface 222 of the terminal portion 22 is located closer to one surface 61 of the mold resin 60 than the other surface 62 of the mold resin 60 and the other surface 212 of the island portion 21. In the present embodiment, the structure in which the other surface 222 of the terminal portion 22 is located on the one surface 61 side of the mold resin 60 with respect to the other surface 212 of the island portion 21 corresponds to the holding structure.
　なお、このような半導体パッケージ１０は、モールド樹脂６０を成形した後、エッチング等によって端子部２２を他面２２２側から薄くすることで形成される。 Note that such a semiconductor package 10 is formed by molding the mold resin 60 and then thinning the terminal portion 22 from the other surface 222 side by etching or the like.
　以上が本実施形態における半導体パッケージ１０の構成である。そして、半導体パッケージ１０は、図２１に示されるように、アイランド部２１が第１ランド１１１とはんだ２００を介して接続され、端子部２２が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。この場合、端子部２２と第２ランド１１２との間のはんだ２００は、アイランド部２１と第１ランド１１１との間のはんだ２００よりも厚くなる。このため、端子部２２と第２ランド１１２との間のはんだ２００を厚くできる。 The above is the configuration of the semiconductor package 10 in this embodiment. Then, as shown in FIG. 21, the semiconductor package 10 is connected so that the island portion 21 is connected to the first land 111 via the solder 200 and the terminal portion 22 is connected to the second land 112 via the solder 200. Is arranged on one side 101 of the printed circuit board 100. In this case, the solder 200 between the terminal portion 22 and the second land 112 is thicker than the solder 200 between the island portion 21 and the first land 111. Therefore, the solder 200 between the terminal portion 22 and the second land 112 can be thickened.
　以上説明したように、本実施形態では、端子部２２は、他面２２２がアイランド部２１の他面２１２よりもモールド樹脂６０の一面６１側に位置している。このため、端子部２２と他面２１２とアイランド部２１の他面２１２とが同一平面上に位置する場合と比較して、端子部２２と第２ランド１１２との間に配置されるはんだ２００を厚くできる。したがって、はんだ２００の信頼性の向上を図ることができる。 As described above, in the present embodiment, the other surface 222 of the terminal portion 22 is located on one surface 61 side of the mold resin 60 with respect to the other surface 212 of the island portion 21. Therefore, the solder 200 arranged between the terminal portion 22 and the second land 112 is compared with the case where the terminal portion 22, the other surface 212, and the other surface 212 of the island portion 21 are located on the same plane. Can be thickened. Therefore, the reliability of the solder 200 can be improved.
　（第８実施形態の変形例）
　第８実施形態の変形例について説明する。上記第８実施形態において、端子部２２ではなく、アイランド部２１を薄くするようにしてもよい。さらに、アイランド部２１および端子部２２は、例えば、端子部２２の他面２２２がアイランド部２１の他面２１２よりもモールド樹脂６０の一面６１側に位置するのであれば、同じ厚さとされていてもよい。 (Modified example of the eighth embodiment)
A modified example of the eighth embodiment will be described. In the eighth embodiment, the island portion 21 may be made thinner instead of the terminal portion 22. Further, the island portion 21 and the terminal portion 22 have the same thickness, for example, if the other surface 222 of the terminal portion 22 is located on the one surface 61 side of the mold resin 60 with respect to the other surface 212 of the island portion 21. May be good.
　（第９実施形態）
　第９実施形態について説明する。本実施形態は、第１実施形態に対し、端子部２２は、他面２２２と露出側面２２３ａとが分離した状態となるようにしたものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (9th Embodiment)
A ninth embodiment will be described. In the present embodiment, the terminal portion 22 is in a state where the other surface 222 and the exposed side surface 223a are separated from each other as compared with the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体パッケージ１０は、図２２に示されるように、端子部２２は、他面２２２および露出側面２２３ａの連結部分を除去する凹部２２４が形成されている。そして、当該凹部２２４には、モールド樹脂６０が配置されている。 As shown in FIG. 22, in the semiconductor package 10 of the present embodiment, the terminal portion 22 is formed with a recess 224 for removing the connecting portion between the other surface 222 and the exposed side surface 223a. Then, the mold resin 60 is arranged in the recess 224.
　つまり、端子部２２の露出側面２２３ａは、モールド樹脂６０の側面６３のうちの他面６２との境界部分と異なる部分から露出した状態となっている。すなわち、端子部２２は、他面２２２と露出側面２２３ａとが分離した状態となっている。なお、本実施形態では、他面２２２と露出側面２２３ａとが分離した構造が保持構造に相当する。 That is, the exposed side surface 223a of the terminal portion 22 is exposed from a portion of the side surface 63 of the mold resin 60 that is different from the boundary portion with the other surface 62. That is, the terminal portion 22 is in a state in which the other surface 222 and the exposed side surface 223a are separated. In this embodiment, the structure in which the other surface 222 and the exposed side surface 223a are separated corresponds to the holding structure.
　以上が本実施形態における半導体パッケージ１０の構成である。そして、半導体パッケージ１０は、図２３に示されるように、アイランド部２１が第１ランド１１１とはんだ２００を介して接続され、端子部２２が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。この場合、端子部２２は、他面２２２と露出側面２２３ａとが分離した状態となっているため、はんだ２００が他面２２２から露出側面２２３ａ側に這い上がることを抑制できる。したがって、はんだ２００の厚さが薄くなることを抑制できる。 The above is the configuration of the semiconductor package 10 in this embodiment. Then, as shown in FIG. 23, in the semiconductor package 10, the island portion 21 is connected to the first land 111 via the solder 200, and the terminal portion 22 is connected to the second land 112 via the solder 200. Is arranged on one side 101 of the printed circuit board 100. In this case, since the other surface 222 and the exposed side surface 223a are separated from each other in the terminal portion 22, it is possible to prevent the solder 200 from creeping up from the other surface 222 to the exposed side surface 223a. Therefore, it is possible to prevent the solder 200 from becoming thin.
　次に、本実施形態の半導体パッケージ１０の製造方法について説明する。 Next, the manufacturing method of the semiconductor package 10 of the present embodiment will be described.
　例えば、モールド樹脂６０を成形する前に、端子部２２の他面２２２に凹部２２４を形成する。その後、モールド樹脂６０を成形する際、凹部２２４にもモールド樹脂６０が配置されるようにすることにより、端子部２２の他面２２２と露出側面２２３ａとが分離した半導体パッケージ１０が製造される。 For example, before molding the mold resin 60, a recess 224 is formed on the other surface 222 of the terminal portion 22. After that, when the mold resin 60 is molded, the mold resin 60 is also arranged in the recess 224, so that the semiconductor package 10 in which the other surface 222 of the terminal portion 22 and the exposed side surface 223a are separated is manufactured.
　また、例えば、図２４Ａに示されるように、隣合う半導体パッケージ１０の端子部２２を構成する部分がダイシングラインＤＬを介して接続された状態のリードフレーム２０を用意する。そして、端子部２２の他面２２２側の部分において、ダイシングラインＤＬとなる部分を含むように仮凹部２２４ａを形成する。なお、この仮凹部２２４ａは、開口部の幅がダイシングラインＤＬよりも広くなるようにする。 Further, for example, as shown in FIG. 24A, a lead frame 20 is prepared in a state where the portions constituting the terminal portions 22 of the adjacent semiconductor packages 10 are connected via the dicing line DL. Then, a temporary recess 224a is formed on the other surface 222 side of the terminal portion 22 so as to include a portion serving as a dicing line DL. The width of the opening of the temporary recess 224a is made wider than that of the dicing line DL.
　次に、モールド樹脂６０を成形する際、仮凹部２２４ａにも樹脂が入り込むようにする。続いて、図２４Ｂに示されるように、ダイシングラインＤＬに沿って切断することにより、半導体パッケージ１０が製造される。この際、仮凹部２２４ａは、開口部の幅がダイシングラインＤＬよりも広くされているため、切断された際、他面２２２と露出側面２２３ａとの間が分離された状態となる。 Next, when molding the mold resin 60, the resin is also allowed to enter the temporary recess 224a. Subsequently, as shown in FIG. 24B, the semiconductor package 10 is manufactured by cutting along the dicing line DL. At this time, since the width of the opening of the temporary recess 224a is wider than that of the dicing line DL, when the temporary recess 224a is cut, the other surface 222 and the exposed side surface 223a are separated from each other.
　以上説明したように、本実施形態では、端子部２２は、他面２２２と露出側面２２３ａとが分離された状態とされている。このため、はんだ２００が他面２２２から露出側面２２３ａ側に這い上がることを抑制できる。したがって、はんだ２００の厚さが薄くなることを抑制でき、はんだ２００の信頼性の向上を図ることができる。 As described above, in the present embodiment, the terminal portion 22 is in a state in which the other surface 222 and the exposed side surface 223a are separated. Therefore, it is possible to prevent the solder 200 from creeping up from the other surface 222 to the exposed side surface 223a. Therefore, it is possible to prevent the thickness of the solder 200 from becoming thin, and it is possible to improve the reliability of the solder 200.
　（第１０実施形態）
　第１０実施形態について説明する。本実施形態は、第１実施形態に対し、端子部２２の露出側面２２３ａにはんだ濡れ性の低い阻害膜を形成したものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (10th Embodiment)
The tenth embodiment will be described. In this embodiment, an inhibitory film having low solder wettability is formed on the exposed side surface 223a of the terminal portion 22 as compared with the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体パッケージ１０は、図２５に示されるように、端子部２２の露出側面２２３ａに阻害膜９０が形成されている。阻害膜９０は、端子部２２よりもはんだ濡れ性が低い膜で構成されており、例えば、酸化膜で形成される。なお、この阻害膜９０は、例えば、露出側面２２３ａにレーザビームを照射して窪み部２２３ｂが形成されるようにすることによって窪み部２２３ｂの周囲に形成される。なお、本実施形態では、阻害膜９０が保持構造に相当する。 In the semiconductor package 10 of the present embodiment, as shown in FIG. 25, an inhibitory film 90 is formed on the exposed side surface 223a of the terminal portion 22. The inhibitory film 90 is made of a film having a lower solder wettability than the terminal portion 22, and is formed of, for example, an oxide film. The inhibitory film 90 is formed around the recessed portion 223b by, for example, irradiating the exposed side surface 223a with a laser beam so that the recessed portion 223b is formed. In this embodiment, the inhibitory membrane 90 corresponds to the holding structure.
　以上が本実施形態における半導体パッケージ１０の構成である。そして、半導体パッケージ１０は、図２６に示されるように、アイランド部２１が第１ランド１１１とはんだ２００を介して接続され、端子部２２が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。この場合、端子部２２の露出側面２２３ａに阻害膜９０が形成されているため、はんだ２００が他面２２２から露出側面２２３ａ側に這い上がることを抑制できる。したがって、はんだ２００の厚さが薄くなることを抑制できる。 The above is the configuration of the semiconductor package 10 in this embodiment. Then, as shown in FIG. 26, in the semiconductor package 10, the island portion 21 is connected to the first land 111 via the solder 200, and the terminal portion 22 is connected to the second land 112 via the solder 200. Is arranged on one side 101 of the printed circuit board 100. In this case, since the inhibitory film 90 is formed on the exposed side surface 223a of the terminal portion 22, it is possible to prevent the solder 200 from creeping up from the other surface 222 to the exposed side surface 223a. Therefore, it is possible to prevent the solder 200 from becoming thin.
　以上説明したように、本実施形態では、端子部２２の露出側面２２３ａに阻害膜９０が形成されている。このため、はんだ２００が他面２２２から露出側面２２３ａ側に這い上がることを抑制できる。したがって、はんだ２００の厚さが薄くなることを抑制でき、はんだ２００の信頼性の向上を図ることができる。 As described above, in the present embodiment, the inhibitory film 90 is formed on the exposed side surface 223a of the terminal portion 22. Therefore, it is possible to prevent the solder 200 from creeping up from the other surface 222 to the exposed side surface 223a. Therefore, it is possible to prevent the thickness of the solder 200 from becoming thin, and it is possible to improve the reliability of the solder 200.
　（第１１実施形態）
　第１１実施形態について説明する。本実施形態は、第１実施形態に対し、半導体チップ３０上に放熱部材を配置したものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (11th Embodiment)
The eleventh embodiment will be described. In this embodiment, the heat radiating member is arranged on the semiconductor chip 30 as compared with the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体パッケージ１０は、図２７に示されるように、半導体チップ３０の一面３０ａ側に半導体チップ３０と熱的に接続される放熱部材３１が配置されている。そして、放熱部材３１は、半導体チップ３０等と共にモールド樹脂６０で封止されている。なお、放熱部材３１は、モールド樹脂６０よりも熱伝導率の高い材料で構成され、例えば、銅で構成される。 In the semiconductor package 10 of the present embodiment, as shown in FIG. 27, a heat radiating member 31 thermally connected to the semiconductor chip 30 is arranged on one side 30a side of the semiconductor chip 30. The heat radiating member 31 is sealed with the mold resin 60 together with the semiconductor chip 30 and the like. The heat radiating member 31 is made of a material having a higher thermal conductivity than the mold resin 60, and is made of, for example, copper.
　また、半導体パッケージ１０は、厚さ方向の中心を通り、アイランド部２１の面方向に沿った仮想線Ｋに対し、一方の領域にリードフレーム２０が配置され、他方の領域に放熱部材３１が主に配置されるようにしている。なお、他方の領域に放熱部材３１が主に配置されるとは、放熱部材３１の全体積における５０％以上が他方の領域に位置することを意味している。 Further, in the semiconductor package 10, the lead frame 20 is arranged in one region and the heat radiating member 31 is mainly in the other region with respect to the virtual line K that passes through the center in the thickness direction and is along the plane direction of the island portion 21. It is designed to be placed in. The fact that the heat radiating member 31 is mainly arranged in the other region means that 50% or more of the total product of the heat radiating member 31 is located in the other region.
　そして、放熱部材３１は、半導体チップ３０と接続されると共に、端子部２２とも接続されるように配置されている。なお、本実施形態では、放熱部材３１は、リードフレーム２０と同じ材料で構成され、銅で構成されている。 The heat radiating member 31 is arranged so as to be connected to the semiconductor chip 30 and also to the terminal portion 22. In the present embodiment, the heat radiating member 31 is made of the same material as the lead frame 20 and is made of copper.
　以上が本実施形態における半導体パッケージ１０の構成である。そして、半導体パッケージ１０は、図２８に示されるように、アイランド部２１が第１ランド１１１とはんだ２００を介して接続され、端子部２２が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。 The above is the configuration of the semiconductor package 10 in this embodiment. Then, as shown in FIG. 28, in the semiconductor package 10, the island portion 21 is connected to the first land 111 via the solder 200, and the terminal portion 22 is connected to the second land 112 via the solder 200. Is arranged on one side 101 of the printed circuit board 100.
　以上説明したように、本実施形態では、半導体チップ３０の一面３０ａ側に放熱部材３１が配置されている。このため、半導体チップ３０から放熱部材３１を介して放熱し易くなり、はんだ２００に印加される応力を低減できる。したがって、はんだ２００が破壊されることを抑制でき、はんだ２００の信頼性の向上を図ることができる。 As described above, in the present embodiment, the heat radiating member 31 is arranged on the one side 30a side of the semiconductor chip 30. Therefore, heat is easily dissipated from the semiconductor chip 30 via the heat radiating member 31, and the stress applied to the solder 200 can be reduced. Therefore, it is possible to suppress the destruction of the solder 200 and improve the reliability of the solder 200.
　また、本実施形態では、放熱部材３１は、リードフレーム２０と同じ材料で構成されている。そして、半導体パッケージ１０は、仮想線Ｋに対し、一方の領域にリードフレーム２０が配置され、他方の領域に放熱部材３１が主に配置されるようにしている。このため、熱によって半導体パッケージ１０が反ることも抑制でき、さらにはんだ２００に印加される応力を低減できる。 Further, in the present embodiment, the heat radiating member 31 is made of the same material as the lead frame 20. Then, in the semiconductor package 10, the lead frame 20 is arranged in one region and the heat radiating member 31 is mainly arranged in the other region with respect to the virtual line K. Therefore, it is possible to suppress the warping of the semiconductor package 10 due to heat, and further reduce the stress applied to the solder 200.
　さらに、本実施形態では、放熱部材３１は、端子部２２と接続されている。このため、放熱部材３１を接続部材としての機能も発揮させることができる。 Further, in the present embodiment, the heat radiating member 31 is connected to the terminal portion 22. Therefore, the heat radiating member 31 can also function as a connecting member.
　（第１１実施形態の変形例）
　第１１実施形態の変形例について説明する。放熱部材３１は、端子部２２と電気的に接続されていなくてもよい。つまり、半導体チップ３０と端子部２２との接続は、ボンディングワイヤ５０で行うようにしてもよい。また、半導体チップ３０と複数の端子部２２とを接続する場合には、一部の接続を放熱部材３１で行い、残りの接続をボンディングワイヤ５０で行うようにしてもよい。 (Modified example of the eleventh embodiment)
A modified example of the eleventh embodiment will be described. The heat radiating member 31 does not have to be electrically connected to the terminal portion 22. That is, the semiconductor chip 30 and the terminal portion 22 may be connected by the bonding wire 50. Further, when connecting the semiconductor chip 30 and the plurality of terminal portions 22, a part of the connection may be made by the heat radiating member 31, and the remaining connection may be made by the bonding wire 50.
　（第１２実施形態）
　第１２実施形態について説明する。本実施形態は、第１実施形態に対し、アイランド部２１と端子部２２の配置を変更したものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (12th Embodiment)
A twelfth embodiment will be described. In this embodiment, the arrangement of the island portion 21 and the terminal portion 22 is changed from that of the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体パッケージ１０は、図２９に示されるように、端子部２２は、他面２２２がモールド樹脂６０の他面６２から露出するように配置されている。一方、アイランド部２１は、他面２１２がモールド樹脂６０の一面６１から露出するように配置されている。つまり、アイランド部２１と端子部２２とは、モールド樹脂６０の異なる面から露出するように配置されている。 In the semiconductor package 10 of the present embodiment, as shown in FIG. 29, the terminal portion 22 is arranged so that the other surface 222 is exposed from the other surface 62 of the mold resin 60. On the other hand, the island portion 21 is arranged so that the other surface 212 is exposed from one surface 61 of the mold resin 60. That is, the island portion 21 and the terminal portion 22 are arranged so as to be exposed from different surfaces of the mold resin 60.
　なお、端子部２２は、一面２２１に半導体チップ３０側に延びる延設部２２１ａが備えられている。そして、半導体チップ３０は、延設部２２１ａとボンディングワイヤ５０を介して接続されている。 The terminal portion 22 is provided with an extension portion 221a extending toward the semiconductor chip 30 on one side 221. The semiconductor chip 30 is connected to the extension portion 221a via the bonding wire 50.
　以上が本実施形態における半導体パッケージ１０の構成である。そして、半導体パッケージ１０は、図３０に示されるように、端子部２２が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。また、半導体パッケージ１０は、筐体３００とアイランド部２１とがはんだ２００を介して接続されている。なお、筐体３００は、例えば、金属等で構成される。 The above is the configuration of the semiconductor package 10 in this embodiment. Then, as shown in FIG. 30, the semiconductor package 10 is arranged on one side 101 of the printed circuit board 100 so that the terminal portion 22 is connected to the second land 112 via the solder 200. Further, in the semiconductor package 10, the housing 300 and the island portion 21 are connected via the solder 200. The housing 300 is made of, for example, metal or the like.
　以上説明したように、本実施形態では、アイランド部２１と端子部２２とがモールド樹脂６０の異なる面から露出している。つまり、アイランド部２１と端子部２２とを異なる部材に接続できるようにしている。そして、本実施形態では、半導体パッケージ１０は、アイランド部２１が筐体３００と接続されると共に、端子部２２がプリント基板１００と接続されるようにしている。このため、アイランド部２１から筐体３００へ放熱できるため、半導体パッケージ１０からはんだ２００に印加される応力を低減できる。したがって、はんだ２００が破壊されることを抑制でき、はんだ２００の信頼性の向上を図ることができる。 As described above, in the present embodiment, the island portion 21 and the terminal portion 22 are exposed from different surfaces of the mold resin 60. That is, the island portion 21 and the terminal portion 22 can be connected to different members. In the present embodiment, the semiconductor package 10 is such that the island portion 21 is connected to the housing 300 and the terminal portion 22 is connected to the printed circuit board 100. Therefore, since heat can be dissipated from the island portion 21 to the housing 300, the stress applied to the solder 200 from the semiconductor package 10 can be reduced. Therefore, it is possible to suppress the destruction of the solder 200 and improve the reliability of the solder 200.
　（第１３実施形態）
　第１３実施形態について説明する。本実施形態は、第１２実施形態に対し、半導体チップ３０を端子部２２にフリップチップ実装したものである。その他に関しては、上記第１２実施形態と同様であるため、ここでは説明を省略する。 (13th Embodiment)
The thirteenth embodiment will be described. In this embodiment, the semiconductor chip 30 is flip-chip mounted on the terminal portion 22 with respect to the twelfth embodiment. Others are the same as those in the twelfth embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体パッケージ１０は、図３１に示されるように、モールド樹脂６０の他面６２側に複数の端子部２２が並べて配置されている。なお、端子部２２は、他面２２２がモールド樹脂６０の他面６２から露出している。 In the semiconductor package 10 of the present embodiment, as shown in FIG. 31, a plurality of terminal portions 22 are arranged side by side on the other surface 62 side of the mold resin 60. The other surface 222 of the terminal portion 22 is exposed from the other surface 62 of the mold resin 60.
　そして、半導体チップ３０は、一面３０ａ側が端子部２２にはんだ３２を介して接続されている。つまり、半導体チップ３０は、端子部２２に対してフリップチップ実装されている。 Then, the semiconductor chip 30 is connected to the terminal portion 22 on the one side 30a side via the solder 32. That is, the semiconductor chip 30 is flip-chip mounted on the terminal portion 22.
　また、アイランド部２１は、他面２１２がモールド樹脂６０の一面６１から露出するように配置されている。そして、アイランド部２１は、半導体チップ３０の他面３０ｂと接合部材４０を介して接合されている。 Further, the island portion 21 is arranged so that the other surface 212 is exposed from one surface 61 of the mold resin 60. The island portion 21 is joined to the other surface 30b of the semiconductor chip 30 via the joining member 40.
　以上が本実施形態における半導体パッケージ１０の構成である。そして、半導体パッケージ１０は、図３２に示されるように、端子部２２が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。また、半導体パッケージ１０は、筐体３００とアイランド部２１とがはんだ２００を介して接続されている。 The above is the configuration of the semiconductor package 10 in this embodiment. Then, as shown in FIG. 32, the semiconductor package 10 is arranged on one side 101 of the printed circuit board 100 so that the terminal portion 22 is connected to the second land 112 via the solder 200. Further, in the semiconductor package 10, the housing 300 and the island portion 21 are connected via the solder 200.
　以上説明したように、半導体チップ３０を端子部２２にフリップチップ実装するようにしても、上記第１２実施形態と同様の効果を得ることができる。 As described above, even if the semiconductor chip 30 is flip-chip mounted on the terminal portion 22, the same effect as that of the twelfth embodiment can be obtained.
　（第１３実施形態の変形例）
　上記第１３実施形態の変形例について説明する。上記第１３実施形態において、複数の端子部２２のうちの一部の端子部２２上にリードフレーム等の別の導電性部材を積層すると共に、当該導電性部材がモールド樹脂６０の一面６１から露出するようにしてもよい。そして、モールド樹脂６０の一面６１から露出する導電性部材がモールド樹脂６０の一面６１側に配置される電子部品と電気的に接続されるようにし、当該導電性部材と電気的に接続される端子部２２は、プリント基板１００とはんだ２００を介して接続されないようにしてもよい。つまり、一部の端子部２２は、モールド樹脂６０の一面６１側に配置される電子部品と半導体チップ３０とを接続する配線として機能するようにしてもよい。これによれば、配線の自由度の向上を図ることができる。 (Modified example of the thirteenth embodiment)
A modified example of the thirteenth embodiment will be described. In the thirteenth embodiment, another conductive member such as a lead frame is laminated on a part of the terminal portions 22 among the plurality of terminal portions 22, and the conductive member is exposed from one surface 61 of the mold resin 60. You may try to do it. Then, the conductive member exposed from one side 61 of the mold resin 60 is electrically connected to the electronic component arranged on the one side 61 side of the mold resin 60, and the terminal is electrically connected to the conductive member. The portion 22 may not be connected to the printed circuit board 100 via the solder 200. That is, a part of the terminal portions 22 may function as wiring for connecting the electronic components arranged on the one side 61 side of the mold resin 60 and the semiconductor chip 30. According to this, the degree of freedom of wiring can be improved.
　（第１４実施形態）
　第１４実施形態について説明する。本実施形態は、第１実施形態に対し、半導体パッケージ１０とプリント基板１００との間に電子部品を配置したものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (14th Embodiment)
The 14th embodiment will be described. In this embodiment, electronic components are arranged between the semiconductor package 10 and the printed circuit board 100 with respect to the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体装置は、図３３に示されるように、半導体パッケージ１０とプリント基板１００との間に電子部品４００が配置されている。なお、図３３は、図２中のXXXII－XXXII線に沿った断面図である。 In the semiconductor device of this embodiment, as shown in FIG. 33, an electronic component 400 is arranged between the semiconductor package 10 and the printed circuit board 100. 33 is a cross-sectional view taken along the line XXXII-XXXII in FIG.
　本実施形態では、電子部品４００は、一対の電極４０１を有するチップコンデンサとされている。そして、電子部品４００は、一方の電極４０１が、隣合う端子部２２の一方、およびこの端子部２２と対向する第２ランド１１２と接続されるように、はんだ２００を介してプリント基板１００の一面１０１上に配置されている。また、電子部品４００は、他方の電極４０１が、隣合う端子部２２の他方、およびこの端子部２２と対向する第２ランド１１２と接続されるように、はんだ２００を介してプリント基板１００の一面１０１上に配置されている。 In the present embodiment, the electronic component 400 is a chip capacitor having a pair of electrodes 401. Then, in the electronic component 400, one surface of the printed circuit board 100 is connected via the solder 200 so that one electrode 401 is connected to one of the adjacent terminal portions 22 and the second land 112 facing the terminal portion 22. It is arranged on 101. Further, in the electronic component 400, one surface of the printed circuit board 100 is connected via the solder 200 so that the other electrode 401 is connected to the other of the adjacent terminal portions 22 and the second land 112 facing the terminal portion 22. It is arranged on 101.
　以上説明したように、本実施形態では、半導体パッケージ１０とプリント基板１００との間に電子部品４００が配置されている。つまり、半導体パッケージ１０とプリント基板１００との間に、スペーサとしての電子部品４００が配置されている。このため、半導体パッケージ１０とプリント基板１００との間に配置されるはんだ２００の厚さが電子部品４００の厚さより薄くなることを抑制でき、はんだ２００の信頼性の向上を図ることができる。 As described above, in the present embodiment, the electronic component 400 is arranged between the semiconductor package 10 and the printed circuit board 100. That is, the electronic component 400 as a spacer is arranged between the semiconductor package 10 and the printed circuit board 100. Therefore, it is possible to prevent the thickness of the solder 200 arranged between the semiconductor package 10 and the printed circuit board 100 from becoming thinner than the thickness of the electronic component 400, and it is possible to improve the reliability of the solder 200.
　また、半導体パッケージ１０とプリント基板１００との間に電子部品４００を配置することにより、プリント基板１００のうちの半導体パッケージ１０が搭載される部分と異なる部分のスペースを有効活用したり、スペースの削減を図ることができる。 Further, by arranging the electronic component 400 between the semiconductor package 10 and the printed circuit board 100, the space of the portion of the printed circuit board 100 different from the portion on which the semiconductor package 10 is mounted can be effectively utilized or the space can be reduced. Can be planned.
　（第１５実施形態）
　第１５実施形態について説明する。本実施形態は、第１実施形態に対し、第２ランド１１２にスリットを形成したものである。その他に関しては、上記第１実施形態と同様であるため、ここでは説明を省略する。 (15th Embodiment)
The fifteenth embodiment will be described. In this embodiment, a slit is formed in the second land 112 with respect to the first embodiment. Others are the same as those in the first embodiment, and thus the description thereof will be omitted here.
　本実施形態の半導体装置は、図３４および図３５に示されるように、第２ランド１１２にスリット１１２ｂが形成されている。具体的には、スリット１１２ｂは、積層方向において、露出側面２２３ａと重なる部分と異なる部分に形成されている。本実施形態では、スリット１１２ｂは、端子部２２の他面２２２と対向する部分に形成され、第２ランド１１２を２つの領域に分離するように形成されている。 In the semiconductor device of this embodiment, as shown in FIGS. 34 and 35, a slit 112b is formed in the second land 112. Specifically, the slit 112b is formed in a portion different from the portion overlapping the exposed side surface 223a in the stacking direction. In the present embodiment, the slit 112b is formed in a portion facing the other surface 222 of the terminal portion 22, and is formed so as to separate the second land 112 into two regions.
　なお、図３５は、図３４中の紙面左側に位置する第２ランド１１２の平面図である。また、図３５では、積層方向において、第２ランド１１２のうちの露出側面２２３ａと重なる部分を点線で示している。 Note that FIG. 35 is a plan view of the second land 112 located on the left side of the paper surface in FIG. 34. Further, in FIG. 35, a portion of the second land 112 that overlaps the exposed side surface 223a in the stacking direction is shown by a dotted line.
　そして、半導体パッケージ１０は、アイランド部２１が第１ランド１１１とはんだ２００を介して接続され、端子部２２が第２ランド１１２とはんだ２００を介して接続されるように、プリント基板１００の一面１０１上に配置されている。この場合、第２ランド１１２にスリット１１２ｂが形成されているため、プリント基板１００とはんだ２００との間にスリット１１２ｂを含むボイド１３０が形成されている。 Then, in the semiconductor package 10, one side 101 of the printed circuit board 100 is connected so that the island portion 21 is connected to the first land 111 via the solder 200 and the terminal portion 22 is connected to the second land 112 via the solder 200. It is placed on top. In this case, since the slit 112b is formed in the second land 112, a void 130 including the slit 112b is formed between the printed circuit board 100 and the solder 200.
　以上説明したように、本実施形態では、第２ランド１１２にスリット１１２ｂが形成されているため、はんだ２００にクラックが導入された際、クラックの進展が早くなることを抑制できる。すなわち、はんだ２００にクラックが導入される場合、クラックは、はんだ２００と端子部２２の露出側面２２３ａとの境界部分から導入され、露出側面２２３ａに沿って進展し易い。このため、はんだ２００のうちのクラックの進展方向と重なる部分にボイド１３０が存在する場合には、クラックの進展が促進されてはんだ２００の寿命が短くなってしまう。 As described above, in the present embodiment, since the slit 112b is formed in the second land 112, it is possible to prevent the cracks from growing faster when the cracks are introduced into the solder 200. That is, when a crack is introduced into the solder 200, the crack is introduced from the boundary portion between the solder 200 and the exposed side surface 223a of the terminal portion 22, and easily propagates along the exposed side surface 223a. Therefore, when the void 130 is present in the portion of the solder 200 that overlaps the crack growth direction, the crack growth is promoted and the life of the solder 200 is shortened.
　これに対し、本実施形態では、第２ランド１１２には、積層方向において、露出側面２２３ａと重なる部分と異なる部分にスリット１１２ｂが形成されている。そして、はんだ２００とプリント基板１００との間には、積層方向において、露出側面２２３ａと重なる部分と異なる部分にボイド１３０が形成されている。つまり、スリット１１２ｂを形成することにより、積層方向において、露出側面２２３ａと重なる部分と異なる部分に、敢えてスリット１１２ｂを含むボイド１３０が形成されるようにしている。したがって、はんだ２００のうちのクラックの進展方向と重なる部分にボイド１３０が形成されることを抑制できる。これにより、はんだ２００の寿命が短くなることを抑制でき、はんだ２００の信頼性の向上を図ることができる。 On the other hand, in the present embodiment, the second land 112 is formed with a slit 112b in a portion different from the portion overlapping the exposed side surface 223a in the stacking direction. A void 130 is formed between the solder 200 and the printed circuit board 100 in a portion different from the portion overlapping the exposed side surface 223a in the stacking direction. That is, by forming the slit 112b, the void 130 including the slit 112b is intentionally formed in a portion different from the portion overlapping the exposed side surface 223a in the stacking direction. Therefore, it is possible to prevent the void 130 from being formed in the portion of the solder 200 that overlaps the crack growing direction. As a result, it is possible to prevent the life of the solder 200 from being shortened, and it is possible to improve the reliability of the solder 200.
　（第１５実施形態の変形例）
　第１５実施形態の変形例について説明する。第１５実施形態において、スリット１１２ｂの形状は適宜変更可能である。例えば、図３６に示されるように、スリット１１２ｂは、第２ランド１１２を分割させないように形成されていてもよい。なお、図３６は、図３４中の紙面左側に位置する第２ランド１１２の平面図である。また、スリット１１２ｂは、積層方向において、露出側面２２３ａと重なる部分と異なる部分に形成されていれば、端子部２２の他面２２２と対向する部分に形成されていなくてもよい。 (Modified example of the 15th embodiment)
A modified example of the fifteenth embodiment will be described. In the fifteenth embodiment, the shape of the slit 112b can be changed as appropriate. For example, as shown in FIG. 36, the slit 112b may be formed so as not to divide the second land 112. Note that FIG. 36 is a plan view of the second land 112 located on the left side of the paper surface in FIG. 34. Further, the slit 112b may not be formed in a portion facing the other surface 222 of the terminal portion 22 as long as it is formed in a portion different from the portion overlapping the exposed side surface 223a in the stacking direction.
　（他の実施形態）
　本開示は、実施形態に準拠して記述されたが、本開示は当該実施形態や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 (Other embodiments)
Although this disclosure has been described in accordance with embodiments, it is understood that this disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within an equal range. In addition, various combinations and forms, as well as other combinations and forms that include only one element, more, or less, are also within the scope of the present disclosure.
　上記各実施形態において、被実装部材は、プリント基板１００ではなく、セラミック配線基板等であってもよい。 In each of the above embodiments, the mounted member may be a ceramic wiring board or the like instead of the printed circuit board 100.
　また、上記各実施形態を適宜組み合わせることもできる。例えば、上記第２実施形態を適宜各実施形態に組み合わせ、端子部２２に突起部２２２ａを形成してもよい。上記第３実施形態を適宜各実施形態に組み合わせ、端子部２２に阻害膜７０を形成してもよい。上記第４実施形態を適宜各実施形態に組み合わせ、アイランド部２１および端子部２２にメッキ膜８０を形成すると共に阻害膜８１を形成するようにしてもよい。上記第５実施形態を適宜各実施形態に組み合わせ、アイランド部２１および端子部２２に転写はんだ２０２を配置するようにしてもよい。上記第６実施形態を適宜各実施形態に組み合わせ、アイランド部２１および端子部２２に高温はんだ２０３を介して中間リードフレーム２４を配置するようにしてもよい。上記第７実施形態を適宜各実施形態に組み合わせ、端子部２２に窪み部２２２ｂを形成するようにしてもよい。上記第８実施形態を適宜各実施形態に組み合わせ、端子部２２を薄くするようにしてもよい。上記第９実施形態を適宜各実施形態に組み合わせ、端子部２２の他面２２２と露出側面２２３ａとが分離するようにしてもよい。上記第１０実施形態を適宜各実施形態に組み合わせ、端子部２２の露出側面２２３ａに阻害膜９０を形成するようにしてもよい。上記第１１実施形態を適宜各実施形態に組み合わせ、放熱部材３１を配置するようにしてもよい。上記第１２実施形態を適宜各実施形態に組み合わせ、アイランド部２１の他面２１２と端子部２２の他面２２２とをモールド樹脂６０の異なる面から露出させるようにしてもよい。この場合、上記第１３実施形態のように、半導体チップ３０を端子部２２にフリップチップ実装するようにしてもよい。上記第１４実施形態を適宜各実施形態に組み合わせ、半導体パッケージ１０とプリント基板１００との間に電子部品４００を配置するようにしてもよい。上記第１５実施形態を適宜各実施形態に組み合わせ、第２ランド１１２にスリット１１２ｂを形成するようにしてもよい。 Further, each of the above embodiments can be combined as appropriate. For example, the second embodiment may be combined with each embodiment as appropriate to form a protrusion 222a on the terminal portion 22. The inhibitory film 70 may be formed on the terminal portion 22 by appropriately combining the third embodiment with each embodiment. The fourth embodiment may be appropriately combined with each embodiment to form a plating film 80 and an inhibitory film 81 on the island portion 21 and the terminal portion 22. The fifth embodiment may be appropriately combined with each embodiment, and the transfer solder 202 may be arranged on the island portion 21 and the terminal portion 22. The sixth embodiment may be appropriately combined with each embodiment, and the intermediate lead frame 24 may be arranged on the island portion 21 and the terminal portion 22 via the high temperature solder 203. The seventh embodiment may be appropriately combined with each embodiment to form a recessed portion 222b in the terminal portion 22. The eighth embodiment may be combined with each embodiment as appropriate to make the terminal portion 22 thinner. The ninth embodiment may be appropriately combined with each embodiment so that the other surface 222 of the terminal portion 22 and the exposed side surface 223a are separated from each other. The tenth embodiment may be appropriately combined with each embodiment to form an inhibitory film 90 on the exposed side surface 223a of the terminal portion 22. The eleventh embodiment may be combined with each embodiment as appropriate, and the heat radiating member 31 may be arranged. The twelfth embodiment may be appropriately combined with each embodiment so that the other surface 212 of the island portion 21 and the other surface 222 of the terminal portion 22 are exposed from different surfaces of the mold resin 60. In this case, the semiconductor chip 30 may be flip-chip mounted on the terminal portion 22 as in the thirteenth embodiment. The 14th embodiment may be appropriately combined with each embodiment, and the electronic component 400 may be arranged between the semiconductor package 10 and the printed circuit board 100. The fifteenth embodiment may be appropriately combined with each embodiment to form a slit 112b in the second land 112.

Claims (20)

  1. 　被実装部材（１００）にはんだ（２００）を介して配置される半導体パッケージであって、
    　半導体チップ（３０）と、
    　一面（２１１）および前記一面と反対側の他面（２１２）を有し、前記一面に前記半導体チップが配置されるアイランド部（２１）と、
    　一面（２２１）、前記一面と反対側の他面（２２２）、前記一面と前記他面とを繋ぐ側面（２２３）を有し、前記半導体チップと接続部材（５０）を介して接続される端子部（２２）と、
    　一面（６１）、前記一面と反対側の他面（６２）、前記一面と他面とを繋ぐ側面（６３）を有し、前記一面または前記他面から前記アイランド部の他面を露出させ、前記他面から前記端子部の他面を露出させると共に前記側面から前記端子部の側面の一部を露出させ、前記半導体チップを封止するモールド樹脂（６０）と、を備え、
    　少なくとも前記端子部は、前記はんだを介して前記被実装部材と接続されており、
    　前記アイランド部、前記端子部、および前記モールド樹脂の少なくとも１つには、前記はんだを介して前記被実装部材に配置された際、前記はんだの厚さを所定以上の厚さに保持する保持構造（２５、２６、６２ａ、７０、８０、８１、９０、２０２、２０３、２２２ａ、２２２ｂ）が形成されている半導体パッケージ。     A semiconductor package that is placed on the mounted member (100) via solder (200).
    Semiconductor chip (30) and
    An island portion (21) having one surface (211) and another surface (212) on the opposite side to the one surface on which the semiconductor chip is arranged, and
    A terminal having one surface (221), another surface (222) opposite to the one surface, and a side surface (223) connecting the one surface and the other surface, and connected to the semiconductor chip via a connecting member (50). Part (22) and
    It has one surface (61), another surface (62) opposite to the one surface, and a side surface (63) connecting the one surface and the other surface, and exposes the other surface of the island portion from the one surface or the other surface. A mold resin (60) for exposing the other surface of the terminal portion from the other surface and exposing a part of the side surface of the terminal portion from the side surface to seal the semiconductor chip is provided.
    At least the terminal portion is connected to the mounted member via the solder.
    At least one of the island portion, the terminal portion, and the mold resin has a holding structure that holds the thickness of the solder at a predetermined thickness or more when it is arranged on the mounted member via the solder. The semiconductor package in which (25, 26, 62a, 70, 80, 81, 90, 202, 203, 222a, 222b) is formed.
  2. 　前記モールド樹脂の他面には、前記保持構造として、前記端子部の他面よりも突出した凸部（６２ａ）が形成されている請求項１に記載の半導体パッケージ。 The semiconductor package according to claim 1, wherein a convex portion (62a) protruding from the other surface of the terminal portion is formed on the other surface of the mold resin as the holding structure.
  3. 　前記アイランド部は、前記他面が前記モールド樹脂の他面から露出していると共に、前記はんだを介して前記被実装部材と接続されており、
    　前記アイランド部の他面および前記端子部の他面の少なくとも一方には、前記保持構造として、前記モールド樹脂の他面よりも突出した突起部（２２２ａ）が形成されている請求項１または２に記載の半導体パッケージ。     The island portion has the other surface exposed from the other surface of the mold resin and is connected to the mounted member via the solder.
    According to claim 1 or 2, a protrusion (222a) protruding from the other surface of the mold resin is formed as the holding structure on at least one of the other surface of the island portion and the other surface of the terminal portion. The described semiconductor package.
  4. 　前記突起部は、ボンディングワイヤで形成されている請求項３に記載の半導体パッケージ。 The semiconductor package according to claim 3, wherein the protrusion is formed of a bonding wire.
  5. 　前記端子部は、前記側面のうちの前記モールド樹脂から露出する部分を露出側面（２２３ａ）とすると、前記他面のうちの前記露出側面との境界部分に、前記保持構造として、前記端子部よりもはんだ濡れ性の低い阻害膜（７０）が形成されている請求項１または２に記載の半導体パッケージ。 Assuming that the portion of the side surface exposed from the mold resin is the exposed side surface (223a), the terminal portion is formed at the boundary portion between the other surface and the exposed side surface as the holding structure from the terminal portion. The semiconductor package according to claim 1 or 2, wherein an inhibitory film (70) having low solder wettability is formed.
  6. 　前記端子部は、前記他面のうちの外縁部を被覆するように前記阻害膜が形成されており、前記阻害膜から露出する部分にはんだボール（２０１）が配置されている請求項５に記載の半導体パッケージ。 The fifth aspect of the present invention, wherein the inhibitory film is formed on the terminal portion so as to cover the outer edge portion of the other surface, and the solder ball (201) is arranged in the portion exposed from the inhibitory film. Semiconductor package.
  7. 　前記アイランド部は、前記他面が前記モールド樹脂の他面から露出していると共に、前記はんだを介して前記被実装部材と接続されており、
    　前記アイランド部の他面および前記端子部の他面の少なくとも一方は、前記保持構造として、メッキ膜（８０）と、前記メッキ膜よりはんだ濡れ性が低い阻害膜（８１）が形成されている請求項１または２に記載の半導体パッケージ。     The island portion has the other surface exposed from the other surface of the mold resin and is connected to the mounted member via the solder.
    Claim that at least one of the other surface of the island portion and the other surface of the terminal portion is formed with a plating film (80) and an inhibitory film (81) having a lower solder wettability than the plating film as the holding structure. Item 2. The semiconductor package according to Item 1 or 2.
  8. 　前記アイランド部は、前記他面が前記モールド樹脂の他面から露出していると共に、前記はんだを介して前記被実装部材と接続されており、
    　前記アイランド部の他面および前記端子部の他面は、前記保持構造として、前記モールド樹脂の他面から突出しており、突出している部分に転写はんだ（２０２）が配置されている請求項１または２に記載の半導体パッケージ。     The island portion has the other surface exposed from the other surface of the mold resin and is connected to the mounted member via the solder.
    The other surface of the island portion and the other surface of the terminal portion protrude from the other surface of the mold resin as the holding structure, and the transfer solder (202) is arranged in the protruding portion according to claim 1 or 2. The semiconductor package according to 2.
  9. 　前記アイランド部は、前記他面が前記モールド樹脂の他面から露出していると共に、前記はんだを介して前記被実装部材と接続されており、
    　前記アイランド部の他面および前記端子部の他面の少なくとも一方は、前記保持構造として、前記はんだよりも融点が高い材料で構成された高温はんだ（２０３）を介して中間部材（２５、２６）が配置されている請求項１または２に記載の半導体パッケージ。     The island portion has the other surface exposed from the other surface of the mold resin and is connected to the mounted member via the solder.
    At least one of the other surface of the island portion and the other surface of the terminal portion is an intermediate member (25, 26) via a high temperature solder (203) made of a material having a melting point higher than that of the solder as the holding structure. The semiconductor package according to claim 1 or 2, wherein is arranged.
  10. 　前記アイランド部は、前記他面が前記モールド樹脂の他面から露出していると共に、前記はんだを介して前記被実装部材と接続されており、
    　前記アイランド部の他面および前記端子部の他面の少なくとも一方は、前記保持構造として、窪み部（２２２ｂ）が形成されている請求項１または２に記載の半導体パッケージ。     The island portion has the other surface exposed from the other surface of the mold resin and is connected to the mounted member via the solder.
    The semiconductor package according to claim 1 or 2, wherein a recess (222b) is formed as a holding structure on at least one of the other surface of the island portion and the other surface of the terminal portion.
  11. 　前記アイランド部は、前記他面が前記モールド樹脂の他面から露出していると共に、前記はんだを介して前記被実装部材と接続されており、
    　前記アイランド部および前記端子部は、前記保持構造として、一方の前記他面が他方の前記他面よりも前記モールド樹脂の一面側に位置している請求項１または２に記載の半導体パッケージ。     The island portion has the other surface exposed from the other surface of the mold resin and is connected to the mounted member via the solder.
    The semiconductor package according to claim 1 or 2, wherein the island portion and the terminal portion have the holding structure in which one of the other surfaces is located on one surface side of the mold resin with respect to the other surface of the other.
  12. 　前記端子部は、前記側面のうちの前記モールド樹脂から露出する部分を露出側面（２２３ａ）とすると、前記保持構造として、前記露出側面と前記他面とが分離している請求項１または２に記載の半導体パッケージ。 The terminal portion according to claim 1 or 2, wherein the exposed side surface and the other surface are separated as the holding structure, assuming that the portion of the side surface exposed from the mold resin is the exposed side surface (223a). The described semiconductor package.
  13. 　前記端子部は、前記側面のうちの前記モールド樹脂から露出する部分を露出側面（２２３ａ）とすると、前記保持構造として、前記露出側面に前記端子部よりもはんだ濡れ性の低い阻害膜（９０）が形成されている請求項１または２に記載の半導体パッケージ。 Assuming that the portion of the side surface exposed from the mold resin is the exposed side surface (223a), the terminal portion has an inhibitory film (90) having a lower solder wettability on the exposed side surface than the terminal portion as the holding structure. The semiconductor package according to claim 1 or 2, wherein the above is formed.
  14. 　前記半導体チップのうちの前記アイランド部側と反対側には、前記モールド樹脂より熱伝導率が高い材料で構成され、前記半導体チップと熱的に接続されると共に前記モールド樹脂で封止された放熱部材（３１）が配置されている請求項１ないし１３のいずれか１つに記載の半導体パッケージ。 The side of the semiconductor chip opposite to the island portion side is made of a material having a higher thermal conductivity than the mold resin, and is thermally connected to the semiconductor chip and heat-dissipating sealed with the mold resin. The semiconductor package according to any one of claims 1 to 13, wherein the member (31) is arranged.
  15. 　前記アイランド部は、前記他面が前記モールド樹脂の一面から露出している請求項１ないし１４のいずれか１つに記載の半導体パッケージ。 The semiconductor package according to any one of claims 1 to 14, wherein the island portion is the other surface exposed from one surface of the mold resin.
  16. 　被実装部材（１００）にはんだ（２００）を介して配置される半導体パッケージであって、
    　半導体チップ（３０）と、
    　一面（２１１）および前記一面と反対側の他面（２１２）を有し、前記一面に前記半導体チップが配置されるアイランド部（２１）と、
    　一面（２２１）および前記一面と反対側の他面（２２２）を有し、前記半導体チップと接続部材（５０）を介して接続される端子部（２２）と、
    　前記アイランド部の他面および前記端子部の他面を露出させつつ、前記半導体チップを封止するモールド樹脂（６０）と、を備え、
    　少なくとも前記端子部は、前記はんだを介して前記被実装部材と接続されており、
    　前記半導体チップのうちの前記アイランド部と反対側には、前記モールド樹脂より熱伝導率が高い材料で構成され、前記半導体チップと熱的に接続されると共に前記モールド樹脂で封止された放熱部材（３１）が配置された半導体パッケージ。     A semiconductor package that is placed on the mounted member (100) via solder (200).
    Semiconductor chip (30) and
    An island portion (21) having one surface (211) and another surface (212) on the opposite side to the one surface on which the semiconductor chip is arranged, and
    A terminal portion (22) having one surface (221) and the other surface (222) opposite to the one surface and connected to the semiconductor chip via a connecting member (50).
    A mold resin (60) for sealing the semiconductor chip while exposing the other surface of the island portion and the other surface of the terminal portion is provided.
    At least the terminal portion is connected to the mounted member via the solder.
    The side of the semiconductor chip opposite to the island portion is composed of a material having a higher thermal conductivity than the mold resin, and is thermally connected to the semiconductor chip and sealed with the mold resin. The semiconductor package in which (31) is arranged.
  17. 　被実装部材（１００）にはんだ（２００）を介して配置される半導体パッケージであって、
    　半導体チップ（３０）と、
    　一面（２１１）および前記一面と反対側の他面（２１２）を有し、前記一面に前記半導体チップが配置されるアイランド部（２１）と、
    　一面（２２１）および前記一面と反対側の他面（２２２）を有し、前記半導体チップと接続部材（５０）を介して接続される端子部（２２）と、
    　一面（６１）および前記一面と反対側の他面（６２）を有し、前記アイランド部の他面および前記端子部の他面を露出させつつ、前記半導体チップを封止するモールド樹脂（６０）と、を備え、
    　前記アイランド部の他面は、前記モールド樹脂の一面から露出しており、
    　前記端子部の他面は、前記モールド樹脂の他面から露出しており、
    　前記端子部が前記はんだを介して前記被実装部材と接続されている半導体パッケージ。     A semiconductor package that is placed on the mounted member (100) via solder (200).
    Semiconductor chip (30) and
    An island portion (21) having one surface (211) and another surface (212) on the opposite side to the one surface on which the semiconductor chip is arranged, and
    A terminal portion (22) having one surface (221) and the other surface (222) opposite to the one surface and connected to the semiconductor chip via a connecting member (50).
    A mold resin (60) having one surface (61) and another surface (62) opposite to the one surface, and sealing the semiconductor chip while exposing the other surface of the island portion and the other surface of the terminal portion. And with
    The other surface of the island portion is exposed from one surface of the mold resin.
    The other surface of the terminal portion is exposed from the other surface of the mold resin.
    A semiconductor package in which the terminal portion is connected to the mounted member via the solder.
  18. 　被実装部材（１００）にはんだ（２００）を介して半導体パッケージ（１０）が配置された半導体装置であって、
    　請求項１ないし１７のいずれか１つに記載の前記半導体パッケージと、
    　少なくとも前記端子部と前記はんだを介して接続されるランド（１１２）を有する前記被実装部材と、を備えている半導体装置。     A semiconductor device in which a semiconductor package (10) is arranged on a mounted member (100) via solder (200).
    The semiconductor package according to any one of claims 1 to 17 and the above-mentioned semiconductor package.
    A semiconductor device including at least the terminal portion and the mounted member having a land (112) connected via the solder.
  19. 　被実装部材（１００）にはんだ（２００）を介して半導体パッケージ（１０）が配置された半導体装置であって、
    　前記半導体パッケージは、
    　半導体チップ（３０）と、
    　一面（２１１）および前記一面と反対側の他面（２１２）を有し、前記一面に前記半導体チップが配置されるアイランド部（２１）と、
    　一面（２２１）および前記一面と反対側の他面（２２２）を有し、前記半導体チップと接続部材（５０）を介して接続される端子部（２２）と、
    　前記アイランド部の他面および前記端子部の他面を露出させつつ、前記半導体チップを封止するモールド樹脂（６０）と、を備え、
    　前記被実装部材は、前記端子部と前記はんだを介して接続されるランド（１１２）を備え、
    　前記端子部と前記ランドとの間には、前記端子部および前記ランドと電気的に接続される電子部品（４００）が配置されている半導体装置。     A semiconductor device in which a semiconductor package (10) is arranged on a mounted member (100) via solder (200).
    The semiconductor package is
    Semiconductor chip (30) and
    An island portion (21) having one surface (211) and another surface (212) on the opposite side to the one surface on which the semiconductor chip is arranged, and
    A terminal portion (22) having one surface (221) and the other surface (222) on the opposite side to the one surface and connected to the semiconductor chip via a connecting member (50).
    A mold resin (60) for sealing the semiconductor chip while exposing the other surface of the island portion and the other surface of the terminal portion is provided.
    The mounted member includes a land (112) connected to the terminal portion via the solder.
    A semiconductor device in which an electronic component (400) electrically connected to the terminal portion and the land is arranged between the terminal portion and the land.
  20. 　被実装部材（１００）にはんだ（２００）を介して半導体パッケージ（１０）が配置された半導体装置であって、
    　前記半導体パッケージは、
    　半導体チップ（３０）と、
    　一面（２１１）および前記一面と反対側の他面（２１２）を有し、前記一面に前記半導体チップが配置されるアイランド部（２１）と、
    　一面（２２１）、前記一面と反対側の他面（２２２）、前記一面と前記他面とを繋ぐ側面（２２３）を有し、前記半導体チップと接続部材（５０）を介して接続される端子部（２２）と、
    　一面（６１）、前記一面と反対側の他面（６２）、前記一面と他面とを繋ぐ側面（６３）を有し、前記一面または前記他面から前記アイランド部の他面を露出させ、前記他面から前記端子部の他面を露出させると共に前記側面から前記端子部の側面の一部を露出させ、前記半導体チップを封止するモールド樹脂（６０）と、を備え、
    　前記被実装部材は、前記端子部と前記はんだを介して接続されるランド（１１２）を備え、
    　前記端子部の側面のうちの前記モールド樹脂から露出する部分を露出側面（２２３ａ）とすると、前記ランドは、前記半導体パッケージと前記被実装部材との積層方向において、前記露出側面と重なる部分と異なる部分にスリット（１１２ｂ）が形成されている半導体装置。     A semiconductor device in which a semiconductor package (10) is arranged on a mounted member (100) via solder (200).
    The semiconductor package is
    Semiconductor chip (30) and
    An island portion (21) having one surface (211) and another surface (212) on the opposite side to the one surface on which the semiconductor chip is arranged, and
    A terminal having one surface (221), another surface (222) opposite to the one surface, and a side surface (223) connecting the one surface and the other surface, and connected to the semiconductor chip via a connecting member (50). Part (22) and
    It has one surface (61), another surface (62) opposite to the one surface, and a side surface (63) connecting the one surface and the other surface, and exposes the other surface of the island portion from the one surface or the other surface. A mold resin (60) for exposing the other surface of the terminal portion from the other surface and exposing a part of the side surface of the terminal portion from the side surface to seal the semiconductor chip is provided.
    The mounted member includes a land (112) connected to the terminal portion via the solder.
    Assuming that the portion of the side surface of the terminal portion exposed from the mold resin is the exposed side surface (223a), the land is different from the portion overlapping the exposed side surface in the stacking direction of the semiconductor package and the mounted member. A semiconductor device in which a slit (112b) is formed in a portion.
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