TW200822334A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- TW200822334A TW200822334A TW096123072A TW96123072A TW200822334A TW 200822334 A TW200822334 A TW 200822334A TW 096123072 A TW096123072 A TW 096123072A TW 96123072 A TW96123072 A TW 96123072A TW 200822334 A TW200822334 A TW 200822334A
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- leads
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- lead
- lead frame
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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Description
200822334 九、發明說明: 【發明所屬之技術領域】 本發明涉及一種半導體裝置之製造方法及半導體裝置之 技術,特別是涉及適用於如下半導體裝置之製造方法及半 導體裝置之有效技術,此種半導體裝置使用有引線之打線 - 接合部經壓潰加工之所謂壓框。 【先前技術】 導 於 QFN(Quad Flat N〇n leaded package,四方形扁平無引 線封裝)等所代表之無引線封裝型半導體裝置中,考慮到 確保引線與焊接線之焊接可靠性,有時使用壓框,對於引 線中焊接有焊接線之部分進行壓潰加工(壓印)。 又,於無引線封裝型半導體裝置中,因有時引線較短而 導致於封膠步驟後產生脫落,因此考慮到強化引線與封膠 樹脂之密著性,於引線表面之一部分中與封膠樹脂相接之 部位’於與引線表面交叉之方向上設置凹槽(notch)。 |; 對於QFN而言,例如於日本專利特開2005-276890號公 報(專利文獻1)中有所揭示。上述專利文獻丨中,揭示有如 下技術:於無引線封裝型半導體裝置之引線中,通過蝕刻 或壓潰加工,使連接有焊接線之部分凹陷,並使焊接線迴 路高度低於上述凹陷量,藉此使焊接線不致自封裝體下表 面露出。 此外,於上述專利文獻〗中,揭示有如下技術:於與引 線中焊接有焊接線之面相反之面上形成凹槽,並強化引線 與封膠樹脂之密著性,藉此防止引線脫落。 121902.doc 200822334 此外,例如於日本專利特開平7_245365號公報(專利文 獻2)中,揭示有如下技術:於多引腳封裝用之引線框之製 造方法中’當對内引線前端進㈣印加卫時,以使各内引 線之壓印加工之面積相箄 ㈣寺之方式進行加工,藉此防止引線 出現位置偏離或相鄰引線間出現短路。例如揭示有形成斜 面使内5丨狀前㈣處純^技術,來作為使上述壓印 加工之面積相等之方法。
此外,於上述專敎獻2巾之段落[⑽22]中,揭示有如 下問題·因進行壓潰加工而使内引線之前端彈起。 [專利文獻1] 曰本專利特開2005-276890號公報 [專利文獻2] 曰本專利特開平7-245365號公報(段落[0022]) 【發明内容】 [發明所欲解決之問題] 然而’於使用上述壓框之無引線封裝型半筹體裝置中, 本發明者提出存在如下問題。通過圖丨〜圖1〇對此類問題加 以說明。 圖1表不壓印加工處理前之引線5〇之主要部位剖面圖。 於引線50中,圖i之左侧表示朝向半導體晶片之前端部。 於引線50之上表面’沿著引線5〇之寬度方向而形成有v字 狀槽51,其延伸於與引線50上表面交叉之方向上。 其次’圖2〜圖4表示壓印加工處理中之引線5 〇之主要部 位剖面圖。首先,如圖2所示,於引線50之上表面之上方 I21902.doc 200822334 配置壓印衝頭52。壓印衝頭52之擠壓面與引線5〇之上表面 大致平行。隨後,使上述壓印衝頭52下降,如圖3所示, 將其推到引線50之前端部上,沖擠引線5〇之前端部。此 後,如圖4所示,使壓印衝頭52上升,並離開引線5〇。此 蚪,以形成於引線50上表面之槽51為支點,引線5〇之前端 部向上方彈起(變形)。 其次,圖5表示封膠步驟後之半導體裝置之主要部位剖 面圖。對上述引線50進行壓印處理之後,於引線5〇前端部 之上表面形成鍍銀(Ag)層53,再於鍍銀層53之上表面上焊 接焊接線54後,轉移到封膠步驟。於封膠步驟中,利用封 膠樹脂形成封裝體55。此時,如上所述,因引線5〇前端部 向上彈起,因此,於封膠模具之下模與引線5〇之下表面之 間,形成有間隙,其結果為:封膠樹脂進入到上述間隙 内’形成毛刺(溢膠)55a,覆蓋引線5〇之一部分下表面。因 ^,存在如下問題:當隨後對引線5G表面進行鍵敷處理 時’會因毛刺55a阻礙而無法於引線5〇下表面上形成鑛敷 層,因此無法將半導體裝置安裝於配線基板上。 因此,若減少上述壓印處理時引線5〇之壓潰量,則可抑 制引線50前端彈起’故可減小或防止因上述毛刺而導致半 導體裝置安裂不良。然%,此時存在如下問題。通過圖6 及圖7對上述問題加以說明。圖6表示將壓印處理後之引線 框堆積起來進行搬運•保管時引線之主要部位剖面圖。 此外’圖7表示打線接合步驟後之引線5Q之主要部位剖面 圖。 121902.doc 200822334 如上所述,存在如下情 前h 右減小壓印處理中之引線50 ,+ &,貝里則如圖6所示,當將引線框堆積 起來進行搬運•保瞢拄 積 "、、έ吏上側引線框之引線50下表面 與下側引線框之引線5 0上 卜衣面 觸。直社里* 表面(形成有鍍敷層53之面)相接 . …果為:於下側引線50前端部之上表面鑛敷層53 上,會產生擦傷。然而,若 南田 上述狀恶下,進行打線接合 、 處理,則如圖7所示,合存扁如ΠΓ Μ π 曰在如下問題,於上述引線50之 則‘ ^上表面帶有擦傷$供甫々c q, • “劳之鍍敷層53上,對焊接線54進行焊 接後,會導致出現焊接不良。 十 U U明之目的在於提供—種可提高半導體裝置 率之技術。 本發明之上述以及其他目的與新穎特徵,可通過本說明 書描述及隨附圖式而得到瞭解。 [解決問題之技術手段] 對本申請案所揭示之發明中一個代表性發明之 • 單說明如下。 間 即’本發明具有:封裝體,其具有沿著厚度方向相互位 於:目反側之第!主面及第2主面;半導體晶片,封裝於上述 子衣體内’晶片搭载部,封裝於上述封裝體内部,且搭 載有上述半導體晶片;多個引線,一部分自上述封裝體之 第1主面露出;以及多個桿接線’封裝於上述封裝體内 部’且電性連接上述半導體晶片與上述多個引線;且於上 述多個引線之各引線中,於未谭接有上述嬋接線且與上述 封裝體連接之部位’形成有槽,於上述多個引線之各引線 121902.doc 200822334 中,對焊接有上述焊接線之部分進行塵潰加工,於上述多 個引線之各引線燁接有上述焊接線之部分,位置相對靠= 上述半導體晶片之壓潰量,大於位置相對遠離 體 晶片之壓潰量。 千¥體 [發明之效果] "對本申請案所揭示之發明中代表性發明所取得之效果, • 間單說明如下。 • 卩於上述多個引線之各引線焊接有上述烊接線之部分 巾,由於位置相對靠近上述半導體晶片之壓潰量大於位置 相對遠離上述半導體晶片之壓潰量,因此可提高半導體裝 置之良率。 【實施方式】 、以下實施形態為方便說明’而分成多個部分或實施形態 進行說明,但除特別指明以外,上述多個部分或實施形態 並非相互無關,而是存在其中之一部分係其它一部分或全 • 部=變形例、詳細說明、補足說明等之關係。而且,於以 :貫施形態中,所謂要素之數目等(包括個數、數值、 量、範圍等)’除特別指明及原理上明確限定於特定數目 以外,並非限定於上述特定數目,亦可係特定數目以上或 以下。另外,於以下實施形態中,其構成要素(亦包括要 素步驟等)除特別指明或原理上明確認為必要以外,即可 認為並非必要。同樣,於以下實施形態中,提及構成要素 等之形狀、位置關係等時,除特別指明或原理上可明確認 為並非如此以外’可包含實質上近似或類似於此形狀等。 121902.doc -10- 200822334 對於上述數值及範圍而古 允幺 礼固叩。亦為同樣。此外,於用以說明 本實施形態之全部附圖中,斟呈亡 订口 γ對具有相同功能之部分附以相 同符號,並盡可能省略1會^ ,略具菫複說明。以下,根據圖式對本 發明之實施形態進行詳細說明。 按照圖8之製造流程圖,並通過圖9〜圖25對本實施形離 之半導體裝置之製造方法之一例進行說明。 〜
首先’對晶片處理(初期步驟)結束後之半導體晶片進行 切剎處理’猎此將半導體晶片分割成多個半導體晶片(圖8 中之步驟100)。半導體晶片由例如由單晶矽(Si)構成之平 面近似圓形之半導體薄板構成,且於各半導體晶片之主面 上形成有預期之整合電路。 繼而,如圖9及圖10所示,將上述半導體晶片丨搭載於引 線框2之晶片座(捲帶自動黏合、晶片搭載部)2&上(圖8中之 步驟1 0 1) 〇 圖9係晶片搭載步驟後之引線框2單位區域之平面圖,圖 10係圖9中Xioa線之放大剖面圖。此外,圖u係圖9中又2· X2線之放大剖面圖。 半導體晶片1由例如平面正方形之半導體薄板構成,並 於其主面朝上,其背面朝向晶片座2&之狀態下,繼而固定 於曰曰片座2a上。於半導體晶片1之主面外周附近,沿著上 述主面外周並列配置有多個焊墊(以下僅稱為墊片)Bp。墊 片BP與半導體晶片1主面上之整合電路電性連接。 引線框2由含有例如銅(Cu)或42合金等之金屬薄板構 成,且具有沿著厚度方向相互位於相反侧上之第i主面s 1 121902.doc -11- 200822334 及第2主面S2。 於上述引線框2之弟1、弟2主面SI、S2内,多個單位區 域配置成一行或矩陣狀。於引線框2之各單位區域中,配 置有:晶片座2a ;多個引線2b,其配置為環繞包圍上述外 周;懸空引線2c,自晶片座2a之四個角朝向外侧延伸;以 及框體部2d,支撐上述多個引線2b及懸空引線2c。 多個引線2b之各引線與多個懸空引線2〇之各懸空引線,
通過各自之一端與框體部2d連接成一體而支撐於引線框2 上0 於各引線2b之第2主面側中,半導體晶片}側之前端部 上’形成有相對引線框2之第2主面傾斜之第3主面S3。於 上述第3主面S3上,形成有例如由銀(Ag)形成之鍍敷層 2e。於形成有上述鍍敷層2e之部分,焊接有下述焊接線。 此外於各引線2b之第2主面S2上,自引線2b之半導體 晶片1側前端後退與第3主面83相應之距離後之位置上,與 上述第2主面S2父叉之方向上形成有凹槽(凹口,橫切各 引線2b之長度方向。上述槽2£之形成目的係為了提高下述 封膠步驟後封膠樹脂與引線孔之密著性,以抑制或防止引 線2b脫洛。因此,槽2f形成於由封膠樹脂覆蓋之部分上。 此外,槽2f形成於並未焊接有下述焊接線之部分上。 通過圖12〜圖14對上述引線2b之第3主面S3之形成方法之 一例進行說明。另外, 2 b之主要部位放大剖面 首先,如圖12所示, 圖12〜圖η係第3主面S3形成時引線 圖。 將形成槽2f後之引線框2載置於壓 121902.doc •12- 200822334 印室3a上。使引線框2狀態如下··其第1主面S1朝向壓印臺 3a,且其弟2主面S2朝向壓印衝頭3b。壓印衝頭3b之引線 擠壓面PS相對於引線2b之第2主面傾斜。即,壓印衝頭3七 之引線擠壓面PS,係以朝向引線儿之前端部逐漸降低之方 式傾斜。 繼而,如圖13所示’將壓印衝頭3b之引線擠壓面PS推到 引線2b前端部之第2主面S2側,對上述引線2b前端部進行 壓潰。此時,因壓印衝頭3b之引線擠壓面ps形成為傾斜 面,因此於引線2b之前端部,位置相對靠近半導體晶片i 側之壓潰量,將大於位置相對遠離半導體晶片丨之壓潰量 (傾斜壓印處理)。此外,亦使引線2b之壓潰量大於上述鍍 敷層2e之厚度。 隨後,如圖14所示,使壓印衝頭3b離開引線孔。因此, 於引線2b於半導體晶片1側之前端部上,上述壓印衝頭% 之引線擠壓面PS所推壓之部位上,將形成相對於引線沘之 第1主面S1及第2主面S2傾斜之第3主面S3。 上述第3主面S3形成為自槽2f朝向引線2b位於半導體晶 片1側上之前端,以平面觀察,則形成為幅寬大於引線几 其他部分之平面四邊形。又,上述第3主面S3,以剖面觀 察,則形成為由槽2f朝向引線2b之前端,其高度(距離引線 2b之第1主面S1之距離)逐漸降低(變短)。上述第3主面以之 壓潰尺寸設定如下:當引線框2於厚度方向上重疊時,使 上側引線2b之第1主面si與下側引線2b之第3主面S3上之鍍 敷層2e相互不接觸。另外,第3主面S3亦相對半導體裝置 121902.doc -13 - 200822334 之安裝面傾斜。 當本實施形態如卜%、+、 厅迷日守,可通過進行上述傾斜壓印處 理’使墨印潘於^ p! Θ 圖4所說明之情況。因此,即使於引 線2b之前端部形诸 β 成上迷槽2f,亦可以抑制或防止引線21}前 端部彈起。 回表不將上述壓印處理後之2個引線框2堆積起來進行 ,運或保官時引線⑪之主要部位放大剖面圖。於本實施形 〜中”引線2b蝻端部之第3主面S3為傾斜的,並且使引線 堊’貝里大於上述鍍敷層2e之厚度。因此,當將多個引 線框2堆積起來時’可降低或防止上側引線2b之第1主面 (下表面)S1與下側引線2b之第3主面S3之鍍敷層2e產生接 觸口此’可降低或防止下側引線2b前端部之第3主面S3 之鍍敷層2e上產生擦傷。
Ik後’如圖16、圖17及圖18所示,通過焊接線(以下僅 稱為焊線,而電性連接上述半導體晶片1之墊片BP、與 引線框2之引線2b(U 8中之步驟1〇2)。 圖16係打線接合步驟後之引線框2之單位區域之平面 圖’圖17係圖16中xi-xi線之放大剖面圖,圖18係圖16中 X2-X2線之放大剖面圖。 焊線5例如由金(An)形成。焊線5由例如正焊缝方式焊 接。即’焊線5之一端(第1焊點)焊於半導體晶片1之墊片 BP上,焊線5另一端(第2焊點)焊於引線2b之第3主面S3之 鍍敷層2e上。再者,焊線5之第2焊點,於設計上看,位於 距離引線2b前端〇· 15 mm左右之位置上。 121902.doc -14- 200822334 於本實施形態中,由於可降低或防止引線2b之鍍敷層以 擦傷,因此,可將焊線5之一端(第2烊點)良好地焊接於引 線2b前端部之第3主面S3(鍍敷層2e)上。即,因能夠提高焊 線5與引線2b之焊接性,故可提高半導體裝置之良率及可 靠性。 隨後,通過轉注封膠步驟,如圖19、圖2〇及圖21所示, 於各單位區域中形成封裝體7(圖8中之步驟1〇3)。 圖19係封膠步驟後引線框2之單位區域之平面圖,圖2〇 係圖19中χΐ-χι線之放大剖面圖,圖21係圖2〇中局部a即 圖19中之X2-X2線之放大剖面圖。另外,於圖19中,為使 圖式清晰可見,而使封装體7之内部透明可見。 封展體7例如由ί哀氧樹脂形成。通過封裝體7而封裝半導 體晶片1、焊線5、晶片座2a之一部分、引線2b之一部分、 以及懸空引線2c之一部分。 於本實施形態中,如上所述,因可抑制或防止引線几之 前端部彈起,因此可減小或消除引線2b之第1主面S1與封 膠下模之引線框搭載面之間之間隙。故而可降低或防止產 生於引線2b之第1主面s 1上附著上述毛刺(溢膠)等不良情 形。 繼而,於引線框2(引線2b)中自封裝體7裏面露出之表面 上’形成例如由銀構成之鍍敷層(圖8中之步驟1〇4)。此 ^於本貝^形態中,由於如上所述可降低或防止出現引 線2b之第1主面S1上附著有上述毛刺(溢膠)等不良情形, 故而可降低或防止鍍敷潤濕不足。 121902.doc •15- 200822334 繼而,對引線框2之一部分進行切割,使引線㉛成形(圖 8中之步驟1〇5)。藉此使各個半導體裝置與引線框2分離。 圖22係切割步驟後半導體裝置之整體平面圖,圖23係圖 22中半導體裝置之側面圖,圖24係圖22中X3-X3線之放大 剖面圖,圖25係圖22中X4-X4線之放大剖面圖。另外,於 圖22中,為使圖式清晰可見,而使封裝體7之内部透明可 見。 本實施形態之半導體裝置之結構為例如QFN(Quad Flat Non leaded Package)。即,本實施形態之半導體裝置構成 如下,雖然引線2b之一部分自封裝體7之側面及背面露 出’但引線2b自封裝體7側面突出之突出長度較短。 於上述引線2b之露出面(除了引線框2之切割面)上,形 成有通過上述圖8中步驟1〇4之鍍敷處理而形成之鍍敷層 8。如上所述,根據本實施形態,因可降低或防止產生引 線2b之第1主面S1上附著上述毛刺(溢膠)等不良情形,故 而,能夠於引線2b之第1主面S1上良好地形成鍍敷層8。因 此,可降低或防止出現半導體裝置安裝不良。 另外’於QFN結構方面,存在引線2b由於較短而自封裝 體7上脫落之可能性,但於本實施形態中,由於通過於引 線2b之第2主面S2上形成槽2f,便能夠提高引線2b與封裝 體7(封膠樹脂)之岔著性,因此,可抑制或防止較短引線2匕 出現脫落。 隨後,自取得之多個半導體裝置中篩選出合格品進行出 貨(圖8中之步驟106、1〇7)。 121902.doc -16 - 200822334 以上,根據實施形態對本發明者所完成之發明進^_ 體說明,但本發明並非限定於上述實施形態, 仃了具 以於不偏離其精神之範圍内進行各種變更。 [產業上之可利用性] 本舍明可應用於半導體裝置之製造業。 【圖式簡單說明】 圖1係壓印處理前引線之主要部位剖面圖。 圖2係壓印處理過程中引線之主要部位剖面圖。 圖3係繼續圖2之壓印處理過程中引線之主要 口丨叹剖面 圖。 圖4係繼續圖3之壓印處理過程中引線之主要部位剖面 圖。 圖5係封膠步驟後半導體裝置之主要部位剖面圖。 圖6係將壓印處理後之引線框堆積起來進行搬•保管時弓j 線之主要部位剖面圖。 圖7係打線接合步驟後引線之主要部位剖面圖。 圖8係本發明作為一個實施形態之半導體裝置之製造方 法之一例之製造流程圖。 圖9係圖8中晶片搭載步驟後引線框之單位區域之平面 圖。 圖10係圖9中X1-X1線之放大剖面圖。 圖11係圖9中X2-X2線之放大剖面圖。 圖12係圖9中引線框第3主面之形成步驟中之引線之主要 部位放大剖面圖。 121902.doc 200822334 圖13係繼圖12之引線框第3主面之形成步驟φ + ^ 之 之 或 面 τ之引線 主要部位放大剖面圖。 圖14係繼圖13之引線框第3主面之形成步驟++ 3 外甲之弓丨線 主要部位放大剖面圖。 圖15係將壓印處理後之2個引線框堆積起來進行搬、 保管時引線之主要部位放大剖面圖。 圖16係圖8中打線接合步驟後引線框之單位區 4 t平 圖。 圖17係圖16中X1-X1線之放大剖面圖。 圖1 8係圖16中X2-X2線之放大剖面圖。 圖19係圖8中封膠步驟後引線框之單位區域之平面圖。 圖20係圖19中X1-X1線之放大剖面圖。 圖21係圖20之局部A即圖19中X2-X2線之放大剖面圖。 圖22係圖8中切割步驟後半導體裝置之整體平面圖。 圖23係圖22中之半導體裝置之側面圖。 圖24係圖22中X3-X3線之放大剖面圖。 圖25係圖22中X4-X4線之放大剖面圖。 【主要元件符號說明】 1 半導體晶片 2 引線框 2a 晶片座(晶片 2 b 引線 2c 懸空引線 2d 框體部 121902.doc 18· 200822334
2e 鍍敷層 2f 槽 3a 壓印臺 3b 壓印衝頭 5 焊接線 7 封裝體 8 鑛敷層 50 引線 51 槽 52 壓印衝頭 53 鑛敷層 54 焊接線 55 封裝體 55a 毛刺 BP 焊墊 SI 第1主面 S2 第2主面 S3 第3主面 PS 引線擠壓面 121902.doc
Claims (1)
- 200822334 十 i. 、申請專利範圍: 一種半導體裝置之製造方法,其特徵在於,具有 驟:⑷步驟,準備引線框,上述引線棍具有沿著厚产; 向相互位於相反側之第1主面及第2主面,且於每個;位 區域中具有上述晶片搭載部及上述多個引線,步驟, 於上述引線框之上述晶片搭載部之第2主面上,搭載上 述半導體晶片;⑷步驟,通過焊接線電性連接上述半導 體晶片與上述引線框之上述多個引線;⑷步驟,以覆宴 上述多個引線之各引線之—部分中之整個上述半導體曰 片及整個上述焊接狀方式,形成封錢;⑷步驟,於 上述多個引線巾,對自上述封裝體中露出之部分進行鍵 敷處理;以及(f)步驟,切割一部分上述引線框,使上述 封裝體自上述引線框中分開;且對上述⑷步驟中之引線 框實施如下步驟:(al)於上述引線框之上述多個引線之 各引線之第2主面中,並未焊接有上述焊接線且由上述 封裝體覆蓋之部分中,於與上述多個引線之各引線之第 2主面又叉之方向上,以橫切上述多個引線之各引線長 度方向之方式,形成凹槽,(a2)於上述引線框中上述多 個引線之各引線第2主面上,對焊接有上述焊接線之部 分,以位置相對靠近上述半導體晶片之壓潰量大於位置 相對遠離上述半導體晶片之壓潰量之方式進行壓潰加 工,(a3)對上述引線框中上述多個引線焊接有上述焊接 線之部分’實施鑛敷處理。 2·如明求項1之半導體裝置之製造方法,其中,於上述(a) 121902.doc 200822334 步驟中上述引線框之上述多個引線之各引線第2主面 、側烊接有上述焊接線之部分上,形成有相對於上述多 個引線之各引線第2主面傾斜之第3主面。 3.如請求項〗之半導體裝置之製造方法,其中,上述(&2)中 上述引線框之上述多個引線之各引線之壓潰量,大於上 • 述(a3)中之鍍敷厚度。 • 4· 一種半導體裝置之製造方法,其特徵在於,具有如下步 φ 驟·(勾步驟,準備引線框,上述引線架具有沿著厚度方 向相互位於相反側之第丨主面及第2主面,且於每個單位 區域中具有上述晶片搭載部及上述多個引線;⑻步驟, 於上述引線框之上述晶片搭載部之第2主面上,搭载上 述半導艟晶片;(c)步驟,通過焊接線電性連接上述半導 體晶片與上述引線框之上述多個引線;(d)步驟,以覆蓋 上述多個引線中之各引線之一部分上之整個上述半導= 晶片及整個上述焊接線之方式,形成封裝體;⑷步驟, # 於上述多個引線中,對自上述封裝體中露出之部分進行 鍍敷處理;以及(f)步驟,切割上述引線框之一部分,使 • 上述封裝體自上述引線框分開;且上述⑷步驟具有如下 步驟··(al)步驟,於上述引線框中上述多個引線之各引 •線第2主面中,並未焊接有上述焊接線且由上述封裝體 覆蓋之部分上,於與上述多個引線之各弓丨線第2主面交 叉之方向上,以橫切上述多個引線之各引線長度方向之 方式,形成凹槽;(a2)步驟,於上述引線框中上述多個 引線之各引線第2主面中,對焊接有上述焊接線之部分 121902.doc 200822334 施行壓潰加工;(a3)步驟,對上述引線框中上述多個引 線知接有上述烊接線之部分,實施鑛敷處理;以及 步驟,於上下引線框之第1主面與第2主面相對向之狀鎮 下,於厚度方向上堆積上述⑽〜㈤)步驟後之多個上述 引線框;且’於上述⑻)步驟中,對上述多個引緣之各 引線’以位置相對靠近上述半導體晶片之壓潰量,大於 位置相對遠離上述半導體晶片之壓潰量之方式實施壓潰 加工。 5. =請求項4之半導體裝置之製造方法,其中,於上述⑽ 二驟中,於上述多個引線之各引線第2主面側焊接有上 述焊接線之部分上,形成相對上述多個引線之各引線第 2主面傾斜之第3主面。 7. 6. 如請求項4之半導體裝置之製造方法,其中,上述㈣步 驟中之壓潰量大於上述(a3)步驟中實施锻敷之厚产。 ,導體裝置’其特徵在於:具有:封裝體,具有沿 者厚度方向相互位於相反側之第1±面及第2主面·半導 體晶片,封裝於上述封裝體之内部;晶片搭載部,封穿 於上述封裝體之内部且搭載有上述半導體晶片;多個引 線’一部分自上述封裝體之^主面露出;以及多個焊 接線’封裝於上述封裝體之内部,且電性連接上述半導 體晶片與上述多個引線;且’於上述多個引線之各引線 第2主面上,對焊接有上述焊接線之部分進行遷潰加 工’而於上述多個引線之各引線第2主面上,對桿接有 上述焊接線且經過上述屋潰加工之部分,實施鑛敷處 121902.doc 200822334 理’並且於上述多個引 ,,^ 線之各引線第2主面上焊技亡p 述焊接線之部分上,位置相對靠近:二 潰量,大於位置相對遠離上述半導體晶片之麗潰量片。之反 8.如_7之半導體裝置,其中,於上述多個引線之各 引線第2主面側,焊接有上述焊接線之部分中,形成有 相對上述多個引線之各引線第2主面傾斜之第3主面。9·如請求項7之半導體裝置,其中,於上述多個引線之各 引線弟2主面上,焊接有上述焊接線之部分之壓潰量, 大於上述多個引線之各引線第2主面上對焊接有上述焊 接線之部分所實施鍍敷之鍍敷厚度。121902.doc
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US9870985B1 (en) * | 2016-07-11 | 2018-01-16 | Amkor Technology, Inc. | Semiconductor package with clip alignment notch |
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