TW200820401A - Chip package and manufacturing method thereof - Google Patents

Chip package and manufacturing method thereof Download PDF

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Publication number
TW200820401A
TW200820401A TW095138948A TW95138948A TW200820401A TW 200820401 A TW200820401 A TW 200820401A TW 095138948 A TW095138948 A TW 095138948A TW 95138948 A TW95138948 A TW 95138948A TW 200820401 A TW200820401 A TW 200820401A
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TW
Taiwan
Prior art keywords
heat
carrier
wafer
heat sink
package structure
Prior art date
Application number
TW095138948A
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English (en)
Inventor
Chi-Hsing Hsu
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW095138948A priority Critical patent/TW200820401A/zh
Priority to US11/565,866 priority patent/US20080093733A1/en
Publication of TW200820401A publication Critical patent/TW200820401A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

200820401 VIT06-0127 21927twf.doc/t 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件及其製造方法，且特 別是有關於一種晶片封裝結構及其製造方法。 ‘ 【先前技術】
在半‘體產業中’積體電路（integrated circuits，1C) 的生產主要可分為三個階段：積體電路的設計（IC 〆 design)、積體電路的製作（ICpr〇cess)及積體電路的封 ’ 裝（IC package )。 :在積體電路的製作中，晶片（chip)是經由晶圓（wafer) 衣作、形成積體電路以及切割晶圓（wafer sawing)等步驟 而元成。晶圓具有一主動面（active surface )，其泛指晶 圓之具有主動元件（active element)的表面。當晶圓内部 之積體電路完成之後，晶圓之主動面更配置有多個焊墊 (bondingpad)，以使最終由晶圓切割所形成的晶片可經 =這些焊墊而向外電性連接於一承載器（carrie〇。承載 (/器例如為一導線架（ieadframe)或一封裝基板（package substrate)。晶片可以打線接合（wire b〇ncjing)或覆晶接 _ 合Ending)的方式連接至承載器上，使得晶片 i 之這些焊墊可電性連接於承載器之接點，以構成一晶片封 裝結構。 就覆晶接合技術（flip chip bonding technology )而言， 通常在晶圓之主動面上形成這些烊墊之後，會在各個焊墊 上進行製作一凸塊（bump)，以作為晶片電性連接外部封 5 200820401 VIT06-0127 21927twf.doc/t f基板之用。由於這些凸塊通常以鱗列的方式排列於晶 一之主，Φ上使彳錢晶接合技術適於運躲高接點數及 同，點4度之aa片封裝結構，例如已普遍地應用於半導體 封裝產業中的覆晶/球格陣列式封裝（_物編gr.d _y paekage)。此外’相較於打線接合技術，由於這些 凸塊可提供BB片與承载&之間較短的傳輸路徑，使得覆晶 接δ技術可提升Βθ片封|結構之電性效能 (electrical
performance)。 在習知的覆晶接合製程中，在將晶片經由多個凸塊而 ^生連^且蚊在基板上之後，為了加強晶片的散熱效 果，通常會將—具有凹槽（e一）的散熱器（heat spreader) ，散熱膠（thermal感―而貼附於晶片的背面，使 得晶片位於配置於基板上的散熱器的凹槽内。當習知晶片 封裝結構運㈣，晶片所產生的熱主要藉由晶片背面的散 ，膠與散熱ϋ而傳遞（tmnsfo)至外界環境巾，所以散熱 益直接與晶片背©難接的部分其溫度較高，而散熱器直 他部分的溫賴較低。換言之，f知晶片封裝結構的^孰 益的散熱效率較差。然而，隨著晶片運作時的高耗能與高 ，率的設計趨勢下，習知職於^上之散熱㈣散熱效 率已不敷需求，因此改善習知晶片縣結構的散熱效率是 有其必要性。 【發明内容】 本發明之目的是提供-種晶片封裝結構，敎 有所提升。 ...... 6 200820401 VIT06-0127 21927twf.doc/t 本發明之另—目的是提供—種晶片㈣結構的製造 =法，使得散熱效率有所提升的晶片封裝結構的製造成本 較為低廉。 為達上述或是其他目的，本發明提出一種晶片封装处 ΐ:其包括T承載器、至少—晶片、—散熱器與—導熱^ 貝（thermal interface materia卜 ΤΙΜ)。晶片配置於承 上f電性連接至承制。散熱11配置於承載ϋ上，其中气 熱器與=載器共同形成—密閉空間（ — spaa) '、且:曰曰 片位於密閉空間内。此外，導熱介質填滿密閉空間。曰曰 =達上述或是其他目的，本發明提出— 承載器、至少—晶片、一散熱器與一夂; i於:^上於承^器上且電性連接至承載器。散熱器配 、表载。„上’其中散熱器與承載器共同形成一密閉空 fU且Ϊ片位於密閉空間内。此外，導熱介質位於密閉Ϊ 間内、’其中導熱介質與散熱器之内表面相接觸。 構的iSi或目的’本發明提出一種晶崎結 :錢方法，其包括下列步驟。首先，提供—承載哭。 片少:Ϊ片配置於承载器上。接著，電‘ 《载°°。後，將一散熱環體配置於承載器上，使得 二广體®繞晶片。之後’將—導熱介質填滿散熱環體於 ::上所圍繞的—容置空間 space#)、7 使‘ 上包覆晶片。織’將—散熱板體配置於散熱環體 散執产=散熱板f覆蓋晶片且導熱介質填滿由散熱板體、 心！體與承載器戶斤共同开)成的一密閉空間。 7 200820401 VIT06-0127 21927twf.doc/t 為讓本發明之上述和其他目的、特徵和優點能更明顯
易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 、W 【實施方式】 - 請參考圖1A，其繪示本發明第一實施例之一種晶片 - 封裝結構的剖面示意圖。第一實施例之晶片封裝結構1〇〇 包括一承載器110、至少一晶片12〇、一散熱器13〇與一導 熱介質140。晶片120配置於承載器11〇上且電性連接至 承載器110。散熱器130配置於承載器11〇上，其中散熱 器130與承載器11〇共同形成一密閉空間1〇，且晶片 位於密閉空間1〇内。此外，導熱介質14〇填滿密閉空間 10 〇 值得注意的是，當晶片封裝結構100運作時，由於導 熱介質140填滿密閉空間10，因此晶片12〇所產生的熱可 藉由導熱介質140以傳導的方式傳遞至散熱器13〇。由圖1 之粗黑箭頭可知，本實施例之晶片120所產生的熱不但可 ^ 由晶片120之背面亦可由晶片12〇之侧面以傳導的方式傳 遞至散熱為13〇。因此，與習知相較，本實施例之散熱器 130的溫度較為均勻（unif〇rm)，換言之，本實施例之晶 、 片封裝結構1〇〇的散熱效率較佳。 ^熱”貝140可為導熱化合物（thermally conductive C〇mp〇Und )或導熱彈性體（thermally conductive elastomer)。具體而言，導熱介質14〇可為錫膏（s〇lder
Past〇、散熱膏（thermal grease)或為添加二氧化矽或銀 8 200820401 VIT06-0127 21927twf.doc/t 的環氧樹脂（epoxy resin)。其中導熱介質140亦可包含 錫或鉛等金屬材質。在此必須說明的是，導熱介質140可 依設計者的需求而有所改變，第一實施例只是用以舉例而 非限定本發明。 詳言之，第一實施例之散熱器130包括一散熱板體 (thermal plate) 132 與一散熱環體（thermal ring) 134。 散熱環體134配置於散熱板體132上，且散熱環體134與 散熱板體132共同形成一凹槽136，而散熱環體134位於 散熱板體132與承載器11〇之間。由圖1可知，在第一實 施例中，密閉空間1〇可由散熱板體132、散熱環體134與 承載器110所共同形成，而填滿密閉空間1〇的導熱介質 140與散熱器130之内表面138相接觸。換言之，第一實 施例之導熱介質140與散熱器130之凹槽136的内壁相接 觸。 在此必須說明的是，第一實施例之散熱板體132與散 熱環體134可預先分別成型，之後再加工加以接合而成（詳 見後述），然而散熱板體132與散熱環體134亦可依照設 计需求而一體成型（integrally formed)。此外，請失考囷 1B，其繪示本發明第一實施例之另一種晶片封裝結構的^ 面示意圖。晶片封裝結構100,的散熱器13〇,更包括多個^ 片（fm) 139，其配置於散熱板體132之相對於散熱環= 134的^一侧上。、換言之，這些鰭片139由散熱板體u【以 朝向遠離晶片120的方向延伸。這些鰭片139的功能在於 增加散熱器130’與外界環境進行熱交換的面積，進而提升 9 200820401 VIT06-0127 21927twf.doc/t 散熱器130’的散熱效率。 請再參考圖1A，第一實施例之晶片封裝結構1〇〇更 包括多個導電凸塊（conductive bump) 150與一底膠層 (underfill layer ) 160，而承載器110可為電路板。這些導 電凸塊150配置於晶片120與承載器11〇之間，且底膠層 160包覆這些導電凸塊150。底膠層160用以保護這迪導電 凸塊150，並且當晶片封裝結構1〇〇運作而產生熱時，底 膠層160可緩衝受熱的承載器11〇與受熱的晶片12〇之間 所產生的熱應變（thermal strain )之不匹配（mismatch )的 現象。 以下對於第一實施例之晶片封裝結構1〇〇的製造方法 作詳細說明。圖2A至圖2G繪示圖1A之晶片封裝結構的 製造方法的流程示意圖，第一實施例之晶片封裝結構1〇〇 的製造方法包括下列步驟。首先，請參考圖2A，提供一承 載器110。接著，請參考圖2B,將至少一晶片12〇配置於 承載器11〇上。接著，電性連接晶片120與承載器11〇。 在第一實施例中，上述將晶片120配置於承&器11〇 上且電性連接至承載器110的這些步驟是藉由覆晶接合技 術而加以完成’其包括以下子步驟。首先，例如以電朗 方式於晶片110上形成多個導電凸塊150。之後，將曰片 120配置於承載器110上，且迴焊（refl〇w)這些導電=塊 15〇,使得這些導電凸塊150電性連接於晶片12〇與承載器 110之間。最後，形成一底膠層160,以包覆這些導電凸二 150。底膠層160通常是藉由於晶片12〇與承載器11〇之間 10 200820401 VIT06-0127 21927twf.d〇c/t 填充一底膠（underfill)且加以烘烤而完 之後’請參考圖2C，例如以黏著^。 體134配置於承載器11〇上 =式將一散熱環 120。之後，請參考圖2D，將一導^%體134圍繞晶片 體134於承载器110上所圍繞的:容置質140填滿散熱環 啊e) 20 ’使得導熱介質140包覆晶片^間（_taming 然後，請參考圖2E，在第一實施例中0 熱介質140填滿容置空間2〇的步驟之 了在上述*將¥ 内部的氣體抽離。若導熱介質刚為’將¥熱介f 140 取Ua__ion)的丄導===空二 i山μ · it道也人μ 丨貝140内部的氣體 =二為液態’則可以真空抽取或加熱或 ί將導熱介質140内部的氣體抽離。在此必 r熱介質刚内部的氣體抽離之後，導 …、’丨貝140的鬲度η通常會下降。 Ο 置空圖2F，再填人導熱介f 14G，以填滿容 = °復晶片12G°然後，請參考U2G，例如藉 由黏錢焊㈣方式將—散熱板體132配置於散熱環體 4上，使得散熱板體132覆蓋晶片120,且導熱介質14〇 填滿由散熱板體132、散熱環體134與承載器/川所共同 形成的一密閉空間10。其中，散熱板體132與散熱環體/'134 構成（compose)本實施例之散熱器ι3〇。 ^巧芩考圖1A，在第一實施例中，前述的密閉空間 疋以散熱板體132的内表面132a、散熱環體134的内表面 134a及承载器11〇的承載面112為界。散熱器13〇之内表 200820401 VIT06-0127 21927twf.doc/t 面138是由散熱板體…間衣甸與散熱環 的内表面134a所構成。導熱介質14()填人賴空間 導熱介質M0會和内表面138與承载面112相接觸。 導熱介質140覆蓋散熱板體132的内表面n，散熱 134的内表面134a及承載器11〇的承載面112。…衣體 請參考圖3，其緣示本發明第二實施例之一種 裝結構的剖面示㈣。第二實施例之晶片 ^
第一實施例之晶片封裝結構1〇〇的 U 片220相互電性連接，且以堆疊 二曰曰 上。在此必須說明的是，這4b 210 載上的方式可依照設計者的需求而有所改變。本ΐ 鈀例只疋用以舉例而非限定本發明。 貝 具有；：下H本發明之晶片塊結構及錢造方法至少
U 填滿密閉以構運作時，由於導熱介質 導的方式傳遞至散熱器。因此，藉2熱介質以傳 不但可由晶片之背面亦可由晶片：二=的熱 至散熱ϋ。φ域可知，細 的方式傳遞 部溫度較為_，抑卩太^知相較，本發明之散熱器内 較佳。 &月之晶片封裝結構的散熱效率 驟可與現有製之結構的製造方 U此本發明之散熱效率有所提升的 12 200820401 VIT06-0127 21927twf.d〇c/t 晶片^結_製造成本較為低廉。 脫離本發明之精神和範圍=域中具有通常知識者，在不 因此本發明之保護範^可作些許之更動與潤飾， 為準。 現谈附之申請專利範圍所界定者 【圖式簡單說明】 圖1A #會示本發明第〜丧a 剖面示意圖。 汽知例之一種晶片封裝結構的 的剖面示意圖。 〜實施例之另一種晶片封裝結構 之晶片封裝結構的製造方法 圖2A至圖2G繪示圖1 a 的流程示意圖。 圖3繪示本發明第二實 面示意圖。 、知例之一種晶片封裝結構的」 【主要元件符號說明】 Ο 1〇 :密閉空間 20 :容置空間 片封裝結構 100、100,、200 ··晶 110、210 :承載器 112 :承載面 120、220 :晶片 130、130’ ··散熱器 132 :散熱板體 13 200820401 VIT06-0127 21927twf.doc/t 132a :散熱板體之内表面 134 :散熱環體 134a :散熱環體之内表面 136 :凹槽 138 ·•散熱器之内表面 139 :鰭片 140 :導熱介質 150 :導電凸塊 160 :底膠層 Η :高度 14

Claims (1)

  1. 200820401 VIT06-0127 21927twf.doc/t 十、申請專利範圍： 1. 一種晶片封裝結構，包括： 一承載器； 至少一晶片，配置於該承載器上且電性連接至該承載 • 裔， - 一散熱器，配置於該承載器上，其中該散熱器與該承 載器共同形成一密閉空間，且該晶片位於該密閉空間内； 以及 一導熱介質，填滿該密閉空間。 2. 如申請專利範圍第1項所述之晶片封裝結構，其中 該散熱器包括： 一散熱板體；以及 一散熱環體，配置於該散熱板體上，其中該散熱環體 與該散熱板體共同形成一凹槽，且該散熱環體位於該散熱 板體與該承載器之間。 3. 如申請專利範圍第2項所述之晶片封裝結構，其中 U 該散熱板體與該散熱環體為一體成型。 4. 如申請專利範圍第2項所述之晶片封裝結構，其中 - 該散熱器更包括多個鰭片，其配置於該散熱板體之相對於 . 該散熱環體的一侧上。 5. 如申請專利範圍第1項所述之晶片封裝結構，其中 該導熱介質為錫膏、散熱膏、或添加二氧化矽或銀的環氧 樹脂。 6. 如申請專利範圍第1項所述之晶片封裝結構，更包 15 200820401 VIT06-0127 21927twf.doc/t 括： 多個導電凸塊，配置於該晶片與該承載器之間，·以及 一底膠層，包覆該些導電凸塊。 7.如申請專利範圍第〗項所述之以封裝結構， ^ 該承載器為電路板。 、 • 8· 一種晶片封裝結構，包括： 一承載器； (、 至^、一晶片，配置於該承载器上且電性連接至該承載 器； 一散熱器，配置於該承载器上，其中該散熱器與該承 載器共同形成一密閉空間，直該晶片位於該密閉空間内； 以及 一導熱介質，位於該密閉空間内，其中該導熱介質與 该散熱器之内表面相接觸。 9·如申請專利範圍第8頊所述之晶片封裝結構，其中 該散熱器包括： 〇 一散熱板體；以及 放熱環體，配置於該散熱板體上，其中該散熱環體 _ 與該散熱板體共同形成一凹槽，且該散熱環體位於該散熱 _ 板體與該承載器之間。 … 10·如申請專利範圍第9項所述之晶片封裝結構，其中 该散熱板體與該散熱環體為/體成型。 U•如申請專利範圍第9項所述之晶片封裝結構，其中 該散熱器更包括多個鰭片，其配置於該散熱板體之相對於 16 200820401 VIT06-0127 21927twf.doc/t 該散熱環體的一侧上。 12·如申請專利範圍第8項所述之晶片封 該導熱介質為錫膏、散熱膏、或添加二氧化^^冓，其中 樹脂。 或銀的環氧 括：.如申請專利範圍第8項所述之晶片封裝結構，更包 多個導電凸塊，配置於該晶片與該承载器 一底膠層，包覆該些導電凸塊。 扣日】；以及 14.如申請專利範圍第8項所述之晶 該承載器為電路板。 攻、、、。構，其中 15· —種晶片封裴結構的製造方法，包 提供一承載器； β 將至少一晶片配置於該承載器上； 電性連接該晶片與該承載器·， 將-散熱環體配置於該承载器上 繞該晶片； 又行^政熱環體圍 Ο 將一導熱介質填滿該散埶環 覆蓋======，_散熱板體 與該承載器所共同形成的= 空 16·如申請專利範圍第】 ^曰 造方法，其中該晶片配置、j14之晶片封裝結構的製 載器的步聽括： 器上且連接至該承 17 200820401 YIT06-0127 21927twf.doc/t 於該晶片上形成多個導電凸塊； 將該晶片配置於該承載器上，使得該些導電凸塊電性 連接於該晶片與該承載器之間；以及 形成一底膠層，以包覆該些導電凸塊。 - 17.如申請專利範圍第15項所述之晶片封裝結構的製 . 造方法，其中在將該導熱介質填滿該容置空間的步驟之 後，更包括將該導熱介質内部的氣體抽離。 18. 如申請專利範圍第17項所述之晶片封裝結構的製 : 造方法，其中該導熱介質為固態或液態，且將該導熱介質 内部的氣體抽離的方式為真空抽取。 19. 如申請專利範圍第17項所述之晶片封裝結構的製 造方法，其中該導熱介質為液態，且將該導熱介質内部的 氣體抽離的方式包括加熱該導熱介質。 20. 如申請專利範圍第17項所述之晶片封裝結構的製 造方法，其中在將該導熱介質内部的氣體抽離的步驟之 後，更包括再填入該導熱介質，以填滿該容置空間且包覆 iJ 該晶片。 18
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