CN102668075B - 带有焊料扩散保护的半导体芯片器件 - Google Patents

带有焊料扩散保护的半导体芯片器件 Download PDF

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Publication number
CN102668075B
CN102668075B CN201080057868.5A CN201080057868A CN102668075B CN 102668075 B CN102668075 B CN 102668075B CN 201080057868 A CN201080057868 A CN 201080057868A CN 102668075 B CN102668075 B CN 102668075B
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semiconductor chip
main limit
thermal interfacial
interfacial material
solder
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CN102668075A (zh
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迈克尔·Z·苏
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Abstract

公开了使用焊料型热材料（90）为半导体器件建立传热途径的各种方法和装置。在一方面，提供了一种制造方法，包括提供具有基片和延伸到基片中第一距离的第一有源电路部分（40）的第一半导体芯片（20）。在第一半导体芯片（20）中形成抑制焊料扩散的屏障（135），该屏障（135）围绕该第一有源电路部分（40）但与该第一有源电路部分（40）横向分开并且延伸到基片中比该第一距离更大的第二距离。

Description

带有焊料扩散保护的半导体芯片器件
技术领域
本发明一般性地涉及半导体加工，特别涉及用于半导体芯片封装的热界面材料结构及其制造方法。
背景技术
很多现有的集成电路作为多个管芯形成在一个共同的晶片上。在管芯上形成电路的基本处理步骤结束后，单个的管芯（die）被从晶圆分离开来。然后，分离的管芯通常被安装在诸如电路板之类结构上，或以某种形式的外壳封装。
一个经常使用的封装包括在其上安装了管芯的基片。基片的上表面包括电气互连。管芯用多个焊盘制造。一批焊点被提供在管芯的焊盘与基片互连之间以建立欧姆接触。在管芯安装到基片上之后，盖被连接到基片上以覆盖管芯。诸如微处理器等一些传统的集成电路产生数量可观的热量，热量必须传递走以避免器件停机或损坏。盖既作为防护罩又作为传热途径。
为了提供从集成电路到盖的传热途径，将热界面材料放置在集成电路的上表面上。在理想的情况下，热界面材料充分接触集成电路的上表面和盖的覆盖集成电路的下表面的部分。传统的热界面材料包括各种类型的焊膏，在某些情况下包括金属。凝胶型热界面材料包括与诸如铝之类的热传导粒子一起散置的聚合物基体。最近，设计师们开始转向作为一种热界面材料的焊接材料，特别是用于高功率高温度的芯片。
如铟之类的焊料热界面材料具有对高功率高温度的管芯起很好作用的良好的热性能。然而，铟对硅表现出相对较差的附着性。为了方便与铟粘接，可在硅片背面设置有金属叠层（metalstack），金属叠层包括容易粘接到硅上的层、很容易湿化铟的层以及或许是一个或多个中间屏障层或其它层。在切成管芯前，管芯的整个晶圆可被设置为具有各自的金属叠层。为了在传统焊料热界面材料和半导体芯片和支撑它的盖之间建立良好的热接触，进行回流焊过程以湿化适用面。
堆叠的管芯为焊料热界面材料的集成提出了另外的技术挑战。相对于底层的封装基片，堆叠的管芯设置是非平面的，但经常希望在焊料热界面材料、每一个芯片和盖之间为热接触。这可将堆叠的管芯的最上面的外侧壁暴露从而使焊料可能扩散进入关键的电路结构。
本发明涉及克服或减少一个或多个上述缺点的影响。
发明内容
根据本发明的一个方面，提供了一种制造方法，包括提供具有基片和延伸到基片中第一距离的第一有源电路部分的第一半导体芯片。第一半导体芯片中形成屏障，该屏障围绕第一有源电路部分但与第一有源电路部分横向分开并且延伸到基片中比第一距离更大的第二距离。
根据本发明的另一个方面，提供了一种制造方法，包括连接具有第一外围壁的第一半导体芯片和具有第二外围壁的第二半导体芯片，其中在第一半导体芯片和第二半导体芯片之间有间隙。形成覆盖第一半导体芯片的至少第一外围壁的屏障层。在第一外围壁的周围安置焊料型热界面材料。屏障层抑制焊料型热界面材料扩散进入第一外围壁。
根据本发明的另一个方面，提供了一种制造方法，包括：连接具有第一主边和第二主边以及第一外围壁的第一半导体芯片和具有第一主边和第二主边的第二半导体芯片，其中在第一半导体芯片和第二半导体芯片之间有间隙。在第一半导体芯片的第二主边上安置第一焊料型热界面材料，在第二半导体芯片的第一主边上安置第二热界面材料部分但与第一焊料型热界面横向分开以留下空间。
根据本发明的另一个方面，提供了一种装置，该装置包括具有基片和延伸到基片中第一距离的第一有源电路部分的第一半导体芯片。屏障在第一半导体芯片中，其围绕第一有源电路部分但与第一有源电路部分横向分开并且延伸到基片中比第一距离更大的第二距离。
根据本发明的另一个方面，提供了一个装置，包括具有第一主边和第二主边和第一外围壁的第一半导体芯片。第二半导体芯片包括连接到第一半导体芯片的第一主边的第一主边、第二主边和第二外围壁，在该第一半导体芯片和该第二半导体芯片之间有间隙。屏障层覆盖第一半导体芯片的至少第一外围壁，并且焊料型热界面材料围绕第一外围壁。屏障层抑制焊料型热界面材料扩散进入第一外围壁。
根据本发明的另一个方面，提供了一种装置，该装置包括具有第一主边和第二主边以及第一外围壁的第一半导体芯片。第二半导体芯片包括连接到第一半导体芯片的第一主边的第一主边、第二主边和第二外围壁，在该第一半导体芯片和该第二半导体芯片之间有间隙。第一焊料型热界面材料部分被安置在第一半导体芯片的第二主边上，并且第二热界面材料部分被安置在第二半导体芯片的第一主边上但与第一焊料型热界面横向分开以留下空间。
附图说明
一旦阅读下面的详细说明和参照附图，本发明的上述及其它优势将变得明显。在附图中：
图1是包括堆叠的半导体芯片的半导体芯片器件的一个典范的实施例的剖视图;
图2是以更大的放大倍数表示的图1的一部分；
图3是从图1中所描述的方向翻转的半导体芯片之一的部分分解图的视图;
图4是经受典范的屏障沟槽形成的半导体芯片之一的剖视图;
图5是描绘在沟槽内沉积屏障材料的与图4类似的剖视图;
图6是描绘典范的屏障材料的平坦化的与图5类似的剖视图;
图7是与图5类似、但描绘屏障沟槽的替换的典范形成的剖视图;
图8是经受典范的籽晶层的形成的、图1中所绘的其它半导体芯片的剖视图;
图9是描绘掩膜形成的、与图8类似的剖视图;
图10是与图9类似的、但描绘在半导体芯片上的典范的堤的形成的剖视图;
图11是堆叠的半导体芯片的剖视图;
图12是与图11类似的、描绘在半导体芯片的堆叠上的焊料型热界面材料的安置的剖视图;
图13是包括堆叠的半导体芯片的半导体芯片器件的替换的典范的实施例的剖视图;
图14是经受屏障层的施加的图13的半导体芯片的剖视图;
图15是包括堆叠的半导体芯片的半导体芯片器件的另一个替换的典范的实施例的剖视图;
图16是在16-16部分取的图15的剖视图;
图17是包括堆叠的半导体芯片的半导体芯片器件的另一个替换的典范的实施例的剖视图;
图18是在18-18部分取的图17的剖视图;
图19是与图18类似的、但描绘在高分子热界面材料的施加之前的处理阶段的剖视图。
具体实施方式
本文说明了半导体芯片器件的各个实施例。一个例子包括安装到电路板上的两个堆叠的半导体芯片。散热器或盖覆盖着芯片。焊料型热界面材料提供了在盖和半导体芯片之间的传热途径。上面的半导体芯片被提供了屏障，该屏障抑制焊料型热界面材料扩散到敏感的电路结构。现在将说明更多的细节。
在下面说明的附图中，在相同的元件出现在一个以上的图中时，参考数字一般重复。现在转到附图，特别是在图1，在其中显示了包括安装在电路板25和由散热器或盖30围绕的堆叠的半导体芯片15和20的半导体芯片器件10的典范的实施例的剖视图。虽然描述了两个半导体芯片15和20，但应理解，此处公开的技术可被应用到更大的数字，无论是堆叠的或以其它方式布置的半导体芯片。半导体芯片15包括主边32和33及外围壁34。半导体芯片20类似地包括主边35和36及外围壁37。半导体芯片15和20包括各自的有源电路区35和40，有源电路区35和40的厚度分别与芯片15和20的整体的厚度相比是相对较小的。有源电路区38和40包括为单个芯片15和20和诸如金属化或其它类型的互连层和层间绝缘层之类多个互连层提供功能的各种逻辑电路和其它类型的电路。半导体芯片15可通过多个导电柱45电连接到半导体芯片。可选地，其它类型的管芯-管芯互连可被使用，诸如焊点、导电柱加焊料（conductivepillarplussolder）或其它类型的互连。为了为半导体芯片15和20提供电源、接地和信号的输入/输出，半导体芯片15可被提供在导电垫55处终止的多个穿孔50。半导体芯片15可通过多个焊点60安装到电路板25，多个焊点通过冶金方式结合到相应的多个导电垫65。底部填充材料层70可介于半导体芯片15和电路板25之间，以减轻CTE差的影响。
半导体芯片15和20可以是诸如微处理器、图形处理器、结合的微处理器/图形处理器、专用集成电路、存储器件或类似物之类的在电子学中使用的许多不同类型的电路器件中的任何一种，并且可以是单核或多核或甚至堆叠着额外的管芯。半导体芯片15和20可用诸如硅或锗之类批量（bulk）半导体或诸如绝缘体上硅（silicon-on-insulator）材料之类的在绝缘材料上的半导体建造。
电路板25可以是半导体芯片封装基片、电路卡或几乎任何其它类型的印刷电路板。虽然单片式结构可用于电路板25，但更典型的配置将利用增层（build-up）设计。就这一点而言，电路板25可由中间核构成，在中间核之上形成一个或一个以上的增层，在中间核之下形成另外的一个或多个增层。核自身可包含一个或多个层的堆叠。如果作为半导体芯片封装基片实现，则在电路板25中的层的数量可以在从4到16或更多之间改变，然而少于4的层数也可被使用。所谓“无核”（“coreless”）的设计也可使用。电路板25的层可包括绝缘材料，如各种穿插着金属互连的公知的环氧树脂。非增层的多层配置可被使用。可选地，电路板25可由公知的陶瓷或其它适宜于封装基片或其它印刷电路板的材料构成。电路板115被提供了很多导体走线和孔以及其它结构（不可见），以便在半导体芯片110和诸如例如另一个电路板之类其它器件之间提供电源、接地以及信号传输。电路板25可通过诸如所描绘的球栅阵列之类的输入/输出阵列的方式电连接到另一个器件（未显示）。球栅阵列包括通过冶金方式结合到各自的球垫80的多个焊球75。球垫80通过未示出的多个互连走线和孔以及其它结构连接到导体垫65。可选地，其它类型的互连可用于电路板25，诸如针栅阵列、连接盘网格阵列或其它类型的互连结构。
盖30可以是所描绘的浴缸设计，可以是顶帽设计或所期望的一些其它的结构。盖30可由期望的公知的陶瓷或金属材料构成。一些典范的材料包括镀镍铜、阳极氧化铝、铝-硅-碳、氮化铝、氮化硼或类似物。盖25可以由公知的触变胶、环氧树脂、其他类型的聚合物甚至焊料构成的粘合剂85固定到基片20。
焊料型热界面材料90被安置在半导体芯片20和盖30的下表面95之间。可形成多种粘附层，以促进热界面材料90湿化到盖30和半导体芯片15和20的各种表面上。例如，半导体芯片15的主边32可被提供粘附层105。粘附层105可以是单片或层压板。类似地，盖30的下表面95可被提供粘合层110，半导体芯片20的主边35可被提供粘附层120，这两粘附层可以是单片或层压板。粘附层105、110和115的更多细节将在下面提供。焊料型热界面材料90可由诸如例如铟、铟焊料、锡-银、铋-锡、其它锡焊料、镓加聚合物或类似物之类适用于热界面材料的多种焊接材料构成。
依然参照图1，堤125被安置在半导体芯片15和20之间，围绕互连结构45，起作用以防止热界面材料90灌注到芯片15和20之间的空间130，否则在那里可能有电气短路发生。堤125可由诸如铜、银、铂、金、铝、钯、这些的合金或类似物等各种材料构成。此外，屏障135在半导体芯片20的周边中形成，沿半导体芯片20的周边延伸，作为屏障起作用以抵制不要的热界面材料90扩散进入特别是靠近有源器件区40的半导体芯片20。如在下面更详细地描述的那样，屏障135可以由诸如例如致密硅氮化物、氮氧化硅、具有大量抑制金属扩散的植入离子的硅等多种材料构成。
图1的由虚线椭圆形140外切的一部分将以大的放大显示在图2中并用于描述堤125和屏障135的更多细节。现在关注图2。因为图2有比图1更大的放大倍率，所以有几个在图1中不可见的一些特征在图2中是可见的。例如，互连结构45可包括通过热粘接、焊接或其它一些技术合在一起的各自的柱145和150。柱145被连接到半导体芯片20的导体垫155，并且柱150被连接到半导体芯片15的导体垫160。半导体芯片15和20的有源器件区38和40的一小部分是可见的。如上所述，希望避免焊料型热界面材料90的部分或粒子165扩散入邻近其有源器件区40的半导体芯片20的部分170。屏障135被设计为阻碍粒子165的这类扩散。屏障没有必要阻碍所有的扩散。因此，屏障135最好是被提供具有比有源器件区40的厚度x2大的高度x1。因为有源器件区40的厚度通常是半导体芯片20的整体厚度的一小部分，所以，这是很容易做到的。由虚线的L形区域175示出了热界面材料粒子165的假想的扩散。事实上，由于更接近有源器件区40区170被保护不被扩散，有一些铟粒子165在半导体芯片20的部分180附近扩散是没有问题的。请注意，半导体芯片20被安置在半导体芯片15上，使屏障135和堤125大体上垂直对齐。垂直对齐不是绝对必要的。在半导体芯片15和20之间的空间130可以是空隙，或充填所需要的某些类型的填充材料层。
粘附层105的一小部分是可见的。粘附层105可由适合湿化被选作热界面材料90的材料和适合半导体芯片15上表面100的各种材料构成。在一个典范的实施例中，粘附层105可包括铜和金的层压板。事实上，再次暂时参考图1，半导体芯片20的粘附层120可包括同一种类型的材料。在典范的实施例中，粘附层120可包括在半导体芯片20上形成的铝膜、在铝膜上形成的钛膜、在钛膜上形成的镍-钒膜和在镍-钒膜上形成的金膜。铝膜提供了与硅的有利的附着力。钛膜提供了屏障层以防止金和铟迁移到半导体芯片20中并促进与镍-钒膜的附着，镍-钒膜提供了与金的理想的附着力和抑制扩散入钛层的屏障。金膜为铟提供了理想的润湿表面。粘附层110可由相同类型的材料或例如由金或金合金单独构成。
现在可以通过参考图3理解堤125、屏障135和半导体芯片20的更多细节，图3是示出了从半导体芯片20分解的堤125和屏障135的部分分解图的视图。请注意，所示出的半导体芯片20为已按图1中所描述的方向翻转过来了。因此，互连结构45和有源器件区40的一部分是可见的。在这一说明的实施例中，屏障135可由例如由致密氮化硅构成的框架状结构构成。屏障135在框架状沟槽185中形成，沟槽185是在有源器件区40的外侧的半导体芯片20的边190中形成。堤125可能有通常类似（track）屏障135的占板面积（footprint）的占板面积，并且堤和屏障125和135一般都会有诸如方形、长方形之类类似半导体芯片20的占板面积的占板面积。有关沟槽185的形成的另外的细节将结合后面的图进行说明。
现在参考图4，图4是从图1中所描绘的方向翻转过来的半导体芯片20的剖视图，可通过用于材料去除的各种技术在半导体芯片20中形成沟槽185。在典范的实施例中，蚀刻掩膜195可应用于半导体芯片20的表面190上，进行图案化以具有口200，口200被安置和成型为具有沟槽185所需的占板面积的占板面积。掩膜195保护下伏的有源器件区40。在这一阶段中，半导体芯片20可能已经被提供了粘附层120。应该理解，可以按所需在晶圆级或裸片级阶段在半导体芯片上执行建立屏障135的过程步骤。继在掩膜195中的口200的光刻图案化之后，可以执行深槽蚀刻以在半导体芯片20中建立沟槽185。沟槽185有利地蚀刻到x1的深度，如上所述,x1有利地比有源器件区40的厚度x2大。深槽沟槽蚀刻可以由等离子体刻蚀执行，参数选择为提供一个相对各向异性的刻蚀轮廓。典范的蚀刻化学品包括CF4、SF4、NF3、H2/Cl2/SiCl4或类似物。可选地，激光烧蚀可用来形成带防护罩或不带防护罩的沟槽185。
现在参照图5，在图5中所绘的掩膜195被剥离，另一个光刻掩膜205形成在有源器件区40上，并且进行沉积过程以在沟槽185中建立致密的氮化硅210。致密的氮化硅210可以用具有或不具有等离子体增强的化学气相沉积法或其它沉积技术沉积。当然，一些氮化硅210将盖住掩膜205。在沉积之后，可以进行蚀刻工艺以去除致密的氮化硅210的过量的部分，并且掩膜205可以如图6所示剥离以离开完成了的屏障135。可通过使用诸如CF4、SF4或NF3之类的化学品的干化蚀刻去除多余的氮化硅210。可以使用带有例如热磷酸浸液的湿化蚀刻。这样的湿化蚀刻也会去除掩膜210。掩膜205可以通过灰化、溶剂剥离或其它掩膜去除技术去除。在这一阶段，半导体芯片20特别是其有源器件区40可以被提供有导电柱145和安装在图1和图2中描绘的半导体芯片15上的倒装芯片。
正如在本文的别处指出的，可通过沉积诸如致密氮化硅之类特殊材料之外的方式形成屏障135。例如并且如在图8中所绘，屏障可通过离子注入来形成。图7描绘了装有具有如上所述的图案化的口200的光刻掩膜195的半导体芯片15的与图4类似的剖视图。在这里，可植入离子215以建立屏障135’来取代蚀刻和后续的材料沉积过程。用于植入的选定的离子种类215的类型有多种。在典范的实施例中，离子215可以是例如钽或钛。这些品种可以通过动能转移破坏半导体芯片的植入部分的晶格结构。被破坏的区变得更能抵制焊料型热界面材料90扩散进入邻近有源器件区40的芯片20的部分中。诸如钽和钛之类品种是具成本效益的，并且在半导体制造中很好理解。合适的能量范围可以是约300keV到1.0MeV。在植入之后，掩膜195通过灰化、溶剂剥离或类似方式去除。
现在关注用于在图1和2中所描述的堤125的典范制作过程的说明。在这方面，关注现在转向图8，图8是与在与图1和2中所示相同的方向上的半导体芯片15的剖视图。半导体芯片15被描绘成处于在图1所绘的在向其施加半导体芯片20和施加用来将芯片15连接到电路板25的连接焊点60之前的处理阶段。在这个阶段，半导体芯片15的有源器件区38已经被提供了导体螺栓150以及全通硅穿孔50和导体垫55。在互连螺栓150和整个有源器件区38上形成了光刻掩膜220。接着，将一个非常薄的铜晶种层225应用于半导体芯片15的主边32。可使用铜之外的材料。可通过电镀、溅射或类似方式应用种层225。种层225的目的是为了方便在图1和2中所描绘的堤125的后续电镀。
接着，如图9所绘，在种层225上形成第二光刻掩膜230，但不与其同延以留下沟槽235，沟槽235具有随后形成的堤的期望的占板面积。沟槽235可通过公知的光刻工艺在掩膜230中图案化。在掩膜230的光刻处理期间，掩膜220留在原位。
下面，如图10所绘，电镀工艺可用于在位于光刻掩膜230和光刻掩膜220之间的沟槽235中建立堤125。种层225用于建立必要的电气通路，以便于堤125的电镀。在典范的实施例中，堤125可由铜构成。然而，可以使用诸如铜、金、铂、钯、铝或类似物的合金之类的其它导体材料。事实上，可使用诸如物理气相沉积或其它技术之类电镀技术之外的技术来建立堤125。由于堤125构成了可横向离开有源器件区35并坐在芯片15的表面100之上的结构，堤125也可以被作为单独的组件制作，此后单独的组件被放在半导体芯片15上并用例如粘合剂、焊料或其它材料的连接技术固定在其上。在堤125形成后，光刻掩膜220和235可通过灰化、溶剂剥离或类似方式剥离。
现在参照图11，半导体芯片20可安装到半导体芯片15和加入的各自的导体螺栓145和150以建立多元互连结构45。如果铟被选作随后使用的焊料的热界面材料，那么粘附层105可通过沉积诸如金的湿化铟的膜来完成。在这里，金膜240可通过例如闪（flash）镀层工艺或适于沉积金膜的其它工艺应用于之前形成的铜晶种层225。防护的光刻掩膜245可应用于半导体芯片15的相反侧250，以避免金沉积在导体垫55上。堤125将限制金膜240的电镀。如果需要，建立金膜240的电镀过程可根据需要被用来在半导体芯片20上建立粘附层120的最上的部分。正如在本文的别处所说明的，在半导体芯片20中的屏障135可以与堤125垂直对齐。在沉积金膜240之后，掩膜880可使用灰化、溶剂剥离或类似方式剥离。
现在关注图12。热界面材料90可以以各种不同的方式应用在半导体芯片15和20的组合上。例如，热界面材料90可作为预制品被置位在半导体芯片20的粘附层120上。此后，在图1中描绘的盖30可被置位在热界面材料90上，回流过程被建立，以使热界面材料90的部分液化并随后湿化粘附层105。如果需要，焊料热界面材料90的预制品可以在将其安置在半导体芯片20上以促进对粘附层105更均匀湿化之前被设置成浴缸的形状。在另一个选项中，焊料热界面材料的预制品90可先安装到盖30然后盖30可以被置位在电路板25上。在这一选项中，如图1所示，热界面材料90和盖30将在半导体芯片15和20安装到电路板25以及建立焊点60所需的任一焊回流进行之后被置位在电路板25上。
现在通过参照是剖视图的图13可以理解半导体芯片器件260的另一个典范的实施例。半导体芯片器件260可以与在图1和2中描绘的半导体芯片器件10的典范的实施例共享几个属性。在这方面，如本文的别处所述，半导体芯片15和20可堆叠并安装到电路板25上。盖30可固定在电路板25上，焊料的热界面材料90可用于促进传热。然而，屏障层265的覆盖层可应用在半导体芯片15和半导体芯片20上，以替代利用在图1和2中描绘的屏障135来抑制热界面材料90扩散进入邻近其有源器件区40的芯片20的部分。层265有利地由湿化焊料型热界面材料90的材料或多种材料构成。在典范的实施例中，层265可由金构成。如果需要，为了方便层265的粘附，种层270可应用在芯片15的上表面100和侧边275上，并且类似的种层280可应用在半导体芯片20的主边35和外围壁37上。如果需要，种层280可以由通常会被应用到芯片20的主边35的背面金属堆叠的各层构成。如在本文的别处所述，堤125可形成在半导体芯片15上并用来防止粘附层265侵入在芯片20和15之间的空间130。
将结合图14说明粘附层265的形成。如上所述，为促进到半导体芯片15和20的粘附层265的湿化，半导体芯片15可被提供种层270，种层270可使用与如上结合在图8中所描绘的种层225的制造相同的基本过程制造。然而，种层270将制作为沿边275向下延伸。此外，粘附层280可与在芯片20上的背面金属化薄板结合形成，或按需要作为独立的过程来形成。材料点是粘附层280沿芯片20的外围壁37向下延伸的点。在粘附层270和280准备就绪后，芯片20可使用上面所述的技术结合在图1和2中所描绘的实施例安装到芯片15。接着，合适的掩膜290可应用到芯片15的表面250，并且粘附层265层应用在芯片15和20的没有掩膜的部分上。粘附层265可由适于湿化以后要应用的热界面材料的材料构成。在典范的实施例中，粘附层265可由金构成，并使用公知的电镀工艺施加。在粘附层265施加之后，掩膜290可通过灰化、溶剂剥离或类似方式剥离。在粘附层265准备就绪后，芯片15和20的堆叠可安装到在图13中描绘的电路板25上，盖30和焊料的热界面材料90可如在本文的别处所述那样安装。粘附层265和如果存在的种层280相结合提供了屏障以阻碍焊料的热界面材料90扩散到在图13所示的邻近其有源器件区40的半导体芯片20的部分中。
现在通过参照是剖视图的图15可以理解半导体芯片器件300的另一个替代的典范的实施例。半导体芯片器件300可以包括上述以堆叠方式安装在电路板25上和如本文的别处所述但有一些值得注意的例外的用盖30覆盖的半导体芯片15和20。在这一个说明的实施例中，在半导体芯片15和20与盖30之间的传热途径由两个热界面材料部分305和310提供。热界面材料部分305提供了在半导体芯片15和盖30之间的传热途径，热界面材料部分310提供了在半导体芯片20和盖30之间的传热途径。间隙315被有意地提供在部分305和部分310之间，以避免任何热界面材料扩散进入邻近其有源器件区40的芯片20的部分中的潜在性。热界面材料部分305相应地比热界面材料部分310厚，并湿化到在芯片15的主表面32上形成的外围粘附层320上和在盖30的下表面95上形成的外围粘附层320上。热界面材料部分310被湿化到芯片20的粘附层120和在盖30的下表面95上的中央粘附层325上。热界面材料部分305和310可相应地在将盖30定位在电路板25之前作为预制品安装到盖30上，或作为预制品先安装在芯片15和20上。要谨慎小心，以确保热界面材料部分305在回流期间不侵入在芯片15和20之间的空间130以通过冶金方式将热界面材料部分305和310结合到多个粘附层320和325上。
现在通过参照是取自图15在断面16-16的剖视图的图16可以理解外围粘附层320和中央粘附层部分325的更多细节。周边部分320和中央部分325由间隙327分开。像本文中公开的其它粘附层一样，粘附层320和325可由湿化置于上面和下面的任何膜的材料构成。在典范的实施例中，粘附层320和325可由金构成。在周边部分320和盖的侧壁335之间的间隙330是可选的。
现在通过参照是剖视图的图17可以理解半导体芯片器件340的另一个替换的典范的实施例。半导体芯片器件340的说明性实施例可共享与在图15和图16中描绘的半导体芯片器件300相同的并在本文的别处说明的属性。在这方面，器件340可包括以堆叠方式安装在电路板25上，由盖30封闭，并由热界面材料部分305和310提供传热途径的半导体芯片15和20。然而，在说明的实施例中，盖30和热界面材料部分可被改性305，以使高分子热界面材料345被注入到盖30内部的各种腔内。因为图17描绘的是在高分子热界面材料345注入之后的半导体芯片器件340，所以，热界面材料部分305是不清晰的，从而以虚线（phantom）显示。为了方便高分子热界面材料345的注入，盖330可被提供入口350和出口355。出口355被设计为允许空气在注射过程期间逸出。为使高分子材料345环绕半导体芯片20从而与半导体芯片15的主边32的部分接触，热界面材料部分305必须有某些种类的开口，以方便高分子热接口材料345移动进入在半导体芯片20和热界面材料部分305之间的间隙357内。
现在通过参照取自图17的断面18-18的剖视图的图18可以理解热界面材料部分305的更多细节。请注意，断面18-18通过入口350、热界面材料部分305、半导体芯片20、注入的热界面材料345、盖30和间隙357。请注意，热界面材料部分305被形成为带有开口360和365，以方便热界面材料345的注入不只进入在热界面材料部分305和盖壁之间的空间还进入在半导体芯片20和热界面材料部分305之间的间隙357中。热界面材料345可由适合热界面材料的诸如例如混合氧化锌的硅橡胶之类的各种高分子材料构成。可选地，可以使用在硅橡胶之外的柔性的基本材料和传导热但不导电的粒子。
简要地观察与图18相同的、但没有注入高分子热界面材料345的剖视图可能是有用的。在这方面，现在关注图19，图19示出了在热界面材料部分305中的开口360和365。应该明白，粘附层320、325和315应该以与热界面材料部分相同的占板面积形成，因而是不连续的，所以开口360和365将被建立。
虽然本发明可能会有各种修改和替换形式，但具体的实施例已通过举例的方式在附图中示出，并已在文中做了详细说明。然而，应理解，本发明的目的不是只限于所公开的特定形式。相反，本发明包含在由下面附加的权利要求所定义的本发明的精神和范围中的所有改变、等同和替代方案。

Claims (20)

1.一种用于制造半导体芯片器件的方法，包括：
提供包括具有第一主边和第二主边的基片和延伸到该基片中第一距离的第一有源电路部分(40)的第一半导体芯片(20)；
在所述第一半导体芯片(20)中形成屏障(135)，所述屏障(135)围绕所述第一有源电路部分(40)但与所述第一有源电路部分(40)横向分开并且延伸到所述基片中比所述第一距离更大的第二距离；
用多个互连将第二半导体芯片(15)连接至所述第一半导体芯片(20)，所述第二半导体芯片具有第三主边，所述第三主边面向所述第一半导体芯片的所述第二主边但是与所述第一半导体芯片的所述第二主边分开一间隙；以及
在所述第一半导体芯片的所述第一主边上和所述第三主边中与所述互连横向分开的一部分上安置焊料型热界面材料(90)。
2.如权利要求1所述的方法，包括在所述第一半导体芯片和所述第二半导体芯片之间安置堤(125)并且所述堤(125)围绕所述第一有源电路部分(40)，以防止材料进入间隙(130)。
3.如权利要求1所述的方法，其中，所述形成所述屏障(135)包括在所述第一半导体芯片(20)中形成沟槽(185)和在所述沟槽中淀积绝缘材料(210)。
4.如权利要求1所述的方法，其中，所述形成屏障(135)包括在所述基片的部分中植入阻碍金属粒子流动的离子(215)。
5.一种用于制造半导体芯片器件的方法，包括：
连接包括第一外围壁(37)的第一半导体芯片(20)和包括第二外围壁(34)的第二半导体芯片(15)，其中在所述第一半导体芯片和所述第二半导体芯片之间有间隙(130)；
形成覆盖所述第一半导体芯片的至少所述第一外围壁(37)的屏障层(265)；以及
在所述第一外围壁(37)的周围安置焊料型热界面材料(90)，所述屏障层(265)抑制所述焊料型热界面材料扩散进入所述第一外围壁。
6.如权利要求5所述的方法，其中，所述第一半导体芯片(20)包括第一有源电路部分(40)，该方法包括在所述第一半导体芯片和所述第二半导体芯片之间安置堤(125)并且该堤(125)围绕所述第一有源电路部分(40)，以防止材料进入所述间隙(130)。
7.如权利要求5所述的方法，其中，第一半导体芯片(20)包括第一主边和第二主边(35)(36)并且所述第二半导体芯片(15)包括第一主边和第二主边(32)(33)和第二外围壁(34)，该方法包括形成屏障层(265)以覆盖所述第一半导体芯片(20)的所述第二主边(36)、所述第二半导体芯片(15)的所述第一主边(32)的一部分和所述第二外围壁(34)。
8.一种用于制造半导体芯片器件的方法，包括：
连接包括第一主边和第二主边以及第一外围壁的第一半导体芯片(20)和包括第一主边和第二主边的第二半导体芯片(15)，其中在所述第一半导体芯片和所述第二半导体芯片之间有间隙；
在所述第一半导体芯片的所述第二主边(35)上安置第一焊料型热界面材料部分(310)；以及
将第二热界面材料部分(305)安置在所述第二半导体芯片(15)的所述第一主边(32)上但将所述第二热界面材料部分(305)与所述第一焊料型热界面材料部分(310)横向分开以留下空间。
9.如权利要求8所述的方法，包括在所述空间中安置高分子热界面材料(345)。
10.如权利要求8所述的方法，包括放置与所述第一焊料型热界面材料部分和第二焊料型热界面材料部分热接触的散热器(30)。
11.一种半导体芯片器件，包括：
第一半导体芯片(20)，其包括具有第一主边和第二主边的基片和延伸到该基片中第一距离的第一有源电路部分(40)；
在所述第一半导体芯片(20)中的屏障(135)，该屏障(135)围绕所述第一有源电路部分(40)但与所述第一有源电路部分(40)横向分开、并且延伸到所述基片中比第一距离更大的第二距离；
连接到所述第一半导体芯片的第二半导体芯片，所述第二半导体芯片具有第三主边，所述第三主边面向所述第一半导体芯片的所述第二主边但是与所述第一半导体芯片的所述第二主边分开一间隙；
将所述第二主边连接到所述第三主边的多个互连；以及
所述第一半导体芯片的第一主边上和所述第三主边中与所述互连横向分开的一部分上的焊料型热材料。
12.如权利要求11所述的半导体芯片器件，包括安置在所述第一半导体芯片和所述第二半导体芯片之间的并围绕所述第一有源电路部分以防止材料进入所述间隙(130)的堤(125)。
13.如权利要求11所述的半导体芯片器件，其中，所述屏障(135)包括在所述第一半导体芯片(20)中的沟槽(185)和在所述沟槽中的绝缘材料(210)。
14.如权利要求11所述的半导体芯片器件，其中，所述屏障(135)包括含有阻碍金属粒子流动的植入离子(215)的所述基片的一部分。
15.一种半导体芯片器件，包括：
第一半导体芯片(20)，其包括第一主边和第二主边(35)(36)和第一外围壁(37)；
第二半导体芯片(15)，其包括连接到所述第一半导体芯片(20)的所述第一主边(36)的第一主边(32)、第二主边(33)和第二外围壁(34)，在所述第一半导体芯片和所述第二半导体芯片之间有间隙(130)；
屏障层(265)，其覆盖所述第一半导体芯片的至少所述第一外围壁；和
围绕所述第一外围壁的焊料型热界面材料(90)，所述屏障层(265)抑制所述焊料型热界面材料(90)扩散进入所述第一外围壁(37)。
16.如权利要求15所述的半导体芯片器件，其中，所述第一半导体芯片(20)包括第一有源电路部分(40)并且所述半导体芯片器件包括安置在所述第一半导体芯片和所述第二半导体芯片之间的并围绕所述第一有源电路部分以防止材料进入所述间隙(130)的堤(125)。
17.如权利要求15所述的半导体芯片器件，其中，所述屏障层(265)覆盖所述第一半导体芯片的所述第二主边、所述第二半导体芯片的所述第一主边的一部分和所述第二外围壁。
18.一种半导体芯片器件，其包括：
第一半导体芯片(20)，其包括第一主边和第二主边以及第一外围壁；
第二半导体芯片(15)，其包括连接到所述第一半导体芯片的所述第一主边的第一主边、第二主边和第二外围壁，其中在所述第一半导体芯片和所述第二半导体芯片之间有间隙(130)；
安置在所述第一半导体芯片的所述第二主边上的第一焊料型热界面材料部分(310)；和
安置在所述第二半导体芯片(15)的所述第一主边上但与第一焊料型热界面材料部分(310)横向分开以留下空间的第二热界面材料部分(305)。
19.如权利要求18所述的半导体芯片器件，包括安置在所述空间的高分子热界面材料(345)。
20.如权利要求18所述的半导体芯片器件，其包括与所述第一焊料型热界面材料部分和第二焊料型热界面材料部分处于热接触的散热器(30)。
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WO2011084362A2 (en) 2011-07-14
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US8299633B2 (en) 2012-10-30
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