TW200708967A - External device access device - Google Patents

External device access device

Info

Publication number
TW200708967A
TW200708967A TW095120239A TW95120239A TW200708967A TW 200708967 A TW200708967 A TW 200708967A TW 095120239 A TW095120239 A TW 095120239A TW 95120239 A TW95120239 A TW 95120239A TW 200708967 A TW200708967 A TW 200708967A
Authority
TW
Taiwan
Prior art keywords
address
write
external device
read
storage unit
Prior art date
Application number
TW095120239A
Other languages
English (en)
Inventor
Takao Kawakami
Masaitsu Nakajima
Tokuzo Kiyohara
Hiroyuki Morishita
Nobuo Higaki
Yousuke Kudo
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of TW200708967A publication Critical patent/TW200708967A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bus Control (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Communication Control (AREA)
  • Microcomputers (AREA)
TW095120239A 2005-06-15 2006-06-07 External device access device TW200708967A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005175677 2005-06-15

Publications (1)

Publication Number Publication Date
TW200708967A true TW200708967A (en) 2007-03-01

Family

ID=37532167

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095120239A TW200708967A (en) 2005-06-15 2006-06-07 External device access device

Country Status (7)

Country Link
US (1) US7685351B2 (zh)
EP (1) EP1895425A4 (zh)
JP (2) JP4688822B2 (zh)
KR (1) KR20070122228A (zh)
CN (1) CN100587678C (zh)
TW (1) TW200708967A (zh)
WO (1) WO2006134804A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2120153A1 (en) * 2008-01-28 2009-11-18 Panasonic Corporation Orthogonal converter and integrated circuit
US20100318707A1 (en) * 2008-02-08 2010-12-16 Panasonic Corporation External device access apparatus, control method thereof, and system lsi
KR20120115854A (ko) * 2011-04-11 2012-10-19 에스케이하이닉스 주식회사 리페어 방법과 이를 이용한 집적회로
CN103970687B (zh) * 2013-02-05 2017-11-10 中兴通讯股份有限公司 一种访问地址处理系统及方法
US9934117B2 (en) * 2015-03-24 2018-04-03 Honeywell International Inc. Apparatus and method for fault detection to ensure device independence on a bus
CN108153703A (zh) * 2016-12-05 2018-06-12 深圳市中兴微电子技术有限公司 一种外设访问方法和装置
EP4092556A1 (en) * 2021-05-20 2022-11-23 Nordic Semiconductor ASA Bus decoder

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2618624B1 (fr) * 1987-07-24 1992-04-30 Michel Servel Systeme de commutation de multiplex temporels hybrides a memoire tampon optimisee
US5003465A (en) * 1988-06-27 1991-03-26 International Business Machines Corp. Method and apparatus for increasing system throughput via an input/output bus and enhancing address capability of a computer system during DMA read/write operations between a common memory and an input/output device
JPH0512190A (ja) * 1991-07-09 1993-01-22 Fujitsu Ltd 転送情報制御方式
US5768548A (en) 1992-04-15 1998-06-16 Intel Corporation Bus bridge for responding to received first write command by storing data and for responding to received second write command by transferring the stored data
EP0574598A1 (de) * 1992-06-13 1993-12-22 International Business Machines Corporation Datenpufferspeicher
JPH06110823A (ja) * 1992-09-28 1994-04-22 Fuji Xerox Co Ltd バス変換システムおよびバッファ装置
EP0601715A1 (en) 1992-12-11 1994-06-15 National Semiconductor Corporation Bus of CPU core optimized for accessing on-chip memory devices
JPH08288965A (ja) * 1995-04-18 1996-11-01 Hitachi Ltd スイッチングシステム
JP3061106B2 (ja) * 1996-02-28 2000-07-10 日本電気株式会社 バスブリッジおよびそれを備えた計算機システム
JP3206528B2 (ja) * 1997-11-17 2001-09-10 日本電気株式会社 バスブリッジ回路
JP3711432B2 (ja) 1998-04-15 2005-11-02 セイコーエプソン株式会社 周辺処理装置およびその制御方法
US6366973B1 (en) * 1999-05-03 2002-04-02 3Com Corporation Slave interface circuit for providing communication between a peripheral component interconnect (PCI) domain and an advanced system bus (ASB)
US6546451B1 (en) * 1999-09-30 2003-04-08 Silicon Graphics, Inc. Method and apparatus for decoupling processor speed from memory subsystem speed in a node controller
JP4097883B2 (ja) * 2000-07-04 2008-06-11 松下電器産業株式会社 データ転送装置および方法
JP4464029B2 (ja) 2001-04-19 2010-05-19 キヤノン株式会社 情報処理方法および制御プログラムおよび情報処理装置および周辺装置および応答方法および代理応答装置およびネットワークシステム
US20030093604A1 (en) 2001-11-14 2003-05-15 Lee Terry Ping-Chung Method of error isolation for shared PCI slots
JP2004139361A (ja) * 2002-10-18 2004-05-13 Sony Corp ダイレクトメモリアクセス装置およびその制御方法
JP4089459B2 (ja) * 2003-02-18 2008-05-28 日本電気株式会社 不在装置通知手段を備えた接続状態検出システム
KR100505689B1 (ko) * 2003-06-11 2005-08-03 삼성전자주식회사 송수신 흐름에 따라 공유 버퍼 메모리의 할당량을제어하는 송수신 네트워크 제어기 및 그 방법
US7213092B2 (en) * 2004-06-08 2007-05-01 Arm Limited Write response signalling within a communication bus

Also Published As

Publication number Publication date
US20090037779A1 (en) 2009-02-05
EP1895425A4 (en) 2009-03-18
KR20070122228A (ko) 2007-12-28
EP1895425A1 (en) 2008-03-05
JP2010244580A (ja) 2010-10-28
CN100587678C (zh) 2010-02-03
JP4688822B2 (ja) 2011-05-25
US7685351B2 (en) 2010-03-23
JPWO2006134804A1 (ja) 2009-01-08
CN101198940A (zh) 2008-06-11
WO2006134804A1 (ja) 2006-12-21

Similar Documents

Publication Publication Date Title
TW200708967A (en) External device access device
TW200634844A (en) Apparatus and methods using invalidity indicators for buffered memory
WO2006130208A3 (en) Translation information retrieval
TW200639714A (en) Nonvolatile memory card adaptable to plural specifications
WO2006041520A3 (en) De-coupled memory access system and method
GB2379538A (en) Non-volatile cache
WO2005045631A3 (en) A method and system for storing, retrieving, and managing data for tags
SG133534A1 (en) System for improving endurance and data retention in memory devices
TW200745858A (en) Unified memory and controller
TW200623125A (en) Clock signal generation apparatus for use in semiconductor memory device and its method
WO2007030808A3 (en) Limited use data storing device
TW200502756A (en) Memory device
EP1796102A3 (en) Semiconductor memory device
CA2469682A1 (en) Cache operation with non-cache memory
TW200641625A (en) Command protocol method for nonvolatile memory
TW200717527A (en) Semiconductor memory device
GB2443998A (en) Memory device activation and deactivation
WO2005006196A3 (en) Data integrety of a non valatile cache upon os cache driver operation
WO2004057865A3 (en) More user friendly time-shift buffer
TW200708950A (en) Memory management method and system
WO2006086518A3 (en) Rf tag system with single step read and write commands
EP1215678A3 (en) Semiconductor memory, and memory access method
TW200719723A (en) Apparatus and method for updating television firmware therefor
TW200627468A (en) Balanced bitcell design for a multi-port register file
WO2006120225A3 (en) Dumping data in processing systems to a shared storage