TW200636492A - Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same - Google Patents

Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same

Info

Publication number
TW200636492A
TW200636492A TW095100726A TW95100726A TW200636492A TW 200636492 A TW200636492 A TW 200636492A TW 095100726 A TW095100726 A TW 095100726A TW 95100726 A TW95100726 A TW 95100726A TW 200636492 A TW200636492 A TW 200636492A
Authority
TW
Taiwan
Prior art keywords
pci express
compensating
received data
training sequence
physical layer
Prior art date
Application number
TW095100726A
Other languages
English (en)
Other versions
TWI382317B (zh
Inventor
Soon-Bok Jang
Young-Gyu Kang
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200636492A publication Critical patent/TW200636492A/zh
Application granted granted Critical
Publication of TWI382317B publication Critical patent/TWI382317B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
TW095100726A 2005-01-10 2006-01-09 補償ｐｃｉ ｅｘｐｒｅｓｓ的位元組偏斜的方法以及其ｐｃｉ ｅｘｐｒｅｓｓ物理層接收器 TWI382317B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050001995A KR20060081522A (ko) 2005-01-10 2005-01-10 피씨아이 익스프레스의 바이트 스큐 보상방법 및 이를위한 피씨아이 익스프레스 물리 계층 수신기

Publications (2)

Publication Number Publication Date
TW200636492A true TW200636492A (en) 2006-10-16
TWI382317B TWI382317B (zh) 2013-01-11

Family

ID=36654692

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095100726A TWI382317B (zh) 2005-01-10 2006-01-09 補償ｐｃｉ ｅｘｐｒｅｓｓ的位元組偏斜的方法以及其ｐｃｉ ｅｘｐｒｅｓｓ物理層接收器

Country Status (4)

Country Link
US (1) US7434114B2 (zh)
JP (1) JP4870435B2 (zh)
KR (1) KR20060081522A (zh)
TW (1) TWI382317B (zh)

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Also Published As

Publication number Publication date
KR20060081522A (ko) 2006-07-13
US20060156083A1 (en) 2006-07-13
JP4870435B2 (ja) 2012-02-08
US7434114B2 (en) 2008-10-07
TWI382317B (zh) 2013-01-11
JP2006202281A (ja) 2006-08-03

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