TW200619952A - Semiconductor memory device having a global data bus - Google Patents
Semiconductor memory device having a global data busInfo
- Publication number
- TW200619952A TW200619952A TW094115068A TW94115068A TW200619952A TW 200619952 A TW200619952 A TW 200619952A TW 094115068 A TW094115068 A TW 094115068A TW 94115068 A TW94115068 A TW 94115068A TW 200619952 A TW200619952 A TW 200619952A
- Authority
- TW
- Taiwan
- Prior art keywords
- data bus
- global data
- lines
- memory device
- semiconductor memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20040032794 | 2004-05-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200619952A true TW200619952A (en) | 2006-06-16 |
| TWI290680B TWI290680B (en) | 2007-12-01 |
Family
ID=35374994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW094115068A TWI290680B (en) | 2004-05-10 | 2005-05-10 | A semiconductor memory device having a plurality of banks for arrangement of global data bus lines |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US7227805B2 (zh) |
| KR (1) | KR100733406B1 (zh) |
| CN (1) | CN100592421C (zh) |
| TW (1) | TWI290680B (zh) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7738307B2 (en) * | 2005-09-29 | 2010-06-15 | Hynix Semiconductor, Inc. | Data transmission device in semiconductor memory device |
| KR100668755B1 (ko) * | 2005-10-12 | 2007-01-29 | 주식회사 하이닉스반도체 | 반도체 장치 |
| US7630271B2 (en) * | 2006-11-29 | 2009-12-08 | Hynix Semiconductor Inc. | Semiconductor memory device including a column decoder array |
| GB2444276B (en) * | 2006-12-02 | 2009-06-03 | Schlumberger Holdings | System and method for qualitative and quantitative analysis of gaseous components of multiphase hydrocarbon mixtures |
| KR100990140B1 (ko) * | 2007-09-28 | 2010-10-29 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 |
| KR101393309B1 (ko) | 2008-02-18 | 2014-05-09 | 삼성전자주식회사 | 복수개의 버스 라인들을 구비하는 반도체 장치 |
| KR101047053B1 (ko) * | 2009-06-18 | 2011-07-06 | 주식회사 하이닉스반도체 | 반도체 집적회로 |
| CA2789648C (en) | 2010-02-11 | 2018-08-21 | Sony Corporation | Mapping apparatus and method for transmission of data in a multi-carrier broadcast system |
| US8472279B2 (en) | 2010-08-31 | 2013-06-25 | Micron Technology, Inc. | Channel skewing |
| KR20130091034A (ko) * | 2012-02-07 | 2013-08-16 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 이를 포함하는 반도체 집적 회로 |
| JP6066620B2 (ja) * | 2012-08-10 | 2017-01-25 | 学校法人慶應義塾 | バスシステム及び電子装置 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0973776A (ja) * | 1995-09-07 | 1997-03-18 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
| JPH09288888A (ja) * | 1996-04-22 | 1997-11-04 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPH1040682A (ja) * | 1996-07-23 | 1998-02-13 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US6028811A (en) * | 1998-01-05 | 2000-02-22 | Texas Instruments Incorporated | Architecture for high bandwidth wide I/O memory devices |
| JP3304899B2 (ja) | 1998-11-20 | 2002-07-22 | 日本電気株式会社 | 半導体記憶装置 |
| KR100363079B1 (ko) * | 1999-02-01 | 2002-11-30 | 삼성전자 주식회사 | 이웃한 메모리 뱅크들에 의해 입출력 센스앰프가 공유된 멀티 뱅크 메모리장치 |
| US6137746A (en) * | 1999-07-28 | 2000-10-24 | Alliance Semiconductor Corporation | High performance random access memory with multiple local I/O lines |
| KR100310992B1 (ko) * | 1999-09-03 | 2001-10-18 | 윤종용 | 멀티 뱅크 메모리 장치 및 입출력 라인 배치방법 |
| JP2001126470A (ja) * | 1999-10-26 | 2001-05-11 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP2001155485A (ja) * | 1999-11-29 | 2001-06-08 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP2001297586A (ja) * | 2000-04-12 | 2001-10-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
| KR100380387B1 (ko) | 2001-02-08 | 2003-04-11 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 신호 라인 배치 방법 |
| KR20030043410A (ko) | 2001-11-28 | 2003-06-02 | 삼성전자주식회사 | 글로벌 입출력 라인간의 커플링이 최소화되는 구조를가지는 반도체 메모리 장치 |
| KR100605573B1 (ko) * | 2004-05-06 | 2006-07-31 | 주식회사 하이닉스반도체 | 멀티-포트 메모리 소자 |
| KR100550643B1 (ko) * | 2004-09-06 | 2006-02-09 | 주식회사 하이닉스반도체 | 반도체메모리소자 |
-
2005
- 2005-05-09 US US11/125,447 patent/US7227805B2/en active Active
- 2005-05-09 KR KR1020050038570A patent/KR100733406B1/ko not_active IP Right Cessation
- 2005-05-10 CN CN200510069128A patent/CN100592421C/zh active Active
- 2005-05-10 TW TW094115068A patent/TWI290680B/zh active
-
2007
- 2007-04-24 US US11/789,257 patent/US7394718B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20070195632A1 (en) | 2007-08-23 |
| KR20060045988A (ko) | 2006-05-17 |
| US7394718B2 (en) | 2008-07-01 |
| US7227805B2 (en) | 2007-06-05 |
| US20050259499A1 (en) | 2005-11-24 |
| CN100592421C (zh) | 2010-02-24 |
| KR100733406B1 (ko) | 2007-06-29 |
| CN1707690A (zh) | 2005-12-14 |
| TWI290680B (en) | 2007-12-01 |
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