TW200610118A - Semiconductor device embedded structure and method for fabricating the same - Google Patents
Semiconductor device embedded structure and method for fabricating the sameInfo
- Publication number
- TW200610118A TW200610118A TW093127248A TW93127248A TW200610118A TW 200610118 A TW200610118 A TW 200610118A TW 093127248 A TW093127248 A TW 093127248A TW 93127248 A TW93127248 A TW 93127248A TW 200610118 A TW200610118 A TW 200610118A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- insulating layer
- fabricating
- same
- embedded structure
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093127248A TWI241007B (en) | 2004-09-09 | 2004-09-09 | Semiconductor device embedded structure and method for fabricating the same |
US11/008,964 US7129117B2 (en) | 2004-09-09 | 2004-12-13 | Method of embedding semiconductor chip in support plate and embedded structure thereof |
US11/510,604 US7274099B2 (en) | 2004-09-09 | 2006-08-28 | Method of embedding semiconductor chip in support plate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW093127248A TWI241007B (en) | 2004-09-09 | 2004-09-09 | Semiconductor device embedded structure and method for fabricating the same |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI241007B TWI241007B (en) | 2005-10-01 |
TW200610118A true TW200610118A (en) | 2006-03-16 |
Family
ID=35995386
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093127248A TWI241007B (en) | 2004-09-09 | 2004-09-09 | Semiconductor device embedded structure and method for fabricating the same |
Country Status (2)
Country | Link |
---|---|
US (2) | US7129117B2 (zh) |
TW (1) | TWI241007B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN103906372A (zh) * | 2012-12-27 | 2014-07-02 | 富葵精密组件(深圳)有限公司 | 具有内埋元件的电路板及其制作方法 |
Families Citing this family (58)
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US9691635B1 (en) * | 2002-05-01 | 2017-06-27 | Amkor Technology, Inc. | Buildup dielectric layer having metallization pattern semiconductor package fabrication method |
JP4528062B2 (ja) * | 2004-08-25 | 2010-08-18 | 富士通株式会社 | 半導体装置およびその製造方法 |
TWI241007B (en) * | 2004-09-09 | 2005-10-01 | Phoenix Prec Technology Corp | Semiconductor device embedded structure and method for fabricating the same |
TWI245384B (en) * | 2004-12-10 | 2005-12-11 | Phoenix Prec Technology Corp | Package structure with embedded chip and method for fabricating the same |
JP2006210852A (ja) * | 2005-01-31 | 2006-08-10 | Toshiba Corp | 表面実装型回路部品を実装する回路基板及びその製造方法 |
US7303947B1 (en) * | 2005-07-13 | 2007-12-04 | Lockheed Martin Corporation | Source bridge for cooling and/or external connection |
US7602062B1 (en) * | 2005-08-10 | 2009-10-13 | Altera Corporation | Package substrate with dual material build-up layers |
TWI297941B (en) * | 2005-10-13 | 2008-06-11 | Phoenix Prec Technology Corp | Semiconductor device with electroless plating metal connecting layer and method for fabricating the same |
US7759167B2 (en) * | 2005-11-23 | 2010-07-20 | Imec | Method for embedding dies |
CN100463128C (zh) * | 2005-11-25 | 2009-02-18 | 全懋精密科技股份有限公司 | 半导体芯片埋入基板的三维构装结构及其制作方法 |
TWI279897B (en) * | 2005-12-23 | 2007-04-21 | Phoenix Prec Technology Corp | Embedded semiconductor chip structure and method for fabricating the same |
US8067253B2 (en) * | 2005-12-21 | 2011-11-29 | Avery Dennison Corporation | Electrical device and method of manufacturing electrical devices using film embossing techniques to embed integrated circuits into film |
US8153472B2 (en) | 2006-06-20 | 2012-04-10 | Unimicron Technology Corp. | Embedded chip package process |
TWI292947B (en) | 2006-06-20 | 2008-01-21 | Unimicron Technology Corp | The structure of embedded chip packaging and the fabricating method thereof |
TWI327361B (en) * | 2006-07-28 | 2010-07-11 | Unimicron Technology Corp | Circuit board structure having passive component and stack structure thereof |
KR100796523B1 (ko) | 2006-08-17 | 2008-01-21 | 삼성전기주식회사 | 전자부품 내장형 다층 인쇄배선기판 및 그 제조방법 |
US7851331B2 (en) * | 2006-11-27 | 2010-12-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bonding structures and methods of forming bonding structures |
TWI330401B (en) * | 2006-12-25 | 2010-09-11 | Unimicron Technology Corp | Circuit board structure having embedded semiconductor component and fabrication method thereof |
US20090160053A1 (en) * | 2007-12-19 | 2009-06-25 | Infineon Technologies Ag | Method of manufacturing a semiconducotor device |
KR101070798B1 (ko) * | 2008-01-15 | 2011-10-06 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
TWI443789B (zh) * | 2008-07-04 | 2014-07-01 | Unimicron Technology Corp | 嵌埋有半導體晶片之電路板及其製法 |
US7855439B2 (en) * | 2008-08-28 | 2010-12-21 | Fairchild Semiconductor Corporation | Molded ultra thin semiconductor die packages, systems using the same, and methods of making the same |
US7993941B2 (en) * | 2008-12-05 | 2011-08-09 | Stats Chippac, Ltd. | Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant |
US20110156261A1 (en) * | 2009-03-24 | 2011-06-30 | Christopher James Kapusta | Integrated circuit package and method of making same |
US9299661B2 (en) * | 2009-03-24 | 2016-03-29 | General Electric Company | Integrated circuit package and method of making same |
KR101170878B1 (ko) * | 2009-06-29 | 2012-08-02 | 삼성전기주식회사 | 반도체 칩 패키지 및 그의 제조방법 |
TWI418272B (zh) * | 2009-08-25 | 2013-12-01 | Samsung Electro Mech | 處理核心基板之空腔的方法 |
TWI501376B (zh) * | 2009-10-07 | 2015-09-21 | Xintec Inc | 晶片封裝體及其製造方法 |
DE102009058764A1 (de) * | 2009-12-15 | 2011-06-16 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zur Herstellung einer elektronischen Baugruppe und elektronische Baugruppe |
US8421226B2 (en) * | 2010-02-25 | 2013-04-16 | Infineon Technologies Ag | Device including an encapsulated semiconductor chip and manufacturing method thereof |
US8927339B2 (en) | 2010-11-22 | 2015-01-06 | Bridge Semiconductor Corporation | Method of making thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry |
US8680683B1 (en) * | 2010-11-30 | 2014-03-25 | Triquint Semiconductor, Inc. | Wafer level package with embedded passive components and method of manufacturing |
CN103367339A (zh) * | 2012-03-26 | 2013-10-23 | 宏启胜精密电子(秦皇岛)有限公司 | 芯片封装方法及芯片封装结构 |
CN103929895A (zh) * | 2013-01-15 | 2014-07-16 | 宏启胜精密电子(秦皇岛)有限公司 | 具有内埋元件的电路板、其制作方法及封装结构 |
AT514564B1 (de) * | 2013-07-04 | 2015-02-15 | Austria Tech & System Tech | Verfahren zum Ankontaktieren und Umverdrahten |
CN105934823A (zh) | 2013-11-27 | 2016-09-07 | At&S奥地利科技与系统技术股份公司 | 印刷电路板结构 |
AT515101B1 (de) * | 2013-12-12 | 2015-06-15 | Austria Tech & System Tech | Verfahren zum Einbetten einer Komponente in eine Leiterplatte |
US9171795B2 (en) | 2013-12-16 | 2015-10-27 | Stats Chippac Ltd. | Integrated circuit packaging system with embedded component and method of manufacture thereof |
AT515447B1 (de) | 2014-02-27 | 2019-10-15 | At & S Austria Tech & Systemtechnik Ag | Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte |
US11523520B2 (en) | 2014-02-27 | 2022-12-06 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for making contact with a component embedded in a printed circuit board |
TWI517321B (zh) | 2014-12-08 | 2016-01-11 | 旭德科技股份有限公司 | 封裝結構及其製作方法 |
US9806063B2 (en) | 2015-04-29 | 2017-10-31 | Qualcomm Incorporated | Reinforced wafer level package comprising a core layer for reducing stress in a solder joint and improving solder joint reliability |
CN107463193B (zh) * | 2017-08-30 | 2022-09-09 | 中国医科大学附属第一医院 | 一种低温组织包埋温度控制系统 |
EP3481162B1 (en) * | 2017-11-06 | 2023-09-06 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with two component carrier portions and a component being embedded in a blind opening of one of the component carrier portions |
US11342256B2 (en) | 2019-01-24 | 2022-05-24 | Applied Materials, Inc. | Method of fine redistribution interconnect formation for advanced packaging applications |
TWI718011B (zh) * | 2019-02-26 | 2021-02-01 | 日商長瀨產業股份有限公司 | 嵌入式半導體封裝及其方法 |
IT201900006736A1 (it) | 2019-05-10 | 2020-11-10 | Applied Materials Inc | Procedimenti di fabbricazione di package |
IT201900006740A1 (it) | 2019-05-10 | 2020-11-10 | Applied Materials Inc | Procedimenti di strutturazione di substrati |
US11931855B2 (en) | 2019-06-17 | 2024-03-19 | Applied Materials, Inc. | Planarization methods for packaging substrates |
US11862546B2 (en) | 2019-11-27 | 2024-01-02 | Applied Materials, Inc. | Package core assembly and fabrication methods |
US11257790B2 (en) | 2020-03-10 | 2022-02-22 | Applied Materials, Inc. | High connectivity device stacking |
US11454884B2 (en) | 2020-04-15 | 2022-09-27 | Applied Materials, Inc. | Fluoropolymer stamp fabrication method |
US11400545B2 (en) | 2020-05-11 | 2022-08-02 | Applied Materials, Inc. | Laser ablation for package fabrication |
US11232951B1 (en) | 2020-07-14 | 2022-01-25 | Applied Materials, Inc. | Method and apparatus for laser drilling blind vias |
US11676832B2 (en) | 2020-07-24 | 2023-06-13 | Applied Materials, Inc. | Laser ablation system for package fabrication |
US11521937B2 (en) | 2020-11-16 | 2022-12-06 | Applied Materials, Inc. | Package structures with built-in EMI shielding |
US11404318B2 (en) | 2020-11-20 | 2022-08-02 | Applied Materials, Inc. | Methods of forming through-silicon vias in substrates for advanced packaging |
US11705365B2 (en) | 2021-05-18 | 2023-07-18 | Applied Materials, Inc. | Methods of micro-via formation for advanced packaging |
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US5682066A (en) * | 1996-08-12 | 1997-10-28 | Motorola, Inc. | Microelectronic assembly including a transparent encapsulant |
CN101232776B (zh) * | 1999-09-02 | 2011-04-20 | 揖斐电株式会社 | 印刷布线板 |
JP3813402B2 (ja) * | 2000-01-31 | 2006-08-23 | 新光電気工業株式会社 | 半導体装置の製造方法 |
US6586276B2 (en) * | 2001-07-11 | 2003-07-01 | Intel Corporation | Method for fabricating a microelectronic device using wafer-level adhesion layer deposition |
US20030066679A1 (en) * | 2001-10-09 | 2003-04-10 | Castro Abram M. | Electrical circuit and method of formation |
FI115285B (fi) * | 2002-01-31 | 2005-03-31 | Imbera Electronics Oy | Menetelmä komponentin upottamiseksi alustaan ja kontaktin muodostamiseksi |
TWI241007B (en) * | 2004-09-09 | 2005-10-01 | Phoenix Prec Technology Corp | Semiconductor device embedded structure and method for fabricating the same |
-
2004
- 2004-09-09 TW TW093127248A patent/TWI241007B/zh active
- 2004-12-13 US US11/008,964 patent/US7129117B2/en active Active
-
2006
- 2006-08-28 US US11/510,604 patent/US7274099B2/en active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103906372A (zh) * | 2012-12-27 | 2014-07-02 | 富葵精密组件(深圳)有限公司 | 具有内埋元件的电路板及其制作方法 |
TWI466607B (zh) * | 2012-12-27 | 2014-12-21 | Zhen Ding Technology Co Ltd | 具有內埋元件的電路板及其製作方法 |
US9089082B2 (en) | 2012-12-27 | 2015-07-21 | Zhen Ding Technology Co., Ltd. | Printed circuit board with embedded component and method for manufacturing same |
CN103906372B (zh) * | 2012-12-27 | 2017-03-01 | 碁鼎科技秦皇岛有限公司 | 具有内埋元件的电路板及其制作方法 |
Also Published As
Publication number | Publication date |
---|---|
US7129117B2 (en) | 2006-10-31 |
US20060049530A1 (en) | 2006-03-09 |
US7274099B2 (en) | 2007-09-25 |
US20060290010A1 (en) | 2006-12-28 |
TWI241007B (en) | 2005-10-01 |
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