TW200539382A - Method of forming a semiconductor device having air gaps and the structure so formed - Google Patents

Method of forming a semiconductor device having air gaps and the structure so formed Download PDF

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Publication number
TW200539382A
TW200539382A TW094114443A TW94114443A TW200539382A TW 200539382 A TW200539382 A TW 200539382A TW 094114443 A TW094114443 A TW 094114443A TW 94114443 A TW94114443 A TW 94114443A TW 200539382 A TW200539382 A TW 200539382A
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TW
Taiwan
Prior art keywords
dielectric material
porous
item
patent application
scope
Prior art date
Application number
TW094114443A
Other languages
English (en)
Chinese (zh)
Inventor
Anthony K Stamper
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200539382A publication Critical patent/TW200539382A/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/714—Electrodes having non-planar surfaces, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
TW094114443A 2004-05-25 2005-05-04 Method of forming a semiconductor device having air gaps and the structure so formed TW200539382A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/709,722 US7078814B2 (en) 2004-05-25 2004-05-25 Method of forming a semiconductor device having air gaps and the structure so formed

Publications (1)

Publication Number Publication Date
TW200539382A true TW200539382A (en) 2005-12-01

Family

ID=35451549

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094114443A TW200539382A (en) 2004-05-25 2005-05-04 Method of forming a semiconductor device having air gaps and the structure so formed

Country Status (7)

Country Link
US (3) US7078814B2 (https=)
EP (1) EP1766670A4 (https=)
JP (1) JP5362985B2 (https=)
KR (1) KR100956718B1 (https=)
CN (1) CN1954414A (https=)
TW (1) TW200539382A (https=)
WO (1) WO2005117085A2 (https=)

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US7485567B2 (en) 2007-02-02 2009-02-03 International Business Machines Corporation Microelectronic circuit structure with layered low dielectric constant regions and method of forming same
US20080185722A1 (en) * 2007-02-05 2008-08-07 Chung-Shi Liu Formation process of interconnect structures with air-gaps and sidewall spacers
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US8138036B2 (en) * 2008-08-08 2012-03-20 International Business Machines Corporation Through silicon via and method of fabricating same
US8298911B2 (en) * 2009-03-26 2012-10-30 Samsung Electronics Co., Ltd. Methods of forming wiring structures
KR101536333B1 (ko) * 2009-03-26 2015-07-14 삼성전자주식회사 배선 구조물 및 이의 형성 방법
WO2011021244A1 (ja) * 2009-08-20 2011-02-24 富士通セミコンダクター株式会社 半導体装置の製造方法
US8003516B2 (en) * 2009-08-26 2011-08-23 International Business Machines Corporation BEOL interconnect structures and related fabrication methods
US8456009B2 (en) * 2010-02-18 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having an air-gap region and a method of manufacturing the same
KR20120048991A (ko) * 2010-11-08 2012-05-16 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN103021929A (zh) * 2011-09-22 2013-04-03 中芯国际集成电路制造(北京)有限公司 半导体器件制造方法
KR101827893B1 (ko) 2012-02-22 2018-02-09 삼성전자주식회사 도전 라인 구조물 및 그 형성 방법
US8900989B2 (en) * 2013-03-06 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating an air gap using a damascene process and structure of same
CN105518837B (zh) * 2013-09-27 2019-04-16 英特尔公司 用于后段(beol)互连的自对准过孔及插塞图案化
US9853025B1 (en) * 2016-10-14 2017-12-26 International Business Machines Corporation Thin film metallic resistors formed by surface treatment of insulating layer
US11004612B2 (en) * 2019-03-14 2021-05-11 MicroSol Technologies Inc. Low temperature sub-nanometer periodic stack dielectrics
CN113785382B (zh) 2020-04-10 2023-10-27 株式会社日立高新技术 蚀刻方法
KR102845535B1 (ko) * 2021-04-06 2025-08-13 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
CN116918042A (zh) 2022-02-14 2023-10-20 株式会社日立高新技术 蚀刻处理方法

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Also Published As

Publication number Publication date
EP1766670A2 (en) 2007-03-28
US7674705B2 (en) 2010-03-09
JP2008502140A (ja) 2008-01-24
US7078814B2 (en) 2006-07-18
EP1766670A4 (en) 2011-03-02
JP5362985B2 (ja) 2013-12-11
CN1954414A (zh) 2007-04-25
US20090008788A1 (en) 2009-01-08
KR100956718B1 (ko) 2010-05-06
US20050275104A1 (en) 2005-12-15
KR20070021191A (ko) 2007-02-22
US20060166486A1 (en) 2006-07-27
US7459389B2 (en) 2008-12-02
WO2005117085A3 (en) 2006-10-12
WO2005117085A2 (en) 2005-12-08

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