TW577145B - Method of fabricating a dual damascene structure - Google Patents

Abstract

A first dielectric layer, a second dielectric layer, a first hard mask, and a second hard mask are formed, in order, on a semiconductor wafer. A first photoresist layer with patterns of a trench is formed on the second hard mask. An exposed region of the second hard mask is then removed down to the surface of the first hard mask. A second photoresist layer with patterns of a via hole is formed on the semiconductor wafer. Exposed regions of both the first hard mask and the second dielectric layer are removed down to the surface of the first dielectric layer. After removing the second photoresist layer, exposed regions of the first hard mask are removed, exposed regions of the second dielectric layer are then removed down to a predetermined depth, and the whole second hard mask and exposed regions of the first dielectric layer are also removed.

Description

577145 V. Description of the invention (1) Technical field to which the invention belongs The present invention provides a method for making a dua 1 damascene structure, especially a method that can be applied to ultra-low dielectric constant (ul tra-low-k) Manufacturing method of double mosaic structure of materials. In the prior art, a dual damascene process is a method capable of forming a metal wire and a plug stack structure at the same time, which is used to connect different components and wires between various layers in a semiconductor wafer, and uses the inner layer dielectric around it. Materials (inter-layer dielectrics) are isolated from other components. Therefore, as the development of integrated circuits becomes more sophisticated and complex, how to improve the yield of dual-mosaic structures is an important issue in the current integrated circuit manufacturing process. Please refer to FIGS. 1 to 4. FIGS. 1 to 4 are schematic diagrams of a method for fabricating a dual damascene structure on a semiconductor substrate 10. As shown in FIG. 1, the semiconductor substrate 10 includes a dielectric layer 12, and a conductive layer is in the dielectric layer. The conventional dual-damascene process is to sequentially open the semiconductor substrate ^ 0 into a protective layer (cap a dielectric layer I%, a stop layer 20, and a dielectric layer 22. Among them, the dielectric layer 1 2 It is composed of dioxide: it is used as a barrier between the conductive layer 14 and other electronic components. The layer 14 is a copper wire for electrical connection to a MOS transistor or a metal. Between the inner layer and the protective layer 16 and the stop layer 20 are both

577145 V. Description of the invention (2) 'It is composed of silicon nitride to protect the underlying structure from being damaged by etching. As for the dielectric layer 18 and the dielectric layer 22, they are spin-coated (sPln-on- Coating) of low dielectric constant (10wk) materials, such as FLARET, is the main structure to form a dual damascene structure. ^ After forming the above-mentioned stacked structure, as shown in FIG. 1, a hard mask layer 24 such as an oxy-nitride layer is formed on the surface of the dielectric layer 22. Subsequently, a first yellow light (a ^ ography) process is performed to form a layer above the hard mask layer 24; u layer 2 is formed to reach the surface of the hard mask layer 24 to define the upper trench of the dual damascene structure ( tired of the trench)? R XI Pavilion: So the second, and then-the first etching process, using 4 i ΐ ί 27 to etch down to open the upper trench ^

After the car photoresist layer 26, proceed to the second yellow light on the surface of 1_. The other photoresist layer 30 is formed on the surface of the soil bottom 10, and it reaches the dielectric layer 2 at the photo PJ 4 j site. The opening 31 on the 2 surface is used to set the pattern of the contact holes in the lower layer of the I structure. As shown in FIG. 2, a second etching process is then performed, and the dielectric layer 2 2, the stop layer and the 'I electric layer 1 8 are etched down to the surface of the protective layer 丨 6 along the opening 3 1 according to the pattern of 90. To form a through

Loss such as HSQ, connected to the opening of the silicon L resist layer Photoresist pattern D process, layer 30 double inlaid photoresistor 20 to dielectric

577145 V. Description of the invention (3) The openings of the layer 22, the stop layer 20 and the dielectric layer 18 are used as the lower contact holes 32. After the photoresist layer 30 is removed, as shown in FIG. 4, a second post-etching process is performed, using the hard mask layer 24 as an etching mask, removing the electric layer 22 downward, and using the stop layer 20 as a End etching (end-point) to form an upper-layer trench 3 4 to complete the fabrication of the conventional dual-damascene structure. After the dual damascene structure is formed, a conductive layer is filled in the dual damascene structure to serve as an interconnection between the metals. In order to avoid the capacitive effect between the conductive layer and other metal layers in the dual damascene structure, which affects the electrical performance of the dual damascene structure, organic low dielectric constant materials (dielectric constant k < 3 · 〇), such as aromatic thermosets (aromatic thermosets p0lymers), to form the dielectric f 18 and the dielectric layer 20, and the carbon content of the organic low dielectric constant material (carbon contains ) To reduce the number of dielectric books of the dielectric layer 18 and the dielectric layer 20. However, as the carbon content of the organic low-dielectric constant material increases, the stress constant of the dielectric layer 18 and the dielectric layer 20 (stress consta; G becomes larger, that is, when the organic low-dielectric constant material is larger. The more carbon content in the material, the more fragile the mechanical stress (mechani = al strength) property of the dielectric layer 18 and the dielectric layer 20, especially in the use of ultra-low dielectric constant = < 2 · ^ materials to make dual mosaic structures. When it is surrounded by the dual mosaic structure, the electrical layers 18 and 20 are very likely to cause a fragile situation during the preparation of the dual mosaic structure, causing problems such as leakage current.

Intercalation Low embedding Super inlay for dual use should be strong. In the present method, the power supply of the electric power in the structure is the structure of the inlaid mesh. The double inlay is a modified version of the double-engineering system. It is expected that the factor of this material is not the same. Electric structure 577145 i. Description of the invention (4) In a preferred embodiment of the present invention, a semiconductor wafer is first provided, and the semiconductor wafer includes a substrate and a conductive layer disposed on the substrate. Then, a first dielectric layer, a second dielectric layer, a first hard mask layer and a second hard mask layer are sequentially formed on the surface of the semiconductor wafer and covered on the conductive layer. Then, a first yellow light process is performed to form a first photoresist layer on the surface of the second hard cover curtain layer to define a pattern of an upper trench of the dual damascene structure. Subsequently, a first etching process is performed along the pattern of the first photoresist layer to remove the second hard mask layer not covered by the first photoresist layer, up to the surface of the first hard mask layer. After removing the first photoresist layer, a second yellow light process is performed to form a second photoresist layer on the surface of the semiconductor wafer to define the dual damascene structure = the pattern of the lower contact hole. Then, a second etching process is performed to remove the first hard mask layer and the second dielectric layer which are not covered by the second photoresist layer along the pattern of the second photoresist layer, until the first dielectric Layer surface. After the second photoresist layer is removed, a third etching process is performed. First, the first hard mask layer not covered by the second hard mask layer is removed, and then the first hard mask layer is not removed. The covered second dielectric layer reaches a predetermined depth and the second hard mask layer and the first dielectric layer not covered by the first hard mask layer are removed to the surface of the conductive layer to complete the process.

Page 10 577145 V. Description of the invention (5) Production of double mosaic structure of cost invention. Because the lower contact hole of the present invention is a second dielectric layer and a first dielectric layer penetrating a part, and the composite structure composed of the second dielectric layer and the first dielectric layer can provide a good bottom of the dual damascene structure. The supporting force can effectively avoid the occurrence of brittle cracks in the dielectric layer surrounding the dual damascene structure, so as to suppress problems such as leakage current. Embodiments Please refer to FIGS. 5 to 10, which are schematic diagrams of a method for fabricating a double mosaic structure on a half of the substrate 40 of the present invention. As shown in FIG. 5, the semiconductor substrate 40 includes a dielectric layer 42, and a conductive layer 44 is disposed in the dielectric layer 42. The surface of the conductive layer 44 is approximately tangent to the dielectric layer 42. The dielectric layer 4 2 is formed of silicon dioxide and serves as an isolation between the conductive layer 44 and other electronic components. The conductive layer 44 is a copper, aluminum or aluminum-copper wire, which can be electrically connected. To the MOS transistor or as an interconnect between multiple metals. Next, a protective layer 46, a dielectric layer 48, and a dielectric layer 50 are sequentially formed on the surface of the semiconductor substrate 40, covering the conductive layer 44 and the dielectric layer 42, and the dielectric layer 50 further includes a dielectric layer 50. Stop layer 5 2. Among them, the protective layer 46 and the stop layer 52 are both composed of silicon nitride, and other dense materials can also be used to make the protective layer 46 or the stop layer 5 2.

577145 V. Description of the invention (6) The dielectric layer 48 is made of an oxide layer, a fluorosilica glass ({11101 ^ 1131 ^ (1 silicate glass, FSG) layer or other chemical vapor deposition (CVD) dielectric) The thickness of the dielectric layer 50 is about several thousand angstroms, which is about 300-1000 angstroms (angstrom, A). It is spin-on- It is made of low dielectric constant material including coating, including FLARETM, SiLKTM, aryiene ether polymer, parylene compound, polyimide polymer, and fluorinated polymer. Low dielectric constant materials such as fluorinated polyimide, HSQ, fluorosilicate glass (FSG), stone dioxide, porous silica, or Teflon can be used to form the dielectric In addition, in order to reduce the total dielectric constant of the dielectric layer 48 and the dielectric layer 50, the stop layer 52 provided in the dielectric layer 50 may be omitted in the preferred embodiment of the present invention, and Instead, control the etching chamber to determine the ring hemp of the upper trench of the dual damascene structure. After stacking the structure, as shown in FIG. 5, a hard mask layer 54 and a hard mask layer 56 are sequentially formed on the surface of the dielectric layer 50 to form a double-layer hard mask. The hard cover curtain layer 54 is composed of silicon oxynitride, silicon nitride, or silicon carbide (siHc ^ carbide), and the hard cover curtain layer 56 is composed of a material "phase-compatible with the dielectric layer." In the first yellow light process, a photoresist layer 58 is formed above the hard mask layer 56 and an opening 59 is formed in the photoresist layer 58 to the surface of the hard mask layer 56 to define a dual damascene structure.

Page 12 577145 V. Description of the invention (7) The pattern of the grooves. Then, as shown in FIG. 6, a first etching process is performed, and the etching is performed along the opening 5 9 according to the pattern of the photoresist layer 58 to transfer the pattern of the upper trench to the hard cover curtain layer 56 and hard An opening 60 is formed in the mask layer 56. After removing the photoresist layer 58, a second yellow light process is performed to form another photoresist layer 62 on the surface of the semiconductor substrate 40, and a photoresist layer 62 is formed to reach the surface of the hard cover curtain layer 54. The opening 63 is used to define a pattern of contact holes under the dual damascene structure. As shown in FIG. 7, a second etching process is then performed, and the hard mask layer 54 and the dielectric layer 50 are etched downward along the opening 63 according to the pattern of the photoresist layer 62 to the surface of the dielectric layer 48. An opening 64 is formed through the hard mask layer 54 and the dielectric layer 50. After removing the photoresist layer 62, as shown in FIG. 8, then a third etching process is performed. First, the hard mask layer 56 is used as an etching mask, and the hard mask layer 54 is removed to the surface of the dielectric layer 50. The pattern of the upper trench is transferred to the hard mask layer 54, and then the dielectric layer 50 not covered by the hard mask layer 54 is further etched to a predetermined depth within the dielectric layer 50. The predetermined depth is smaller than the deposition thickness of the dielectric layer 50. For example, the stop layer 52 is used as an etching end point to form an upper trench 66 in the dielectric layer 50. After the dielectric layer 50 is removed, the selection ratio of the etching gas is then adjusted, and the dielectric layer 48 not covered by the hard mask layer 54 is removed downward along the opening 64 to the surface of the protective layer 46 to form a layer. Layer contact holes 68, as shown in Figure IX.

577145

In the preferred embodiment of the present invention, the material of the same material as the dielectric layer 48 is smaller than the dielectric layer 48. Therefore, when the hole 6 8 is removed, the 'hard cover curtain layer 5 6 will be removed to avoid double-layer hardening. The question above the curtain. In addition, since the hard cover curtain layer 56 is composed of and the thickness of the hard cover curtain layer 56 is divided by the dielectric layer 48 and the lower layer is formed to contact the above, the hard cover curtain is completely delayered during the above-mentioned process. The hard cover curtain is not completely removed. The resulting 46, covering the stoppage of the ditch of the affiliation and the obstruction is obvious as shown in the tenth stop of the exposure. The natural compound or the formation of the slot 66 is shown in the double inlay into the barrier layer 70. The conductive layer 52 is then formed by the button metal conductive layer and the lower layer 70 to make the surface approximately the center of the wire. The surface of 1 4 square 4 4 makes the upper trench sequenced by the semiconductor compound 72 and the conductive contact holes 6 8. Mechanical mechanical grinding Residual in double inlay Slightly cut in hard to make. The contact layer 6 at the bottom of the protective layer and removing the hard-layered curtain layer 54 6 6 The surface of the dielectric layer 50 is filled with the surface of the substrate 40 and a barrier layer 70 made of Jin Jin and a copper gold layer 72 are filled. On top of the full double mosaic structure, the hard mask layer 5 4 is finally used as a part of the conductive layer 72 in the manufacturing process. The conductive layer 72 and the mask layer 54 in the embedded structure are used to complete the preferred embodiment of the present invention. In the third etching process, there are three stages of etching steps: (1) removing part of the hard mask layer 54, and transferring the pattern of the upper trench into the hard mask layer 54; (2) according to the hard mask The part of the pattern of the layer 54 is removed; the surface of the electrical layer 50 to the stop layer 52 is used for the dielectric layer 50.

577145 V. Description of the invention (9) An upper trench 66 is formed; the hard mask layer 56 is completely removed, the lower dielectric layer 50 and the third etching process are performed step by step, that is, the lower layer is formed first. The invention can be applied to both the first embedding process and the first contact formation (3) and the removal of a part of the intermediary to form a through-stop layer 52, which is a contact hole 68 below the electrical layer α. Soil:? $ (2) and the order of step (3) can also intersect 68 and then form the upper trench 66 to form a trench first (dual first) double damascene process. Compared with the conventional method of making a double damascene contact hole 68, which penetrates a multilayer structure composed of dielectric ^ 48, and the dielectric layer 48 around ^ is made of chemical gas to provide good support, it can be embedded The dielectric layer surrounding the structure causes problems such as brittleness. In addition, since the thickness of the layer 50 of the present invention is much smaller than that of the conventional organic low-medium, the pattern used in the present invention can reduce the photoresist residue caused by the underexposure of the photoresist layer, and the current structure of 50 The thickness of the organic low-constant yellow light system affected by the surrounding phase deposition to effectively crack during the stop affects the two-layer stop layer to prevent the lower dielectric avoidance. The dielectric material is determined by inlaying. This step is used in layers. It is known that the invention is composed of a dielectric constant and a double avoidance structure, and the bottom of the dielectric layer contact hole 68, which can surround the double-leakage current-resistant material dielectric layers 1 8 and 2 2 inlaid structure and the bottom of the electrical meter. The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the scope of this patent should be covered by this application. Profit-seeking 577145 Simple illustration of the diagrams Simple illustration of the diagrams Figures 1 to 4 are schematic diagrams of the conventional method for making a double mosaic structure. Figures 5 to 10 are schematic diagrams of a method of making a double mosaic structure according to the present invention. Schematic symbol description

Page 16 10 Semiconductor substrate 12 '18 ^ 22 Dielectric layer 14 Conductive layer 16 Protective layer 20 Stop layer 24 Hard cover curtain layer 26 > 30 Photoresist layer 2 28, 28 ^ 31 Open π 32 Lower contact hole 34 Upper trench 40 Semiconductor substrate 42, 48 > 50 Dielectric layer 4 [72 Conductive layer 46 Protective layer 52 Stop layer 54> 56 Hard cover curtain layer 58 '62 Photoresist layer 59 ^ 60 > 63 > 64 Open Π 66 Upper trench 68 Lower contact Hole 70 obstacle layer

Claims (1)

577145 VI. Scope of patent application 1. A method for mounting a dua 1 damascene structure. The method includes the following steps: A semiconductor wafer is provided, and the semiconductor wafer includes a substrate and a conductive layer provided on the substrate. On the substrate; a first dielectric layer, a second dielectric layer, a first hard mask layer and a second hard mask layer are sequentially formed on the surface of the semiconductor wafer and cover the On the conductive layer, a first lithography process is performed to form a first photoresist layer on the surface of the second hard cover curtain layer to define a pattern of an upper trench of the dual damascene structure; Performing a first etch process to remove the second hard mask curtain layer that is not covered by the first photoresist layer along the pattern of the first photoresist layer until the surface of the first hard mask curtain layer; The first photoresist layer; performing a second yellow light process to form a second photoresist layer on the surface of the semiconductor wafer to define a pattern of a via hole of one lower layer of the dual damascene structure; and performing a first two Engraving process, removing the first hard mask layer and the second dielectric layer not covered by the second photoresist layer along the pattern of the second photoresist layer, until the surface of the first dielectric layer; removing the A second photoresist layer; and a third etching process, first removing the first hard mask layer not covered by the second hard mask layer, and then removing the first hard mask layer not covered by the first hard mask layer The second dielectric layer to a predetermined depth and removing the second hard layer 577145 6. Scope of patent application The mask layer and the first dielectric layer not covered by the first hard mask layer, up to the surface of the conductive layer. 2. The method according to item 1 of the scope of patent application, wherein the conductive layer is a copper wire 'and the surface of the conductive layer further includes a protective layer. 3. The method of claim 1 in the patent scope, wherein the first dielectric layer and the second hard cover layer are made of the same material. 4. The method according to item 1 of the patent application scope, wherein the first dielectric layer is composed of a fluorinated silicate glass (FSG) and the second dielectric layer is composed of a low dielectric constant (1 0 w — k). 5. The method according to item 4 of the scope of patent application, wherein the low dielectric constant material includes FLARETM, SiLKTM, poly (arylene ether) polymer, and parylene compound polyimide ( polyimide) polymers, fluorinated polyimide, HSQ, fluorosilicone glass (FSG), stone dioxide, porous silica, or Teflon. 6. The method of claim 1, wherein the predetermined depth is a thickness of the second dielectric layer. ' 577145 6. Application for Patent Scope 7. The method of the first scope of patent application, wherein the second dielectric layer further includes an etch stop layer, so that the third etching process etches the first etch stop layer. When the two dielectric layers are stopped, they can be stopped on the surface of the etch stop layer to form the upper trench of the dual damascene structure. 8. The method of claim 1, wherein after the third etching process is completed, the method includes the following steps: sequentially forming a barrier layer and a metal layer on the surface of the semiconductor wafer, and The metal layer fills the dual damascene structure; and a chemical mechanical polishing (CMP) process is performed using the first hard cover curtain layer as a stop layer to remove a portion of the metal Layer and the barrier layer to form a pair of back-mounted wires. 9. A method of manufacturing a dual damascene structure, the method comprising the following steps: providing a semiconductor wafer, the semiconductor wafer including a substrate and a conductive layer provided on the substrate; and forming a first on the surface of the semiconductor wafer in sequence A dielectric layer, a second dielectric layer, a first hard cover curtain layer and a second hard cover curtain layer, and covering the conductive layer; and an etching process of a double damascene structure is performed on the first Forming an upper trench of the dual damascene structure in the two dielectric layers and forming a lower contact hole of the dual damascene structure in the first dielectric layer; 577145 6. The scope of the patent application where the second hard cover curtain layer is completely removed from the etching process. 0. The method according to item 9 of the patent scope, wherein the conductive layer is a copper wire and the conductive The surface of the layer further includes a protective layer. 1 1. The method according to item 9 of the scope of patent application, wherein the first dielectric layer and the second hard cover curtain layer are made of the same material. 12. The method according to item 9 of the scope of patent application, wherein the etching process is a dual damascene process in which a contact hole (v i a f i r s t) is formed first. 1 3. The method according to item 9 of the scope of patent application, wherein the etching process is a double-mounting process in which a trench first is formed. 14. The method according to item 9 of the scope of patent application, wherein the etching process includes the following steps: a first yellow light process is performed, and a first photoresist layer is formed on the surface of the second hard cover curtain layer to define A pattern of an upper trench of the dual damascene structure; performing a first etching process, removing the second hard mask curtain layer not covered by the first photoresist layer along the pattern of the first photoresist layer, until the The surface of the first hard cover curtain layer; removing the first photoresist layer; performing a second yellow light process to form a second on the surface of the semiconductor wafer 577145 VI. Patent application photoresist layer to define the pattern of one lower contact hole of the dual damascene structure; perform a second etching process to remove the second photoresist layer along the pattern of the second photoresist layer Cover the first hard mask curtain layer and the second dielectric layer up to the surface of the first dielectric layer; remove the second photoresist layer; and perform a third last engraving process to remove The first hard mask layer covered by the hard mask layer, and then the second dielectric layer not covered by the first hard mask layer is removed to a predetermined depth and the second hard mask layer and the second hard mask layer are removed. The first dielectric layer covered by the first hard mask curtain layer reaches the surface of the conductive layer. 15. The method according to item 14 of the scope of patent application, wherein the predetermined depth is smaller than the deposition thickness of the second dielectric layer. 16. The method according to item 14 of the scope of patent application, wherein the second dielectric layer further includes an etch stop layer, so that the third etching process etches the second dielectric layer. At this time, it can stop on the surface of the etch stop layer to form the upper trench of the dual damascene structure. 1 7. The method according to item 9 of the patent application, wherein the first dielectric layer is composed of a fluorosilicon glass (FSG), and the second dielectric layer is composed of a low dielectric constant material. 18. The method according to item 17 of the scope of patent application, wherein the low dielectric constant Page 21 577145 VI. Patent application materials include FLARETM, SiLKTM, poly (arylene ether) polymer, parylene compounds, polyimide polymers, fluorine Fluorinated polyimide, HSQ, fluorspar glass (FSG), spar dioxide, nanoporous silica or teflon. 19. The method according to item 9 of the scope of patent application, wherein after the etching process is completed, the method includes the following steps: sequentially forming a barrier layer and a metal layer on the surface of the semiconductor wafer, and the metal layer is filled up The dual damascene structure; and a chemical mechanical polishing (CMP) process using the first hard cover curtain layer as a stop layer to remove a portion of the metal layer and the obstruction sound,