TWI509740B - Dual damascene process - Google Patents

Description

Double damascene process

The present invention provides a dual damascene process, and more particularly a dual damascene process that can be applied to ultra low dielectric constant (ultra low-k) materials.

The dual damascene process is a method of simultaneously forming a metal wire and a via plug on top of the stacked interconnect structure. The dual damascene structure is used to connect different components and wires between layers in a semiconductor wafer, and is isolated from other components by inter-metal inter-metal dielectrics and inter-layer dielectrics. . Since a chemical mechanical polish (CMP) is finally used in the preparation of the dual damascene structure, the surface of the semiconductor wafer is flattened, which is advantageous for various subsequent deposition and photo-lithography processes. This is done to prepare well-structured multilevel interconnects, so the dual damascene structure is widely used in the process of integrated circuits.

In addition, copper dual damascene technology with low dielectric constant (low-k) dielectric layers is now known for high-accumulation, high-speed logic integrated circuit chip fabrication and for deep sub-micron (deep sub -micro meter) The best metal interconnect solution for semiconductor processes. This is because copper has low resistance (30% lower than aluminum) and better resistance to electromigration resistance, while low dielectric constant materials help reduce the RC delay caused by the capacitive effect between metal wires. (RC delay), it can be seen that the low dielectric constant material with copper metal dual damascene interconnect technology is becoming more and more important in the integrated circuit process.

However, the conventional dual damascene process requires multiple repeated upper photoresist, bottom anti-reflective coating, exposure, development, after developing inspection (ADI), etching, and after etching inspection (AEI). Wait for the steps to complete. This is not only time-consuming and costly, but also causes capacity and pattern transfer when the critical dimension (CD) of the integrated circuit process is reduced to the deep sub-micron or nanometer (1 nm to 100 nm) level. The accuracy is reduced. In particular, when the rework step required for process anomalies is performed, the quality of the dielectric layer between the metal layers is seriously affected, and dielectric constant degradation (dielectric constant, k value, degradation) or critical dimension variation (critical dimension variation) occurs. And other problems, causing line distortion or fragile of the dielectric layer, causing a wriggling of a ditch or a via hole that would otherwise be a straight line, thereby affecting the subsequent The yield of the metallization process.

Therefore, with the development of integrated circuits becoming more sophisticated and complex, how to improve the yield of the dual damascene process is an important issue in the current integrated circuit process.

Accordingly, it is an object of the present invention to provide a method of fabricating a dual damascene structure that can be applied to ultra low dielectric constant materials.

According to the scope of the invention provided by the present invention, a dual damascene process is provided, in which a dielectric layer is first formed on a substrate, and then a first patterned mask is formed on the dielectric layer, and the first patterning is performed. The mask has an opening, and then a material layer is formed on the dielectric layer and covers the first patterned mask, and then a second patterned mask is formed on the dielectric layer, and the second patterned mask The cover has a first opening, and then a second opening is formed in the second patterned mask, and the second opening has a specific spacing from the first opening, and finally the second patterned cover is used. The mask acts as an etch mask to remove portions of the material layer and portions of the dielectric layer through the first opening and the second opening.

Since the present invention is provided with an etch stop layer, a material layer, a protective layer, and the like over a dielectric layer that is intended to form a dual damascene pattern, the dielectric layer is not exposed at all by the patterned mask of the trench and the via hole. The steps of etching, cleaning, photoresist removal, etc., and the rework steps when the post-development inspection (ADI) or post-etch inspection (AEI) is abnormal, can effectively ensure the quality of the inter-metal dielectric layer and the dual damascene pattern. , improve yield.

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Please refer to FIG. 1 to FIG. 10 . FIG. 1 to FIG. 10 are schematic diagrams showing a preferred embodiment of the dual damascene manufacturing method provided by the present invention. As shown in FIG. 1, a substrate 100 such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate is provided, and at least two conductive members 102, 104 are formed on the surface of the substrate 100. An insulating material layer 106 is further formed between the two conductive members 102 and 104 for electrically isolating the two conductive members 102 and 104. The conductive members 102 and 104 may be at least one of the following: a drain/source and a gate of a metal-oxide semiconductor (MOS) transistor, a resistor, and a through-silicon via (Through-Silicon) Via, TSV), doped regions, metal wiring layers, etc.; the insulating material layer 106 may be an interlayer dielectric layer or shallow trench isolation (STI), etc., and depending on product design and process requirements, the conductive members 102, 104 and the substrate 100 There may be at least one interlayer dielectric layer (not shown).

A cap layer 108, a dielectric layer 110, and a first patterned mask 112 are sequentially formed on the surface of the substrate 100. The cap layer 108 is a selectively formed material layer for protecting the conductive members 102, 104 and enhancing the adhesion of the subsequently formed dielectric layer 110. The material of the cap layer 108 is, for example, tantalum nitride (SiN), yttrium oxide (SiO), tantalum carbide (SiC), niobium oxynitride (SiCN) or bismuth oxynitride (SiON). Preferably, the cap layer 108 is a Nitrogen-containing dielectric layer, but not limited to this.

The dielectric layer 110 may comprise a single layer or a plurality of layers of dielectric materials selected from inorganic or organic low dielectric constant materials having a dielectric constant of less than 3.5. For example, fluorine-doped oxide (FSG), organosilicate (OSG), aromatic thermosets polymers, hydrogen silsesquioxane (HSQ, SiO: H) ), methyl silsesquioxane (MSQ, SiO: CH ₃ ), Hybrid Organic Siloxane Polymer (HOSP), Hydrogen-doped polyoxane (H-PSSQ) , methyl polysilsesquioxane (M-PSSQ), phenyl polysilsesquioxane (P-PSSQ) or porous sol-gel, etc., preferably The dielectric layer 110 is a material having an ultra low dielectric constant (ULK) (for example, k < 2.5). In addition, according to the manner of its formation, it can be further divided into chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (high density plasma CVD). Or by spin-on method, but not limited to this.

The first patterned mask 112 has an opening 120 for defining the position of the trench opening in the dual damascene structure, and the relative position of the opening 120 approximately corresponds to the two conductive members 102, 104 and partially overlaps the two conductive members 102. 104. The first patterned mask 112 may be a single layer mask or a multilayer hard mask structure, and may include a metal mask or a non-metal mask or a combination of the two. In the preferred embodiment, the first patterned mask 112 is a multilayer mask, for example, a multilayer stack structure including a titanium layer 112a, a titanium nitride layer 112b, and an oxide layer 112c. For example, the titanium layer 112a, the titanium nitride layer 112b, and the oxide layer 112c are formed in a comprehensive manner to form a mask layer, and then a photoresist coating and lithography process is performed thereon. A patterned photoresist layer (not shown) is formed, followed by an etching process to perform a pattern transfer to etch the opening 120 in the mask layer to form the first patterned mask 112. In addition, depending on product design and process requirements, an etch stop layer 114, such as silicon oxynitride (SiON), may be selectively formed between the first patterned mask 112 and the dielectric layer 110 to serve as the first pattern. The mask 112 is etched with a barrier layer during pattern transfer to protect the dielectric layer 110 beneath it. In addition, if an abnormality occurs in the post-development inspection (ADI) or the post-etch inspection (AEI) of the first patterned mask 112, the preferred embodiment can directly perform a rework step and is disposed above the dielectric layer 110. There is an etch stop layer 114, so the dielectric layer 110 is completely unaffected by the etching, cleaning, photoresist removal, etc. steps required to prepare the first patterned mask 112, as well as post-development inspection (ADI) or post-etch inspection (AEI). The quality of the dielectric layer is ensured by the rework steps during anomalies.

Then, as shown in FIG. 2 and FIG. 3 , a material layer 130 and a second patterned mask 140 are sequentially formed on the surface of the substrate 100 and covered on the first patterned mask 112 and the etch stop layer 114 . Above the dielectric layer 110. The material layer 130 may be a polymer material containing C, H, and O, such as a carbon-spin on hard mask (C-SOH), but is not limited thereto. The second patterned mask 140 has a first opening 180 for defining the position of the via hole in the dual damascene structure, and the position of the first opening 180 is approximately located between the two conductive members 102 and 104. One, for example, directly above the conductive member 104.

In the preferred embodiment, the second patterned mask 140 can be a multilayer mask or a single layer mask, such as a single oxide layer. The manufacturing method is, for example, first forming an oxide compound by chemical vapor deposition as the mask layer 140a, then forming a patterned photoresist layer 150 thereon, and performing an etching process to perform a pattern transfer. The first opening 180 is etched into the mask layer 140a to form a second patterned mask 140. Depending on the product design and process requirements, a second protective layer 160, such as tantalum nitride (SiN), may be selectively formed between the second patterned mask 140 and the material layer 130 to serve as a second patterned mask. The etch stop layer at the time of pattern transfer is performed to protect the material layer 130 underneath. A first bottom anti-reflective layer (BARC) 170, such as silicon oxynitride (SiON) or the like, may be selectively formed between the patterned photoresist layer 150 and the second patterned mask 140.

As shown in FIG. 4 and FIG. 5, a deposition, photoresist coating and lithography process is then performed to sequentially form a second bottom anti-reflective layer 190 and a patterned photoresist layer 200 on the surface of the substrate 100. And overlying the second patterned mask 140, the cover layer 160 and the material layer 130. Then, using the patterned photoresist layer 200 as a mask and using the cap layer 160 as an etch stop layer, another etching process is performed to perform another pattern transfer for etching in the second patterned mask 140. The second opening 220 is used to define the position of another through hole in the dual damascene structure, and the second opening 120 is located approximately at the other of the two conductive members 102, 104, for example, directly above the conductive member 102.

It should be noted that the second opening 220 does not overlap with the first opening 180 and has a specific spacing, and the specific spacing is smaller than the minimum pitch resolution of the lithography process for forming the first patterned photoresist layer 150. Moreover, the thickness of the photoresist layer 150, the photoresist layer 200, the first bottom anti-reflective layer 170 and the second bottom anti-reflective layer 190 can be appropriately adjusted so that the first opening 180 and the second opening are formed. When the holes 220 are respectively etched, they are simultaneously exhausted; of course, the cleaning process can be combined to completely remove the residual photoresist layer 150 and the first bottom anti-reflective layer 170, the photoresist layer 200 and the second bottom reactance. Reflective layer 190. In addition, the preferred embodiment can perform the required rework at any time if the steps described in FIGS. 2 and 5 are performed and an abnormality occurs in the corresponding post-development inspection (ADI) or post-etch inspection (AEI). Steps, and since the etch stop layer 114, the material layer 130 and the cap layer 160 are disposed over the dielectric layer 110, the dielectric layer 110 is not subjected to the etching, cleaning, and photoresist removal described in FIGS. 2 and 5 at all. The problem of dielectric constant degradation (k value degradation) or critical dimension variation caused by the steps and the rework steps when the post-development inspection (ADI) or post-etch inspection (AEI) is abnormal, thereby ensuring the inter-metal dielectric layer With the quality of the double mosaic pattern.

After the post-development inspection (ADI) step confirms that the layout patterns of the first opening 180 and the second opening 220 are correct, then, as shown in FIG. 6, the second patterned mask 140 is used as an etch mask to etch. The cover layer 160 transfers the pattern of the first opening 180 and the second opening 220 in the second patterned mask 140 into the sheath 160.

Then, as shown in FIG. 7, the second patterned mask 140 and the cap layer 160 are used as an etch mask to partially etch the material layer 130, the etch stop layer 114 and the dielectric layer 110 to connect the first opening 180 with The pattern of the second opening 220 continues to be transferred downward into the material layer 130, the etch stop layer 114, and the dielectric layer 110, and the first via hole 180a and the second via hole 220a are correspondingly formed in the dielectric layer 110. Similarly, the thickness of the second patterned mask 140 and the cover layer 160 and the etching parameters can be appropriately adjusted in the preferred embodiment so that the etching process of the first via hole 180a and the second via hole 220a is simultaneously performed. Exhaustion is exhausted; of course, the cleaning process can be combined to completely remove the remaining second patterned mask 140 and the sheath 160. Then, as shown in FIG. 8, a stripping process is performed, for example, a gas containing carbon dioxide, carbon monoxide or hydrogen gas is introduced to completely remove the remaining material layer 130 to expose the first patterned mask 112 having the pattern of the opening 120, An etch stop layer 114 having a pattern of first via holes 180a and second via holes 220a.

Finally, as shown in FIG. 9, the dielectric layer 110 and the cap layer 108 are etched using the first patterned mask 112 and the etch stop layer 114 as an etch mask to continue the pattern of the opening 120 down to the dielectric. In the layer 110, and simultaneously transferring the patterns of the first through holes 180a and the second through holes 220a to the dielectric layer 110 and the cap layer 108, respectively, the conductive members 104 and 102 are exposed to complete the dual damascene pattern 250. Process.

It should be noted that the first patterned mask 112 of the preferred embodiment is a multilayer stacked mask, and the etching rate including the titanium layer 112a and the titanium nitride layer 112b is different from the dielectric layer 110 and the cap layer. 108 and the metal mask material of the etch stop layer 114 have a relatively high etching selectivity. Therefore, when the process of the dual damascene pattern 250 is completed, the oxide layer 112c of the first patterned mask 112 is exhausted, and only the titanium layer 112a and the titanium nitride layer 112b remain on the substrate 100.

The dual damascene pattern 250 is then filled with conductive material to electrically connect the conductive members 104 and 102 to form a dual damascene structure. For example, a barrier layer 260 and a seed layer (not shown) are sequentially formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD) or an electroplating process, and then a copper metal layer 280 is formed by electroplating. The barrier layer may be a composite diffusion barrier layer composed of different combinations of tantalum (Ta), tantalum (Tatal), titanium (Ti), or titanium nitride (TiN), having a double layer or three The layered laminated structure prevents the copper ions of the copper metal layer 280 from migrating outwardly into the dielectric layer 110. Finally, a planarization process is performed to remove the conductive material other than the dual damascene pattern 250, and simultaneously remove the remaining titanium layer 112a and the titanium nitride layer 112b until the etch stop layer 114 or the top surface of the dielectric layer 110, as described Figure 10 shows. This is well known to those skilled in the art and to those of ordinary skill, and therefore will not be described here.

The preferred embodiment described above is primarily a partial-via-first process, but the present invention can also be integrated into a trench-first process, a via-first process, and In a dual damascene process such as a self-aligned process.

In summary, the preferred embodiment can perform the required rework steps at any time, and since the etch stop layer, the material layer and the cladding layer are disposed above the dielectric layer which is intended to form the dual damascene pattern, the dielectric layer is completely Dielectric constant deterioration does not occur due to the steps of etching, cleaning, photoresist removal, etc., and the rework steps when an abnormality occurs after post-development inspection (ADI) or post-etch inspection (AEI) as described in FIGS. 1 and 5. Or a problem such as a critical dimension variation, and further, a layout pattern of a good opening, a first opening, and a second opening can be formed in the first patterned mask and the second patterned mask and the protective layer, respectively. Finally, the subsequent etching process is transferred to the dielectric layer, so that problems such as k value degradation or CD variation can be effectively avoided, and the interlayer dielectric layer and the double damascene are greatly improved. Pattern quality and process yield.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Base

102, 104. . . Conductive part

106. . . Insulating material layer

108. . . Cover

110. . . Dielectric layer

112. . . First patterned mask

112a. . . Titanium layer

112b. . . Titanium nitride layer

112c. . . Oxide layer

114. . . Etch stop layer

120. . . Opening

130. . . Material layer

140. . . Second patterned mask

140a. . . Mask layer

150, 200. . . Photoresist layer

160. . . Cover

170. . . First bottom anti-reflection layer

180. . . First opening

190. . . Second bottom anti-reflection layer

220. . . Second opening

180a. . . First through hole

220a. . . Second through hole

250. . . Double mosaic

260. . . Barrier layer

280. . . Copper metal layer

1 to 10 are schematic views of the dual damascene process of the present invention.

100. . . Base

102, 104. . . Conductive part

106. . . Insulating material layer

108. . . Cover

110. . . Dielectric layer

112. . . First patterned mask

112a. . . Titanium layer

112b. . . Titanium nitride layer

112c. . . Oxide layer

114. . . Etch stop layer

130. . . Material layer

140. . . Second patterned mask

160. . . Cover

180. . . First opening

220. . . Second opening

Claims (18)

A dual damascene process, the dual damascene process comprising: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, the first patterned mask having an opening; forming a a material layer on the dielectric layer and covering the first patterned mask; forming a mask layer on the material layer, and forming a first patterned photoresist layer on the mask layer, and etching the mask a cover layer to form a second patterned mask on the material layer, the second patterned mask having a first opening; after the first opening is formed, forming in the second patterned mask a second opening, and the second opening has a spacing from the first opening, wherein the spacing is smaller than a minimum pitch resolution forming the first patterned photoresist layer, and the spacing partially overlaps the opening; And using the second patterned mask as an etch mask to remove portions of the material layer and portions of the dielectric layer through the first opening and the second opening. The dual damascene process of claim 1, wherein the dielectric layer has a dielectric constant value (k) of less than 2.5. The dual damascene process of claim 1, wherein the substrate has at least one conductive member and an insulating material for electrically isolating the conductive member, and the dielectric layer and the substrate further comprise a a cover layer covering the conductive member. The dual damascene process of claim 1, wherein the dielectric layer and the substrate further comprise an interlayer dielectric layer, wherein the interlayer dielectric layer has at least one conductive member, and the dielectric layer is The interlayer dielectric layer further includes a cap layer covering the conductive member. The dual damascene process of claim 1, wherein the first patterned mask comprises a metal mask. The dual damascene process of claim 1, wherein the first patterned mask comprises a multiplayer hard mask. The dual damascene process of claim 6, wherein the first patterned mask comprises a titanium layer, a titanium nitride layer, and an oxide layer. The dual damascene process of claim 1, wherein the method of forming the second patterned mask comprises: using the first patterned photoresist layer as an etch mask to etch out the mask layer The first opening forms the second patterned mask; and the first patterned photoresist layer is removed. The dual damascene process of claim 8, wherein the method of forming the second opening in the second patterned mask comprises: Forming a second patterned photoresist layer on the second patterned mask; etching the second opening in the second patterned mask by using the second patterned photoresist layer as an etch mask; The second patterned photoresist layer is removed. The dual damascene process of claim 9, wherein the second patterned mask and the dielectric layer further comprise a protective layer for forming the first opening and the second opening The integrity of the layer of material is protected. The dual damascene process of claim 10, further comprising an etching step using the second patterned mask as an etching mask to etch the first opening and the second in the sheath Open the hole. The dual damascene process of claim 8, wherein the first patterned photoresist layer and the second patterned mask further comprise a first bottom anti-reflective layer. The dual damascene process of claim 9, wherein the second patterned photoresist layer and the second patterned mask further comprise a second bottom anti-reflective layer. The dual damascene process of claim 1, wherein the material layer and the portion of the portion are removed through the second opening and the first opening After the dielectric layer, the dual damascene process further includes the step of completely removing the layer of material. The dual damascene process of claim 14, wherein after the material layer is completely removed, the dual damascene process further includes an etching step using the first pattern mask as an etch mask to A double mosaic pattern is formed in the electrical layer. The dual damascene process of claim 15, wherein after forming the dual damascene pattern, the dual damascene process further comprises the step of forming a metal layer in the dual damascene pattern. The dual damascene process of claim 16, wherein the metal layer comprises copper. The dual damascene process of claim 1, wherein the opening comprises a trench opening, and at least one of the first opening and the second opening comprises a through hole.