TW200514211A - Nonvolatile memory fabrication methods comprising lateral recessing of dielectric sidewalls at substrate isolation regions - Google Patents

Nonvolatile memory fabrication methods comprising lateral recessing of dielectric sidewalls at substrate isolation regions

Info

Publication number
TW200514211A
TW200514211A TW093121642A TW93121642A TW200514211A TW 200514211 A TW200514211 A TW 200514211A TW 093121642 A TW093121642 A TW 093121642A TW 93121642 A TW93121642 A TW 93121642A TW 200514211 A TW200514211 A TW 200514211A
Authority
TW
Taiwan
Prior art keywords
dielectric
nonvolatile memory
isolation regions
sidewalls
substrate isolation
Prior art date
Application number
TW093121642A
Other languages
English (en)
Other versions
TWI251310B (en
Inventor
Yi Ding
Original Assignee
Mosel Vitelic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosel Vitelic Inc filed Critical Mosel Vitelic Inc
Publication of TW200514211A publication Critical patent/TW200514211A/zh
Application granted granted Critical
Publication of TWI251310B publication Critical patent/TWI251310B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
TW093121642A 2003-10-03 2004-07-20 Nonvolatile memory fabrication methods comprising lateral recessing of dielectric sidewalls at substrate isolation regions TWI251310B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/678,317 US6838342B1 (en) 2003-10-03 2003-10-03 Nonvolatile memory fabrication methods comprising lateral recessing of dielectric sidewalls at substrate isolation regions

Publications (2)

Publication Number Publication Date
TW200514211A true TW200514211A (en) 2005-04-16
TWI251310B TWI251310B (en) 2006-03-11

Family

ID=33541604

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093121642A TWI251310B (en) 2003-10-03 2004-07-20 Nonvolatile memory fabrication methods comprising lateral recessing of dielectric sidewalls at substrate isolation regions

Country Status (2)

Country Link
US (1) US6838342B1 (zh)
TW (1) TWI251310B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030143757A1 (en) * 1997-06-13 2003-07-31 Jonathan Moore Methods for identifying drug cores
JP2005530357A (ja) * 2002-06-20 2005-10-06 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 導電スペーサで拡張されたフローティングゲート
US20040065937A1 (en) * 2002-10-07 2004-04-08 Chia-Shun Hsiao Floating gate memory structures and fabrication methods
KR100464443B1 (ko) * 2003-01-11 2005-01-03 삼성전자주식회사 이피롬(ＥＰＲＯＭ, ＥｒａａｂｌｅＰｒｏｇｒａｍｍａｂｌｅ Ｒｅａｄ ＯｎｌｙＭｅｍｏｒｙ} 소자의 셀 구조 및 그 제조방법
KR100602081B1 (ko) * 2003-12-27 2006-07-14 동부일렉트로닉스 주식회사 높은 커플링비를 갖는 불휘발성 메모리 소자 및 그 제조방법
US7067388B1 (en) 2004-04-07 2006-06-27 Spansion Llc Flash memory device and method of forming the same with improved gate breakdown and endurance
US7132333B2 (en) * 2004-09-10 2006-11-07 Infineon Technologies Ag Transistor, memory cell array and method of manufacturing a transistor
US7306552B2 (en) * 2004-12-03 2007-12-11 Samsung Electronics Co., Ltd. Semiconductor device having load resistor and method of fabricating the same
KR100691490B1 (ko) * 2005-04-29 2007-03-09 주식회사 하이닉스반도체 플래시 메모리 소자의 게이트 형성 방법
JP4250616B2 (ja) * 2005-05-13 2009-04-08 株式会社東芝 半導体集積回路装置及びその製造方法
KR100784083B1 (ko) * 2005-06-13 2007-12-10 주식회사 하이닉스반도체 플래시 메모리 소자의 플로팅 게이트 형성방법
KR100655435B1 (ko) * 2005-08-04 2006-12-08 삼성전자주식회사 비휘발성 메모리 장치 및 그 제조 방법
US7998809B2 (en) * 2006-05-15 2011-08-16 Micron Technology, Inc. Method for forming a floating gate using chemical mechanical planarization
US20080258206A1 (en) * 2007-04-17 2008-10-23 Qimonda Ag Self-Aligned Gate Structure, Memory Cell Array, and Methods of Making the Same
US20080283910A1 (en) * 2007-05-15 2008-11-20 Qimonda Ag Integrated circuit and method of forming an integrated circuit
TWI340474B (en) * 2007-08-24 2011-04-11 Nanya Technology Corp Method of forming semiconductor structure
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
CN108550525A (zh) * 2018-05-28 2018-09-18 武汉新芯集成电路制造有限公司 浮栅制备方法
CN113363263B (zh) * 2020-03-05 2023-11-10 华邦电子股份有限公司 非易失性存储器结构及其制造方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6960818B1 (en) * 1997-12-30 2005-11-01 Siemens Aktiengesellschaft Recessed shallow trench isolation structure nitride liner and method for making same
US6200856B1 (en) 1998-03-25 2001-03-13 Winbond Electronics Corporation Method of fabricating self-aligned stacked gate flash memory cell
US6130129A (en) 1998-07-09 2000-10-10 Winbond Electronics Corp. Method of making self-aligned stacked gate flush memory with high control gate to floating gate coupling ratio
JP4237344B2 (ja) 1998-09-29 2009-03-11 株式会社東芝 半導体装置及びその製造方法
US6319794B1 (en) 1998-10-14 2001-11-20 International Business Machines Corporation Structure and method for producing low leakage isolation devices
US6127215A (en) * 1998-10-29 2000-10-03 International Business Machines Corp. Deep pivot mask for enhanced buried-channel PFET performance and reliability
US6323085B1 (en) 1999-04-05 2001-11-27 Micron Technology, Inc. High coupling split-gate transistor and method for its formation
US6228713B1 (en) 1999-06-28 2001-05-08 Chartered Semiconductor Manufacturing Ltd. Self-aligned floating gate for memory application using shallow trench isolation
TW484228B (en) 1999-08-31 2002-04-21 Toshiba Corp Non-volatile semiconductor memory device and the manufacturing method thereof
JP3785003B2 (ja) 1999-09-20 2006-06-14 株式会社東芝 不揮発性半導体記憶装置の製造方法
US6518618B1 (en) 1999-12-03 2003-02-11 Intel Corporation Integrated memory cell and method of fabrication
US6312989B1 (en) * 2000-01-21 2001-11-06 Taiwan Semiconductor Manufacturing Company Structure with protruding source in split-gate flash
US6448606B1 (en) 2000-02-24 2002-09-10 Advanced Micro Devices, Inc. Semiconductor with increased gate coupling coefficient
US6376877B1 (en) 2000-02-24 2002-04-23 Advanced Micro Devices, Inc. Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor
JP2001332637A (ja) * 2000-05-23 2001-11-30 Nec Corp 半導体記憶装置及びその製造方法
US6355524B1 (en) 2000-08-15 2002-03-12 Mosel Vitelic, Inc. Nonvolatile memory structures and fabrication methods
US6562681B2 (en) * 2001-06-13 2003-05-13 Mosel Vitelic, Inc. Nonvolatile memories with floating gate spacers, and methods of fabrication
US6743675B2 (en) * 2002-10-01 2004-06-01 Mosel Vitelic, Inc. Floating gate memory fabrication methods comprising a field dielectric etch with a horizontal etch component

Also Published As

Publication number Publication date
US6838342B1 (en) 2005-01-04
TWI251310B (en) 2006-03-11

Similar Documents

Publication Publication Date Title
TW200514211A (en) Nonvolatile memory fabrication methods comprising lateral recessing of dielectric sidewalls at substrate isolation regions
TW200505008A (en) Nonvolatile memory cell with multiple floating gates formed after the select gate
US9536881B2 (en) Semiconductor devices having fin shaped channels
JP2007300098A5 (zh)
WO2003015173A3 (en) Floating gate memory array and methods of forming
TWI263342B (en) Non-volatile memory and manufacturing method and operating method thereof
KR102311929B1 (ko) 반도체 소자 및 이의 제조 방법
TW200518268A (en) Improved method for manufacturing a 2-transistor memory cell, and improved memory cell thus obtained
TW200725813A (en) Method of manufacturing flash memory device
TW200721511A (en) Double gate non-volatile memory device and method of manufacturing such a memory device
US7560340B2 (en) Method of manufacturing flash memory device
CN100452358C (zh) 制造闪存器件的方法
TW200625608A (en) Non-volatile memory device and manufacturing method and operating method thereof
CN101667581A (zh) 一种分栅型埋层浮栅式的非易失性存储单元及其制造方法
TW200616160A (en) Manufacturing method of flash memory
TW200737424A (en) One time programmable memory and the manufacturing method thereof
US7355243B2 (en) Flash memory device and method for fabricating the same
WO2003100841A3 (de) Verfahren zum herstellen einer speicherzelle, speicherzelle und speicherzellen-anordnung
TW200638515A (en) Non-volatile memory and fabricating method thereof and operation thereof
KR100846393B1 (ko) 반도체 소자의 트랜지스터 및 그 제조 방법
KR20020088554A (ko) 플래시 메모리의 셀 및 그 형성 방법
KR20070002342A (en) Method for manufacturing flash memory device
US20070104011A1 (en) Cell array of semiconductor memory device and a method of forming the same
US7005696B2 (en) Structure of nonvolatile memory array
US7663184B1 (en) Memory and method of fabricating the same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees