CN100452358C - 制造闪存器件的方法 - Google Patents

制造闪存器件的方法 Download PDF

Info

Publication number
CN100452358C
CN100452358C CNB2006100836907A CN200610083690A CN100452358C CN 100452358 C CN100452358 C CN 100452358C CN B2006100836907 A CNB2006100836907 A CN B2006100836907A CN 200610083690 A CN200610083690 A CN 200610083690A CN 100452358 C CN100452358 C CN 100452358C
Authority
CN
China
Prior art keywords
interlayer dielectric
etching
nitride film
total
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2006100836907A
Other languages
English (en)
Other versions
CN1971883A (zh
Inventor
郑宇荣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN1971883A publication Critical patent/CN1971883A/zh
Application granted granted Critical
Publication of CN100452358C publication Critical patent/CN100452358C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种制造闪存器件的方法，包括下列步骤：在其中限定单元区域、源选择线区域和漏选择线区域的半导体衬底上形成栅，然后在栅的侧壁上形成间隔物；在整个结构上沉积氮化物膜和第一层间绝缘膜，蚀刻第一层间绝缘膜的区域以形成源接触孔，在整个结构上形成传导膜以掩埋源接触孔，并抛光传导膜；在整个结构上形成第二层间绝缘膜，然后使用掩模蚀刻第二和第一层间绝缘膜和氮化物膜，由此打开其中将形成单元区域和漏接触的区域；以及在整个结构上形成多晶硅层。

Description

制造闪存器件的方法
技术领域
本发明一般地涉及一种制造存储器件的方法，并更具体而言，涉及一种制造闪存器件的方法，在其中它可最小化栅间干扰现象。
背景技术
多级单元(MLC)是闪存单元，用来在一个存储单元中存储2-位数据以便于增加集成级。在MLC中，一个单元可分成四级状态。因而，MLC的位数目两倍地大于用来在一个存储单元中存储1-位数据的单级单元(SLC)的位数目。
然而，在MLC中，由于单元阈值电压(Vt)变化，单元均匀性变得不规则。这导致了通过单元之间的电容产生的干扰现象。
因此，有必要减少单元阈值电压(Vt)的移位。然而，由于器件集成级增加，单位有源区域和单位场区域将被形成的间隔变得更窄。由于栅间距离变得更小，这使干扰现象更成问题。
发明内容
在一个实施例中，本发明提供一种制造闪存器件的方法，该方法通过减少栅之间的电容可减少栅间干扰现象。
因而，本发明的一个实施例提供了一种制造闪存器件的方法，包括下列步骤：在其中限定单元区域、源选择线区域和漏选择线区域的半导体衬底上形成栅，然后在栅的侧壁上形成间隔物；在整个结构上沉积氮化物膜和第一层间绝缘膜，蚀刻第一层间绝缘膜的区域以形成源接触孔，在整个结构上形成传导膜以掩埋源接触孔，并抛光传导膜；在整个结构上形成第二层间绝缘膜，然后使用掩模蚀刻第二层间绝缘膜和第一层间绝缘膜和氮化物膜，由此打开其中将形成单元区域和漏接触的区域；以及在整个结构上形成多晶硅层。
附图说明
当结合附图考虑时，通过参考下列详细描述，对本发明和其许多伴随优点更为彻底的理解将变得明显，同时它们变得更好理解，在附图中，类似参考符号标示相同或类似部件，在附图中：
图1A至图1D是图示根据本发明实施例的制造闪存器件的方法的横截面视图。
具体实施方式
现在将参考附图结合某些示范性实施例详细描述本发明。
图1A至图1D是图示根据本发明实施例的制造闪存器件的方法的横截面视图。
参考图1A，栅102形成在半导体衬底100上，在该半导体衬底100中限定了单元区域、源选择线区域和漏选择线区域，在该栅102中层压了隧道氧化物膜A、浮动栅B、电介质层C、由多晶硅层和传导(例如，钨)膜制成的控制栅D以及硬掩模膜E。间隔物104形成在栅102的侧壁上。可优选地使用氧化物膜形成间隔物104。
参考图1B，氮化物膜106和第一层间绝缘膜108沉积在整个结构上。第一层间绝缘膜108被抛光。优选地通过采用掩模的光刻和蚀刻工艺来蚀刻第一层间绝缘膜108的区域，由此形成接触孔，通过该接触孔暴露源F。
然后钨膜形成在整个结构上。抛光钨膜直到第一层间绝缘膜108的顶表面暴露，由此形成源接触110。
参考图1C，第二层间绝缘膜112形成在整个结构上。通过采用掩模的光刻和蚀刻工艺来蚀刻第二和第一层间绝缘膜112和108以及氮化物膜106，使得其中将形成单元区域和漏接触的区域被暴露。
在单元区域中，氮化物膜106部分地留在半导体衬底100上。第一和第二层间绝缘膜108和112通过干蚀刻工艺来剥离，而且氮化物膜106通过湿蚀刻工艺来剥离。
参考图1D，多晶硅层114形成在整个结构上，使得其中将形成漏接触的以及在单元栅102与单元栅102之间的区域被掩埋。抛光多晶硅层114直到第二层间绝缘膜112的顶表面暴露。
由于多晶硅层114形成在单元栅102之间，可减少在单元栅102之间的电容，因而可减少在栅102之间的干扰现象。
如上所述，根据本发明，多晶硅层形成在单元栅之间。因而，本发明有利之处在于其可减少栅间电容并可改善栅间干扰现象。
虽然结合实际示范性实施例描述了本发明，但本发明不限于所公开的实施例，而是相反地，本发明旨在覆盖在所附权利要求的精神和范围中包括的各种修改和等效设置。

Claims (3)

1.一种制造闪存器件的方法，所述方法包括下列步骤：
在其中限定单元区域、源选择线区域和漏选择线区域的半导体衬底上形成栅，然后在栅的侧壁上形成间隔物；
在整个结构上沉积氮化物膜和第一层间绝缘膜，蚀刻所述第一层间绝缘膜的区域以形成源接触孔，在整个结构上形成传导膜以掩埋所述源接触孔，并抛光所述传导膜；
在整个结构上形成第二层间绝缘膜，然后使用掩模蚀刻所述第二层间绝缘膜和所述第一层间绝缘膜以及所述氮化物膜，由此打开其中将形成单元区域和漏接触的区域；以及，
在整个结构上形成多晶硅层。
2.权利要求1的方法，包括当蚀刻所述氮化物膜时所述单元区域的所述氮化物膜不完全蚀刻，而部分地留在所述半导体衬底上。
3.权利要求1的方法，其中所述传导膜是钨膜。
CNB2006100836907A 2005-11-23 2006-06-02 制造闪存器件的方法 Expired - Fee Related CN100452358C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020050112134A KR100739963B1 (ko) 2005-11-23 2005-11-23 플래쉬 메모리 소자의 제조방법
KR1020050112134 2005-11-23

Publications (2)

Publication Number Publication Date
CN1971883A CN1971883A (zh) 2007-05-30
CN100452358C true CN100452358C (zh) 2009-01-14

Family

ID=38054079

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006100836907A Expired - Fee Related CN100452358C (zh) 2005-11-23 2006-06-02 制造闪存器件的方法

Country Status (3)

Country Link
US (1) US7351630B2 (zh)
KR (1) KR100739963B1 (zh)
CN (1) CN100452358C (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101107620A (zh) * 2005-01-07 2008-01-16 发现控股有限公司 管理健康保险计划业务的方法和系统
WO2007141696A2 (en) * 2006-06-06 2007-12-13 Discovery Holdings Limited A system and method of managing an insurance scheme
AU2007257545A1 (en) * 2006-06-07 2007-12-13 Discovery Holdings Limited A system and method of managing an insurance scheme
KR100838531B1 (ko) * 2006-10-20 2008-06-19 삼성전자주식회사 비휘발성 메모리 소자 및 그 형성방법
WO2009147593A1 (en) * 2008-06-03 2009-12-10 Discovery Holdings Limited A system and method of managing an insurance scheme
CN102057390A (zh) * 2008-06-03 2011-05-11 发现控股有限公司 管理保险方案的系统和方法
KR101185988B1 (ko) * 2009-12-30 2012-09-25 에스케이하이닉스 주식회사 반도체 메모리소자의 랜딩플러그컨택 형성방법
WO2014097009A1 (en) 2012-12-21 2014-06-26 ABRAMSON, Lance A method of determining the attendance of an individual at a location and a system therefor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1117156A (ja) * 1997-06-27 1999-01-22 Toshiba Corp 不揮発性半導体メモリ装置およびその製造方法
US6617639B1 (en) * 2002-06-21 2003-09-09 Advanced Micro Devices, Inc. Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling
US20050157549A1 (en) * 2004-01-21 2005-07-21 Nima Mokhlesi Non-volatile memory cell using high-k material and inter-gate programming
US6936885B2 (en) * 2000-01-17 2005-08-30 Samsung Electronics Co., Ltd. NAND-type flash memory devices and methods of fabricating the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3716047B2 (ja) * 1996-06-13 2005-11-16 ミサワホーム株式会社 土間ユニット構造及び土間ユニットの施工方法
KR101099513B1 (ko) * 2005-06-30 2011-12-28 주식회사 하이닉스반도체 플래쉬 메모리소자의 콘택플러그 형성방법
KR20070005074A (ko) * 2005-07-05 2007-01-10 주식회사 하이닉스반도체 플래쉬 메모리소자의 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1117156A (ja) * 1997-06-27 1999-01-22 Toshiba Corp 不揮発性半導体メモリ装置およびその製造方法
US6936885B2 (en) * 2000-01-17 2005-08-30 Samsung Electronics Co., Ltd. NAND-type flash memory devices and methods of fabricating the same
US6617639B1 (en) * 2002-06-21 2003-09-09 Advanced Micro Devices, Inc. Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling
US20050157549A1 (en) * 2004-01-21 2005-07-21 Nima Mokhlesi Non-volatile memory cell using high-k material and inter-gate programming

Also Published As

Publication number Publication date
KR20070054295A (ko) 2007-05-29
US7351630B2 (en) 2008-04-01
CN1971883A (zh) 2007-05-30
US20070117302A1 (en) 2007-05-24
KR100739963B1 (ko) 2007-07-16

Similar Documents

Publication Publication Date Title
CN100452358C (zh) 制造闪存器件的方法
US7160780B2 (en) Method of manufacturing a fin field effect transistor
US8202781B2 (en) Semiconductor device having vertical pillar transistors and method for manufacturing the same
CN100492647C (zh) 闪存器件及其制造方法
US8735956B2 (en) Semiconductor device and method for manufacturing the same
US7851311B2 (en) Method of manufacturing non-volatile memory device
KR100660543B1 (ko) 낸드형 플래시 메모리 장치 및 그 제조 방법
KR20150065614A (ko) 플래시 메모리 반도체 소자 및 그 제조 방법
KR101205067B1 (ko) 반도체 소자의 형성방법
KR20040060491A (ko) 엔드형 플래쉬 메모리 소자의 제조방법
CN111415937B (zh) 存储器及其形成方法
KR20130073488A (ko) 반도체 소자 및 그 제조 방법
US7355243B2 (en) Flash memory device and method for fabricating the same
KR20030057173A (ko) 실리콘기판 내에 게이트를 갖는 더블게이트 제조방법
KR20110069305A (ko) 플래시 메모리 소자 및 그 제조 방법
KR100832024B1 (ko) 반도체 소자의 절연막 평탄화방법
CN111682025B (zh) 闪存存储器及其制造、使用方法
CN109638016B (zh) 快闪存储器及其形成方法
KR100600955B1 (ko) 비휘발성 메모리 소자의 셀 및 그 제조방법
CN114695563A (zh) 存储器结构及其形成方法
CN115249713A (zh) 半导体结构及其形成方法、以及存储器
KR20100010738A (ko) 플래시 메모리 장치 및 그 제조방법
KR20070000156A (ko) Ｎａｎｄ형 플래쉬 메모리 소자의 제조 방법
US20080283895A1 (en) Memory structure and fabricating method thereof
KR20100078002A (ko) 반도체 소자 및 그 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090114

Termination date: 20130602