TW200423261A - Method of fabricating multi-layer devices on buried oxide layer substrates - Google Patents

Method of fabricating multi-layer devices on buried oxide layer substrates Download PDF

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Publication number
TW200423261A
TW200423261A TW092132599A TW92132599A TW200423261A TW 200423261 A TW200423261 A TW 200423261A TW 092132599 A TW092132599 A TW 092132599A TW 92132599 A TW92132599 A TW 92132599A TW 200423261 A TW200423261 A TW 200423261A
Authority
TW
Taiwan
Prior art keywords
layer
substrate
principles
layers
present
Prior art date
Application number
TW092132599A
Other languages
English (en)
Chinese (zh)
Inventor
Sadeg M Faris
Original Assignee
Reveo Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Reveo Inc filed Critical Reveo Inc
Publication of TW200423261A publication Critical patent/TW200423261A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C99/00—Subject matter not provided for in other groups of this subclass
    • B81C99/0035—Testing
    • B81C99/0045—End test of the packaged device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Micromachines (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
TW092132599A 2002-11-20 2003-11-20 Method of fabricating multi-layer devices on buried oxide layer substrates TW200423261A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US42812502P 2002-11-20 2002-11-20

Publications (1)

Publication Number Publication Date
TW200423261A true TW200423261A (en) 2004-11-01

Family

ID=33551213

Family Applications (3)

Application Number Title Priority Date Filing Date
TW092132599A TW200423261A (en) 2002-11-20 2003-11-20 Method of fabricating multi-layer devices on buried oxide layer substrates
TW092132597A TW200421497A (en) 2002-11-20 2003-11-20 Method and system for increasing yield of vertically integrated devices
TW092132601A TW200428538A (en) 2002-11-20 2003-11-20 Method of fabricating vertical integrated circuits

Family Applications After (2)

Application Number Title Priority Date Filing Date
TW092132597A TW200421497A (en) 2002-11-20 2003-11-20 Method and system for increasing yield of vertically integrated devices
TW092132601A TW200428538A (en) 2002-11-20 2003-11-20 Method of fabricating vertical integrated circuits

Country Status (8)

Country Link
US (1) US7056751B2 (https=)
EP (1) EP1573788A3 (https=)
JP (1) JP2006520089A (https=)
KR (1) KR20050083935A (https=)
CN (1) CN1742358A (https=)
AU (1) AU2003304218A1 (https=)
TW (3) TW200423261A (https=)
WO (1) WO2004112089A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
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TWI728778B (zh) * 2020-02-20 2021-05-21 大陸商長江存儲科技有限責任公司 具有xtacking架構的動態隨機存取儲存器（dram）記憶體元件

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FR2839505B1 (fr) * 2002-05-07 2005-07-15 Univ Claude Bernard Lyon Procede pour modifier les proprietes d'une couche mince et substrat faisant application du procede
US7659631B2 (en) * 2006-10-12 2010-02-09 Hewlett-Packard Development Company, L.P. Interconnection between different circuit types
US20090026524A1 (en) * 2007-07-27 2009-01-29 Franz Kreupl Stacked Circuits
CN102844176A (zh) * 2009-09-30 2012-12-26 微型实验室诊断股份有限公司 微流体装置中选择性的粘结性降低
KR101348655B1 (ko) * 2010-03-24 2014-01-08 한국전자통신연구원 미세유체 제어 장치 및 그 제조 방법
US8829329B2 (en) * 2010-08-18 2014-09-09 International Business Machines Corporation Solar cell and battery 3D integration
DE102010041763A1 (de) 2010-09-30 2012-04-05 Siemens Aktiengesellschaft Mikromechanisches Substrat
US10543662B2 (en) 2012-02-08 2020-01-28 Corning Incorporated Device modified substrate article and methods for making
US10014177B2 (en) 2012-12-13 2018-07-03 Corning Incorporated Methods for processing electronic devices
TWI617437B (zh) 2012-12-13 2018-03-11 康寧公司 促進控制薄片與載體間接合之處理
US9340443B2 (en) 2012-12-13 2016-05-17 Corning Incorporated Bulk annealing of glass sheets
US10086584B2 (en) 2012-12-13 2018-10-02 Corning Incorporated Glass articles and methods for controlled bonding of glass sheets with carriers
US10510576B2 (en) 2013-10-14 2019-12-17 Corning Incorporated Carrier-bonding methods and articles for semiconductor and interposer processing
US10046542B2 (en) 2014-01-27 2018-08-14 Corning Incorporated Articles and methods for controlled bonding of thin sheets with carriers
CN106457758B (zh) 2014-04-09 2018-11-16 康宁股份有限公司 装置改性的基材制品及其制备方法
JP2018524201A (ja) 2015-05-19 2018-08-30 コーニング インコーポレイテッド シートをキャリアと結合するための物品および方法
US11905201B2 (en) 2015-06-26 2024-02-20 Corning Incorporated Methods and articles including a sheet and a carrier
US20170186730A1 (en) * 2015-12-26 2017-06-29 Invensas Corporation System and method for providing 3d wafer assembly with known-good-dies
WO2018013243A1 (en) * 2016-06-01 2018-01-18 Quantum-Si Incorporated Integrated device for detecting and analyzing molecules
TW202216444A (zh) 2016-08-30 2022-05-01 美商康寧公司 用於片材接合的矽氧烷電漿聚合物
TWI810161B (zh) 2016-08-31 2023-08-01 美商康寧公司 具以可控制式黏結的薄片之製品及製作其之方法
CN111372772A (zh) 2017-08-18 2020-07-03 康宁股份有限公司 使用聚阳离子聚合物的临时结合
US11331692B2 (en) 2017-12-15 2022-05-17 Corning Incorporated Methods for treating a substrate and method for making articles comprising bonded sheets
US11315789B2 (en) * 2019-04-24 2022-04-26 Tokyo Electron Limited Method and structure for low density silicon oxide for fusion bonding and debonding
US11829077B2 (en) * 2020-12-11 2023-11-28 Kla Corporation System and method for determining post bonding overlay
JP7097480B1 (ja) 2021-06-24 2022-07-07 浜松ホトニクス株式会社 Ｘ線管、ｘ線発生装置、及び窓部材の製造方法
US11782411B2 (en) 2021-07-28 2023-10-10 Kla Corporation System and method for mitigating overlay distortion patterns caused by a wafer bonding tool
CN114035030B (zh) * 2021-11-05 2023-10-24 爱迪特（秦皇岛）科技股份有限公司 一种测试组件
CN116387256A (zh) * 2023-04-26 2023-07-04 上海易卜半导体有限公司 芯片堆栈及制备方法
CN119275214B (zh) * 2024-12-10 2025-02-25 电子科技大学 一种用于腐蚀工艺监控的表征器件

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US5094697A (en) * 1989-06-16 1992-03-10 Canon Kabushiki Kaisha Photovoltaic device and method for producing the same
JP3214631B2 (ja) * 1992-01-31 2001-10-02 キヤノン株式会社 半導体基体及びその作製方法
JP4126747B2 (ja) * 1998-02-27 2008-07-30 セイコーエプソン株式会社 ３次元デバイスの製造方法
US6133582A (en) * 1998-05-14 2000-10-17 Lightspeed Semiconductor Corporation Methods and apparatuses for binning partially completed integrated circuits based upon test results
JP5121103B2 (ja) * 2000-09-14 2013-01-16 株式会社半導体エネルギー研究所 半導体装置、半導体装置の作製方法及び電気器具
US6965895B2 (en) * 2001-07-16 2005-11-15 Applied Materials, Inc. Method and apparatus for analyzing manufacturing data

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI728778B (zh) * 2020-02-20 2021-05-21 大陸商長江存儲科技有限責任公司 具有xtacking架構的動態隨機存取儲存器（dram）記憶體元件
US11735543B2 (en) 2020-02-20 2023-08-22 Yangtze Memory Technologies Co., Ltd. DRAM memory device with xtacking architecture
US12159849B2 (en) 2020-02-20 2024-12-03 Yangtze Memory Technologies Co., Ltd. DRAM memory device with Xtacking architecture

Also Published As

Publication number Publication date
AU2003304218A8 (en) 2005-01-04
US7056751B2 (en) 2006-06-06
KR20050083935A (ko) 2005-08-26
CN1742358A (zh) 2006-03-01
TW200428538A (en) 2004-12-16
JP2006520089A (ja) 2006-08-31
US20040241888A1 (en) 2004-12-02
EP1573788A3 (en) 2005-11-02
TW200421497A (en) 2004-10-16
WO2004112089A2 (en) 2004-12-23
WO2004112089A3 (en) 2005-09-15
EP1573788A2 (en) 2005-09-14
AU2003304218A1 (en) 2005-01-04

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