WO2007019487A2

WO2007019487A2 - Method and system for fabricating thin devices

Info

Publication number: WO2007019487A2
Application number: PCT/US2006/030849
Authority: WO
Inventors: Sadeg M. Faris
Original assignee: Reveo, Inc.
Priority date: 2005-08-05
Filing date: 2006-08-07
Publication date: 2007-02-15
Also published as: WO2007019493A2; WO2007019493A3; WO2007019487A3

Abstract

Provided herein are various methods of and systems for fabricating ultra thin devices, multilayer devices, and vertically integrated devices. In one embodiment of the invention, a method of making a thin layer having a useful device thereon includes providing a device layer on a substrate with a release layer between the device layer and the substrate; forming one or more devices on the device layer; and separating the device layer from said substrate via processing of said release layer while minimizing or obviating damage to said devices formed on said device layer.

Description

METHOD AND SYSTEM FOR FABRICATING ULTRA THIN DEVICES AND

MULTI LAYER DEVICES

By Sadeg M. Fans, Ph.D.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No.60/705,925 filed on August 5, 2005 entitled "Method and System for Fabricating Milti Layer Devices", which is incorporated by reference herein.

TECHNICAL FIELD

[001] The invention relates to a method and system for fabricating multi layer active devices on a substrate, and more particularly to fabricating vertical integrated circuits, microelectromechanical devices, and microfluidic devices on a substrate.

BACKGROUND OF THE INVENTION

[002] The demand for faster and cheaper integrated circuits is ever growing. Moore's

Law posits that the number of transistors per square inch would double every year. However, as traditional two dimensional (or planar) chipmaking methods are reaching its boundaries, in order to fulfill the prophecy of Moore's Law, more innovative techniques for expanding the chipmaking frontiers are necessary.

[003] Heretofore, most of the demand for denser integrated circuits has been met by ever shrinking active devices fabricated on a relatively planar structure. That is, two dimensional chipmaking has been the predominant method of semiconductor fabrication.

Most semiconductor devices have been built in a planar monocrystalline semiconductor substrate. This approach allows only very limited vertical integration into the third dimension.

[004] As the limitations of two dimensional chip making are approaching, major breakthroughs in performance will be derived from three dimensional chipmaking (that is, chipmaking in the z-dimension).

[005] Vertical integration, or stacking of microdevices into the same package, is an attractive way to decrease packaging volume, to increase circuit density and to conserve board space, and to increase performance and functionality. Reductions of interchip delays and power consumption are both benefits of stacked integration. If the devices are thinned and stacked on top of each other, the advantages in cost and circuit density are potentially huge. For both IC and MEMS processes, the third dimension of the silicon wafer remains largely unexploited.

[006] Current commercial approaches to vertical stacking of 2-dimensional devices are generally chip-scale and rely on wafer thinning by grinding. Most methods rely on interconnection by way of throughholes or wire-bonded, stacked mother-daughter chips. Current methods all have limitations with respect to package size, cost, reliability and yield impact. Despite the difficulties, stacking devices to achieve 3-D integration is finding applications, particularly in combining Micro Electromechanical Systems ("MEMS") with Application Specific Integrated Circuits ("ASIC") controllers. High density memory packages made by stacking individual chips have found specialty applications.

[007] IBM United States Patent No. 6,355,501 discloses a method of fabricating a three- dimensional IC assembly, generally on chip scale. Disclosed therein is assembly consisting of three dimensional stacked Silicon on Insulator (SOI) chips, and a method of forming such integrated circuit assembly. Each of the SOI chips includes a handler making mechanical contact to a first pattern making electrical contact to a semiconductor device. The metalized pattern, in turn, contacts a second metallization pattern positioned on an opposite surface of the semiconductor device. The disclosed method includes the steps of: a) providing a substrate having a third metalized pattern on a first surface of the substrate; b) aligning one of the SOI chips on the first surface of the substrate, by having the second metallization pattern of the SOI chip make electrical contact with the third metalized pattern of the substrate; c) removing the handler from the SOI chip, exposing the first metallization pattern of the SOI chip; d) aligning a second one of the SOI chips with the first SOI chip, having the second metallization pattern of the second SOI chip make electrical contact to the exposed first metallization pattern of the first SOI chip; and e) repeating steps c) and d) for mounting subsequent SOI chips one on top of the other. However, this reference teaches a method that may be prohibitively expensive and severally functionally limited. [008] A key disadvantage of the method taught in the aforementioned U.S. Patent No. 6,335,501 is that the applicants thereof note that forming three-dimension circuits on a wafer scale leads to low yield. Further, alignment of each chip is considered to be a significant problem preventing wafer scale stacking. Each chip stacking step includes alignment of the layers to be bonded to each other. Transparent adhesives and windows must be provided to allow optical access to the alignment marks on both surfaces to be bonded to each other. Further, the handler must be transparent to the alignment marks. Other disadvantages relate to the number of sequential repeated process steps. As described therein, to make electrical contract between stacked layers, a solder reflow step is performed between each layer when it is stacked and aligned. After reflow, the chip stack is edge bonded. Further, the handler must be removed by glue removal (by laser or other heating), polishing, and other preparation steps before the subsequent layer may be bonded. Finally, excess substrate is grinded or otherwise etched-back for removal. [009] These drawbacks lead to several disadvantages related to cost and functionality. Cost detriments are found with the grinding removal; numerous sequential steps; chip scale as opposed to wafer scale stacking, wherein wafer scale is known to reduce cost; inability to overcome yield issues on wafer scale thus reverting to chip scale; limitation of the number of layers, thus to form higher number stacks, stacks must be stacked on other stacks; overall yield is decreased because the number of sequential statistically dependant through interconnects; multiple reflow steps potentially damage other layers; . Functionality drawbacks include lack of diagnostics; lack of interconnect versatility; limited space for interconnects; limited addressability of large stack, particularly memory stack; no ability to integrate noise shielding; no ability to integrate heat dissipation; no ability of ground plane; limitation of the number of layers.

[010] One implementation of 3-dimensional packaging has been undertaken by Irvine Sensors, Irvine, CA, and IBM. Discrete die have been stacked and interconnected utilizing an edge lift-off process.¹ Known-good-die (KGD) are thinned. Solder bumps at the die edge are used to align and interconnect the stacked die. The die are potted in an epoxy matrix. The epoxy helps to align different sized die, and is used as the interconnect surface. The individual stacking and interconnection of die, along with the requirement for KGD causes this to be a very expensive manufacturing method. [011] Another implementation of 3-dimensional packaging has been undertaken by Cubic Memory, who manufactures high-density, stacked memory modules by applying gold interconnect traces that are deposited over insulating layers of polyimide on whole wafers. However, stacking and vertical interconnect is still on an individual chip-scale.

¹ J. Minahan, A. Pepe, R. Some, and M. Suer, "The 3D stack in short form (memory chip packaging)," Proceedings 42nd Electronic Components and Technology Conference, San Diego, CA, (1992) [012] A further implementation of 3-dimensional packaging has been undertaken by Tessera, San Jose, CA₅ in conjunction with Intel, to develop chip-scale, stacked package by attaching the chips onto flexible substrates via micro-ball grid array bonding, then z-folding the chip-loaded tape onto itself. [013] Ziptronix is apparently developing wafer-scale stacking of ICs. Considerable challenges with alignment, stress management, thermal management, high density interconnect and yield are still being addressed.

[014] As illustrated above, there are various deficiencies with available vertical integration. One primary deficiency is due to yield loss. All approaches to device stacking that are currently in the marketplace are die-scale. Individual die are prepared, aligned, stacked and connected. The processing is expensive and the yield loss for the stack is the compounded yield loss for each device in the layer. The increased yield loss is sometimes tolerated for inexpensive devices such as SRAM stacks. But when more expensive devices are being stacked, the solution is to use known good die (KGD). For KGD, each unpackaged die undergoes burn-in and test Furthermore, the stack requires electrical test after the completion of each layer. The process is very expensive and the applications have been limited to high end users, such as military and satellite technology. [015] Another deficiency of conventional vertical integration is due to the fact that the technology is limited to a die-scale. With the exception of the yet-to-reach-the market approach of Ziptronix, all of the approaches to stacking devices are on die scale. The significant economic advantage of wafer-scale manufacturing is completely unavailable to these technologies. The high cost of handling and testing individual die restricts these methods to high-end applications. [016] Another problem known throughout conventional manufacturing processes forming circuits is the requirement to support the processing device on a substrate. During processing, the substrate is required to provide mechanical support and thermal stability. The processed substrate, therefore, must be sufficiently thick to withstand the harsh processing environment, including high pressures and temperatures, as well as chemical and energy exposure. Further processing is therefore required if viable thin film devices are sought [017] One processing approach, undertaken after a circuit or other structure is formed on a sufficiently thick substrate to withstand processing, is to remove the thickness of the substrate by mechanical methods. These mechanical methods, such as cutting or grinding, waste a tremendous amount of material and labor. The cut or ground material often may not be recycled, or, even if it is recyclable, the material must undergo further processing before reuse. Further, the thinned substrate is generally subjected to polishing or other processes to smooth the surface. Other techniques include formation of an etch stop layer on the substrate prior to device fabrication. However, the substrate is still typically ground or otherwise mechanically removed prior to a selective etching step, which etches the substrate generally to the etch stop layer. All of these techniques result in wasted time and material, as well presenting quality control concerns.

[018] Another technique to form thin film devices utilizes ion implantation methods. A common use of ion implantation is to generally derive thin layers of semiconductor materials. Such methods are disclosed in, for example, EP01045448 and WO00/024059, both entitled "Method of Producing SOI Wafer by Hydrogen Ion Implanting Separation Method and SOI Wafer Produced by the Method," and both incorporated by reference herein. Particularly, ions, such as hydrogen ions or helium ions, are implanted within the top surface of an oxidized silicon wafer. The ions are implanted to a depth within the top surface. Thereafter, a thin layer may be delaminated from the bulk silicon substrate, which is generally subjected to high temperature (greater than about 500⁰C) processes. This thin layer may be then supported on an insulator layer and a substrate, and microelectronics or other structures may be formed thereon. The microelectronics, however, must be formed subsequent to delaminating the thin layer, since ion implantation detrimentally affects the microelectronics. Particularly, the thin layer may be warped, the devices may be damaged by the ion implantation, or the device may be damaged during delamination. [019] Bruel et al. WO 98/33209, entitled "Method For Obtaining A Thin Film, In Particular Semiconductor, Comprising A Protected Ion Zone And Involving An Ion Implantation", discloses an approach to providing a thin film including a metal oxide semiconductor (MOS). In general, a MOS transistor is formed on the surface of a semiconductor substrate. The region of the transistor is masked, and surrounding regions are ion implanted to define an intended line of fracture (i.e., where microbubbles develop from the ion implantation step). To separate the thin film having the transistor thereon, cleavage is commencing at the intended line of fracture in the vicinity of the microbubbles, and is propagated through the crystal plane under the transistor (i.e., where no microbubbles exist). While it may be possible to realize thin films having transistors thereon using the teachings of WO 98/33209, the transistors are subjected to undesirable stress in the cleavage propagation, since the crystalline structure of the substrate material must be fractured in the immediate vicinity of the transistor.

[020] Aspar et al. U.S. Patent No. 6,103,597 entitled "Method Of Obtaining A Thin Film Of Semiconductor Material" generally teaches subjecting a thin film substrate having microelectronics or other structures therein to ion bombardment. Gaseous microbubbles are thus formed at a depth therein defining the thickness of the thin film. However, many types of microelectronics and structures that may be formed on the substrate require a subsequent annealing step, in order to repair damage or other defects imparted to the elements. Thereafter, the thin film layer is taught to be separable from the underlying substrate material by thermal treatment that causes a fracture along the line of the microbubbles. [021] Sakaguchi et al., Unites States Patent Nos.6,221,738 entitled "Substrate And Production Method Thereof and 6,100,166 entitled "Process For Producing Semiconductor Article", both of which are incorporated by reference herein, teach bonding a substrate to a porous semiconductor layer. The bonding at the porous layer is taught to be mechanically weaker, thus facilitating removal by application of an external force. U.S. Patent No.

6,100,166 teaches that a layer may be removed with a force in a peeling direction. However, both of these references disclose use of the weak porous separation mechanism at the entire interface between the layers. This may compromise overall mechanical integrity of the intermediate structure and any semiconductor devices formed on the porous semiconductor material.

[022] Henley et al., Unites States Patent No.6,184,111 entitled "Pre-Semiconductor Process Implant And Post-Process FUm Separation," which is incorporated by reference herein, discloses use of a stressed layer at a selected depth below a silicon water surface. Devices are formed above the stressed layer. Implantation is generally carried out at the same energy level with varying dosage across the diameter of the wafer. Controlled cleavage propagation is initiated to separate a layer above the stressed layer, including any devices thereon. It is noted that processing to form the stressed layer may damage devices formed thereon, thus subsequent repair annealing is typically required. Therefore, conventional ion implantation and delamination methods are lacking in that a thin film including microelectronics or other structures thereon may not be ion implanted without warping or other damage to the thin semiconductor.

[023] Figure IA shows an embodiment of a conventional SOI (silicon-on-insulator) configuration 100 widely used in a multitude of semiconductor configurations and processes. The SOI 100 typically includes a non-porous single crystal Si layer 101 attached to a bulk Si substrate 102 via a Si oxide layer (insulator) 103. [024] Referring to Figures IB-ID, typical methods for forming these SOI substrates include using a porous layer 108 on a Si substrate 107. After non-porous single crystal Si layer 101- is epϊtaxially grown on the porous layer 108, it is bonded to bulk Si substrate 102 via Si oxide layer 103. The Si substrate 107 is removed, for example, by grinding to expose the porous layer 108. The porous layer 108 may be removed, for example, by selective etching with a suitable etchant such as KOH or HF + H2O2, resulting in the SOI 100 of Figure IA. According to conventional approaches, the SOI 100 is used as a substrate for processing one or more devices on the non-porous single crystal Si layer 101. The resultant structure includes bulk silicon 102, therefore it is limited in its ability for adaptation to vertically integrated, devices.

[025] Therefore, considering the deficiencies of present circuit processing, it would be desirable to provide a three-dimensional integrated circuit, on a chip or on a wafer scale, which avoids the drawbacks and shortcomings of the conventional approaches.

BRIEF SUMMARY OF THE INVENTION

[026] Provided herein are various methods of and systems for fabricating ultra thin devices and multi layer devices. In one embodiment of the present invention, a method of making a thin layer having a useful device therein or thereon includes providing a device layer on a substrate with a release layer between the device layer and the substrate; forming one or more devices on the device layer; and separating the device layer from said substrate via processing of said release layer while minimizing or obviating damage to said devices formed on said device layer.

[027] In another embodiment of the present invention, a method of making a vertically integrated device includes providing a first multilayer structure comprising a first substrate, a first mechanically weak layer and a first material layer; providing a second multilayer structure comprising a second substrate, a second mechanically weak layer and a second material layer; bonding the first structure to the second structure; detaching the first substrate from the first weak layer; removing the remnants of the first weak layer; making a device structure in the first material ; detaching the second substrate from the second weak layer; bonding the first and the second material layers to form a first device layer to a third substrate; andmaking a multi device-layer structure by aligning and bonding the second device layer to first device layer.

[028] In another embodiment of the present invention, a method of making a vertically integrated devices includes providing a structure A with 3 layers IA, 2A, 3A, wherein layer 2A is a release layer such that a layer IA is releasable from a substrate layer 3A; making a device A on layer IA; separating device layer IA; providing a structure B with layers IB, 2B, 3B, wherein layer 2B is a release layer and a layer IB is releasable from a substrate layer 3B; making a device B on layer IB; releasing device layer IB; and aligning and bonding layers IA and IB.

BRIEF DESCRIPTION OF THE EIGDRES

[029] The foregoing summary as well as the following detailed description of preferred embodiments of the invention will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there is shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. In the drawings, where:

[030] Figures 1A-1D show prior art formation of silicon on insulator structures; [031] Figures 2A-2F show a method and system for making a thin device layer according to various embodiments of the present invention; [032] Figures 3 A-3G show another method and system for making a thin layer with a useful device thereon or therein including a release layer having a sub-layer of first porosity

Pl and a sub-layer of second porosity P2;

[033] Figures 4 A-4F show another method of making a thin device layer according to various embodiments of the present invention;

[034] Figures 5A-5F show a further method of making a thin device layer according to various embodiments of the present invention;

[035] Figures 6A-6E show a method of making a thin device layer according to various embodiments of the present invention wherein edges of the structure are bonded; [036] Figures 7A-7E show a further method of making a thin device layer according to various embodiments of the present invention wherein edges of the structure are bonded;

[037] Figures 8A-8B show various embodiments of the locales of edge bonding according to Figures 6A-7E;

[038] Figure 9 is a schematic cross-section diagram of a selectively bonded multi layer substrate according to various embodiments of the present invention;

[039] Figures 10A- 15B provide schematic cross-sectional diagrams of a selectively bonded multi layer substrate according to various embodiments of the present invention, wherein various methods of forming weak and strong bond regions are shown; [040] Figures 16A-16G show top views of various geometries of bond regions of a wafer according to various embodiments of the present invention;

[041] Figures 17A-21 show schematic illustrations of various debonding techniques according to various embodiments of the present invention;

[042] Figures 22A, 22B, 22C, 22D and 22E show a top view of an embodiment of the present invention for enhanced processing; shows sectional views along lines A-A, B-B arid C-C; sectional views along lines A-A₅ B-B and C-C after removal of material at regions other than the device regions and the connection regions; a top view of plural device regions connected with connector regions formed according to the embodiments of Figures 22A-22C; and a stack of device regions that may be formed by stacking structures as shown in Figure 22D, respectively; [043] Figures 23 A and 23B show a top view of another embodiment of the present invention for enhanced processing, and a top view of plural device regions connected with connector regions and a peripheral connector portion formed according to the embodiment of

Figures 23A, respectively;

[044] Figures 24A and 24B-24D show a top view of a further embodiment of the present invention for enhanced processing and processing steps at sectional views along line B-B, respectively;

[045] Figure 25 shows a process is shown for forming single crystalline silicon wafers out of a cylindrical boule;

[046] Figure 26 shows a method is shown for growing a single crystal silicon layer; [047] Figure 27 shows an isometric schematic of a stack of N wafers and a die cut therefrom;

[048] Figure 28 shows a general method of forming a vertically integrated device;

[049] Figures 29A-29D show another general method of forming a vertically integrated device including a pair of structures having a device layer, a release layer and a support layer; aligning the structures; removing one support layer; and removing both support layers, respectively;

[050] Figure 30 shows a multilayer structure according to embodiments of the present invention; ^■ [051] Figures 31 A-3 ID show a device layer having edge extending conductors; stacking plural device layers having edge extending conductors; dicing the stack; and forming edge interconnects along plural edge extending conductors, respectively;

[052] Figures 32A-32D show a device layer having plural edge extending conductors; stacking plural device layers having plural edge extending conductors; dicing the stack; and forming plural edge interconnects along plural edge extending conductors, respectively;

[053] Figures 32E-32F show an isometric view of a vertically integrated chip without interconnects and with interconnects, respectively;

[054] Figure 33 shows another example of a device layer suitable for chip edge architecture according to certain embodiments of the present invention;

[055] Figures 34A-34C show a device layer having through conductors; stacking plural device layers having through conductors; and dicing the stack, respectively;

[056] Figure 35 shows another example of a through interconnect according to certain embodiments of the present invention; [057] Figure 36 shows a further example of a through interconnect according to certain embodiments of the present invention;

[058] Figures 37A-37C show steps for forming a device layer with through interconnects according to certain embodiments of the present invention;

[059] Figures 38A-38D show a device layer having edge extending conductors and through conductors; stacking plural device layers having edge extending conductors and through conductors; dicing the stack; and forming edge interconnects along plural edge extending conductors, respectively;

[060] Figures 39A-39B show formation of a device layer upon an oxide layer; [061] Figures 40A-40D show formation of a device layer upon an oxide layer and stacking plural layers to form a vertically integrated device; [062] Figure 41 shows another device layer on an oxide layer;

[063] Figure 41 shows an example of a method of enhancing the interconnection area on a device;

[064] Figure 42 shows an example of a method of forming interconnects using thermo- electric migration;

[065] Figure 43 shows an example of a method of forming interconnects using plug fill regions;

[066] Figure 44 shows an example of a method of forming interconnects using tapered via holes to access metallization regions; [067] Figures 45-48show various embodiments of shielding and channels for various enhancements herein;

[068] Figures 49A-49C show various embodiments of formation of MEMs devices in accordance with embodiments of the present invention;

[069] Figures 50A-52B show various features and aspects of a crossbar switch formed according to embodiments of the present invention;

[070] Figures 53A-53D show steps in forming coaxial interconnects in accordance with embodiments of the present invention;

[071] Figures 54A-54B show a structure and method of making a structure, respectively, having plural stacks associated with one another; [072] Figures 55A-55B show a further structure and method of making a structure, respectively, having plural stacks associated with one another;

[073] Figures 56A-56B show a further structure and method of making a structure, respectively, having plural stacks associated with one another;

[074] Figures 57A-57B show a further structure and method of making a structure, respectively, having plural stacks associated with one another; [075] Figures 58A-58B show a further structure and method of making a structure, respectively, having plural stacks associated with one another;

[076] Figures 59A-59B show a further structure and method of making a structure, respectively, having plural stacks associated with one another; [077] Figures 60A-60C show various embodiments of plural stacks interconnected with additional interconnecting stacks, whereby the interconnecting stacks are provided generally normal relative the plural stacks, generally parallel relative the plural stacks, and generally at an angle relative the plural stacks, respectively;

[078] Figures 61-67 show various alignment techniques according to aspects of the present invention;

[079] Figure 68 shows an alignment device according to embodiments of the present invention;

[080] Figure (A9) shows an alignment method using tapered holes according to embodiments of the present invention; [081] Figures 70a and 70b show an alignment and interconnection method for wafer level stacking according to embodiments of the present invention;

[082] Figure 71 shows an optical alignment technique according to embodiments of the present invention;

[083] Figures 72 and 73 show an embodiment of the present invention as a hybrid handler/LC aligner, various conductor patterns, respectively; and

[084] Figure 74 show a sorting method according to various embodiments of the invention;

[085] Figure 75-77 show embodiments of forming vertically integrated devices with a desired number of known good die in accordance with the principles of the invention; [086] Figure 78 shows a schematic of an exemplary stack of N wafers including M dies on each wafer, showing for further reference herein a yield of p good die per layer;

[087] Figure 79 shows a probability distribution of the number of good layers based on varying values of p; [088] Figure 80 shows a probability distribution for a stack of 200 layers of the number of good layers based on varying values of p;

[089] Figure 81 shows plural stacks integrated together to form a stack with a desired number of known good layers; and

[090] Figure 82 shows a probability distribution of the number of good layers versus the yield per layer p based on varying values of the number of layers N.

1. DETAILED DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENTS

[091] In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, one having ordinary skill in the art should recognize that the invention may be practiced without these specific details. In some instances, well-known structures, circuits, devices and techniques have not been show in detail to avoid obscuring the present invention.

[092] The present invention provides a method of fabricating a thin film with one or more useful devices thereon or thereon. The film with one or more useful devices thereon or thereon may later be bonded, in the third dimension, to another layer or wafer that already has a layer of useful devices therein or thereon. Thus, by using films or layers formed according to embodiments of the present invention described herein, a vertically integrated device, with several layers, including 10s, 100s or even 1000s of layers, may be fabricated. These devices may be useful for three-dimensional applications including but not limited to integrated circuits; MEMs; microfluidics; memory devices such as DRAM, SRAM, flash memory; photovoltaic devices; thermo-electric devices; power devices, analog devices, RF devices (such as RFID); optical devices; photonic devices; probes and/or probe arrays, and other useful devices that may benefit from vertical integration. Further, certain embodiments of the present invention may be useful as single layer devices, particularly where it is desirable to reduce layer thickness, reduce processing costs, conserve materials, increase mechanical flexibility, and increase versatility of integration with other devices and systems. [093] Referring now generally to Figures 2A-2F, a method and system for making a thin layer 220 making a thin layer with a useful device thereon or therein is provided according to various embodiments of the present invention. Figure 2A shows a bulk substrate 202 as a starting material for the methods and structures of the present invention. Referring to Figure 2B, a release inducing layer 218 is created at a top surface of the bulk substrate 202. This release inducing layer 218 may include a porous layer or plural porous layers. The release inducing layer 218 may be formed by treating a major surface of the bulk substrate 202 to form one or more porous layers 218. Alternatively, the release inducing layer 218 in the form of a porous layer or plural porous layers may be derived from transfer of a strained layer to the bulk substrate 202.

[094] Further, the release inducing layer 218 may include a strained layer with a suitable lattice mismatch that is close enough to allow growth yet adds strain at the interface. For example, for a single crystalline silicon substrate 202, the release inducing layer in the form of a strained layer may include silicon germanium², other group HI-V compounds, InGaAs, MAl, indium phosphides, or other lattice mismatched material that provides for a lattice mismatch that is close enough to allow growth, in embodiments where single crystalline

² For example, U.S. Patent No.6,790,747 to Silicon Genesis Corporation, incorporated by reference herein, teaches using a silicon alloy such as silicon germanium or silicon germanium carbon, in the context of forming SOI; S.O.I.Tec Silicon on Insulator Technologies S.A. U.S. Patent No.6,953,736, incorporated by reference herein, discloses using a lattice mismatch to form a strained silicon-on- insulator structure with weak bonds at intended cleave sites. 30849

material such as silicon is grown as the deice layer 220, and also provide for enough of a mismatch to facilitate release while minimizing or eliminating damage to devices 222 formed in or upon the device layer 220. The release inducing layer 218 may be formed by treating (e.g., chemical vapor deposition, physical vapor deposition, molecular beam epitaxy plating, and other techniques, which include any combination of these) a major surface of the bulk substrate 202 with suitable materials to form a strained layer 218 with a lattice mismatch to the device layer 220 (e.g., silicon germanium when the device layer 220 and the substrate 202 are formed of single crystalline Si). One key feature of the release layer, particularly in the form of the strained layer, is that at least a portion of the release layer comprises a crystalline structure that is lattice mismatched compared to the bulk substrate and the device layer to be formed or stacked atop the release layer. Alternatively, the release inducing layer 218 in the form of a strained layer may be derived from transfer of a strained layer to the bulk substrate 202.

[095] In other preferred embodiments, the release inducing layer comprises a layer having regions of weak bonding and strong bonding (as described in detail in Applicant's copending U.S. Patent Application Serial No.09/950,909 filed on 9/12/2001 and U.S. Patent Application Serial No. 10/970,814 filed on October 21, 2004, both entitled "Thin films and Production Methods Thereof incorporated by reference herein, and further referenced herein as "the '909 and ' 814 applications"). [096] Still further, the release inducing layer may include a layer having resonant absorbing material (Le., that absorbs certain exciting frequencies) integrated therein. For example, when certain exciting frequencies are impinged on the material such as during debonding operations, resonant forces cause localized controllable debonding by heating and melting of that material. [097] Referring to Figure 2C, a device layer 220 is formed on top of or within the release layer 218. In certain preferred embodiments, the device layer 220 is epitaxially grown, e.g., as an epitaxial single crystal silicon layer. In still further alternative embodiments, the device layer may be attached to the release layer and placed atop the substrate layer or bulk substrate 202. For example, a suitable vacuum handler (such as one formed as described in 10/017,186 filed December 7, 2001 entitled "Device And Method For Handling Fragile Objects, And Manufacturing Method Thereof, incorporated by reference herein, or other vacuum handlers) may be used to hold and transfer a thin layer as mentioned above. [098] A buried oxide layer may optionally be provided below the device layer 220. For example, after the step described with respect to Figure 2B₅ a portion of the release layer 218 may be formed into an oxide layer or region. Alternatively, portions of the release layer 218 may be treated to form buried oxide regions. Further, in another example, after the step described with respect to Figure 2C, a portion of the release layer 218 may be formed into an oxide layer or region, e.g., with suitable implantation treatment, or treated to form buried oxide regions. In a further alternative, where the device layer is attached to the release layer, the surface of the device layer intermediate the release layer may be treated to form an oxide layer, or an oxide layer may be deposited on the surface of the device layer intermediate the release layer. [099] Referring to Figure 2D, one or more devices 222 may be formed in or upon the device layer 220. In certain embodiments, the device layer has wafer scale dimensions, whereby plural devices 222 are formed on the wafer. The release layer 218 allows the device layer 220 to be sufficiently bonded to the bulk substrate 202 such that during processing of the devices 222, overall structural stability remains. [0100] Referring now to Figure 2F, the device layer 220 having devices 222 thereon or therein may easily be separated from the bulk substrate 202. As shown in Figure 2G, the device layer may optionally include a portion 218' of the release layer. This may be kept with the device layer, or removed by conventional methods such as selective etching or grinding. This allows one to have a very thin device layer that may be used alone, e.g., for ultra thin semiconductor devices according to certain embodiments hereof. Alternatively, the thin device layer may be stacked to form vertically integrated circuit or device. Further, the remaining substrate 202 (which may have a portion 218" of the release layer) remains behind, which may be recycled and reused in the same or similar process after any necessary polishing.

[0101] Accordingly, a method to make thin device layer utilizing the release layer described above with respect to Figs 2A-2F includes providing a structure A with 3 layers IA, 2A, 3A, wherein layer IA is a device layer, layer 2A is a release layer, and layer 3A is a support layer. In this manner, layer IA is releasable from layer 3 A. One or more useful devices are fabricated on the device layer IA. Then, device layer IA may be released from support layer 3A. The support layer 3A may be reused for subsequent processes, e.g., as a support layer or as a device layer.

[0102] As shown in Figures 2A-2F, release layer 218 may comprise a layer of porous material, such as porous Si. In a further alternative embodiment, and referring now generally to Figures 3A-3G, a method and system for making a thin layer with a useful device thereon or therein is provided, wherein the release layer comprises a sub-layer 318 of first porosity Pl and a sub-layer 326 of second porosity P2. Thus, the release layer comprises a porous release layer having a sub-layer region of relatively large pores Pl proximate the substrate and a sublayer region of relatively small pores P2 proximate the device layer. In certain embodiments, sub-layer region Pl is formed directly on said substrate. In other embodiments, sub-layer region P2 is grown on said sub-layer region Pl . Note that although these representations show distinct sub-layers 318 of first porosity Pl and sub-layers 326 of second porosity P2, other porosity gradients across the thickness of the overall release layer may be used. [0103] Figure 3 A shows a bulk substrate 302 as a starting material for the methods and structures of the present invention. Referring to Figure 3B, a porous layer Pl (318) is created at a top surface of the bulk substrate 302.

[0104] Referring to Figure 3C, a second porous layer P2 (326) may be formed on the first porous layer Pl (318). In certain embodiments, a layer 326 may be stacked and bonded to layer 318. In certain other embodiments, a layer 326 may be grown or deposited upon layer 318.

[0105] Referring to Figure 3D, a device layer 320 is formed on top of the porous layer P2 (326). In certain embodiments, the device layer 320 is epϊtaxially grown, e.g., as a single crystal silicon layer. In still further alternative embodiments, the device layer may be attached to the release layer, e.g., transferred to the release layer. [0106] A buried oxide layer may optionally be provided below the device layer 320. For example, after the step described with respect to Figure 3B or 3C, a portion of the layer 318 or 326 may be formed into an oxide layer or region. Alternatively, portions of the layer 318 or 326 may be treated for form buried oxide regions. Further, in another example, after the step described with respect to Figure 3D, a portion of the layer 318 or 326 may be formed into an oxide layer or region, e.g., with suitable implantation treatment, or portions of the layer 318 or 326 may be treated to form buried oxide regions. Alternatively, where the device layer is attached to the layer 326, the surface of the device layer intermediate the release layer may be treated to form an oxide layer, or an oxide layer may be deposited on the surface of the device layer intermediate the release layer. T/US2006/030849

[0107] Referring to Figure 3E₅ one or more devices 322 may be formed on the device layer. In certain embodiments, the device layer has wafer scale dimensions, whereby plural devices 322 are formed on the wafer. The layer 318 or 326 allows the device layer 320 to be sufficiently bonded to the bulk substrate 302 such that during processing of the devices 322, overall structural stability remains.

[0108] Referring now to Figure 3F₅ the device layer 320 having devices 322 thereon or therein may easily be separated from the bulk substrate 302. As shown in Figure 3G, the device layer may optionally include a portion 326 of the porous layer P2. This may be kept with the device layer 320, or removed by conventional methods such as selective etching or grinding.

[0109] As shown in Figures 2A-2F and 3A-3G, release layer 218 may comprise a layer of strained material, such as a layer of silicon-germanium (SiGe). For example, a layer of SiGe may be grown on a the substrate layer. Since germanium has a larger lattice constant than Si, the SiGe layer is compressively strained as it grows. [0110] Referring now to Figures 4A-4F, another method of making a thin layer including one or more useful devices therein or thereon is provided. A bulk substrate 402 is provided (Figure 4A). Referring to Figure 4B, all or a portion of a surface 404 of the bulk substrate 402' is treated to form a region 406. In this embodiment, as described below, region 406 is formed of a material and/or having material characteristics to allow growth of a layer on top thereof, and also serve as a portion of the release layer, wherein portion 406 represents a weak bond region as described above and described in further detail in Applicant's copending the '909 and '814 applications incorporated by reference herein. In the embodiment shown with respect to Figures 4A-4F, a portion of the surface 404 of the bulk substrate 402' is treated, whereby portions 408 of the surface 404 remain as the original bulk substrate which (shown in Figures 4B-4F as the periphery, but it is to be understood that other patterns may be created as described in Applicant's copending the '909 and '814 applications incorporated by reference herein). These portions represent strong bond regions as described in the '909 and '814 applications.

[0111] Referring now to Figure 4C, a single crystalline material layer 410 such as single crystalline silicon is epitaxially grown on top of the weak and strong regions 406, 408. Figure 4D shows devices 412 fabricated upon or within the single crystalline material layer 410. Referring to Figure 4E, portions of the single crystalline material layer 410 are removed corresponding to the regions of the portions 408, and the portions 408 are removed, for example by chemical etching, mechanical removal, hydrogen or helium implantation and heating of the portions 408, or providing a material containing a resonant absorber at the portions 408 for subsequent heating and melting of that material. Accordingly, a modified single crystalline material layer 410' on the portion 406 remains. Figure 4F shows the portion 406 removed, thereby leaving single crystalline material layer 410' with devices 412 thereon or therein. Alternatively, single crystalline material layer 410' with devices 412 thereon or therein may be removed from the portion 406, for example, by mechanical cleavage (parallel to the plane of the layers), peeling, or other suitable mechanical removal, whereby some residue of the portion 406 may remain on the back of the single crystalline material layer 410' with devices 412 thereon or therein and some residue of Ae portion 406 may remain on the top of the bulk substrate 402" left behind. In this manner, the bulk substrate 402' ' may be recycled and reused with minimal polishing and/or grinding, thereby minimizing waste of the single crystalline material of the bulk substrate 402.. The single crystalline material layer 410' with devices 412 thereon or therein may be used as is, diced into individual devices or structures, or aligned and stacked (on a device or structure scale, or on a wafer scale) to form a vertically integrated device. [0112] In certain embodiments, the strong bond portions 408 may be formed by starting with a uniform layer. For example, the surface 404 may comprise a strained material, such as silicon germanium. Utilizing zone melting and sweeping techniques, the germanium swept away from the desired strong bond regions 408. When a layer 410 is grown or formed on the layer having portions 406, 408, layer 410 will be strongly bonded at the regions of portions 408 and relatively weakly bonded at the regions of portions 406.

[0113] Referring now to Figures 5A-5F, another method of making a thin layer including one or more useful devices or structures therein or thereon is provided. A bulk substrate 502 is provided (Figure 5A). Referring to Figure 5B, all or a portion of a surface 504 of the bulk substrate 502' is treated to form porous sub-regions 505 and 506. In this embodiment, as described below, region 506 is formed of a material and/or having material characteristics to allow growth of a layer on top thereof, and also serve as a portion of the release layer, wherein porous sub-regions 506/505 represent a weak bond region as described above and described in further detail in the '909 and '814 applications incorporated by reference herein. In the embodiment shown with respect to Figures 5A-5F, a portion of the surface 504 of the bulk substrate 502' is treated (forming sub-regions 505/506), whereby portions 508 of the surface 504 remain as the original bulk substrate which (shown in Figures 5B-5F as the periphery, but it is to be understood that other patterns may be created as described in Applicant's copendingthe '909 and '814 applications incorporated by reference herein). These portions represent strong bond regions as described in the '909 and '814 applications. [0114] Thus, the release layer comprises sub-regions 505/506 and portions 508. Sub- region 505 has relatively large pores Pl proximate the substrate and sub- region 506 has of relatively small pores P2 proximate the device layer to be described below. In certain embodiments, sub-region 505 is formed directly on said substrate, and sub-region 506 is grown on said sub-region 505. In certain embodiments, sub-region 506 may be stacked and bonded to sub-region 505. In certain other embodiments, sub-region 506 may be grown or deposited upon sub-region 505.

[0115] Referring now to Figure 5C, a single crystalline material layer 510 such as single crystalline silicon is epitaxially grown on top of the weak and strong regions 506, 508. Figure 5D shows devices or structures fabricated upon or within the single crystalline material layer 510. Referring to Figure 5E. portions of the single crystalline material layer 510 are removed corresponding to the regions of the portions 508. and the portions 508 are removed, for example by chemical etching, mechanical removal, hydrogen or helium implantation and heating of the portions 508, or providing a material containing a resonant absorber at the portions 508 for subsequent heating and melting of that material.

Accordingly, we are left with a modified single crystalline material layer 510' on the portion 506. Figure 5E shows an exemplary cleaving device, for example a knife edge device, water jet, or other device, used to cut between the sub-regions 505 and 506. Figure 5F shows the bottom portion of sub-region 506 removed (with a portion of sub-region 506 remaining on the bottom of the single crystalline material layer 510), and the top portion of sub-region 505 removed (with a portion of sub-region 505 remaining on the bulk substrate 502"). Accordingly, the single crystalline material layer 510' is left with devices or structures 512 thereon or therein. In this manner, the bulk substrate 502" may be recycled and reused with minimal polishing and/or grinding, thereby minimizing waste of the single crystalline material of the bulk substrate 502. The single crystalline material layer 510' with devices or structures 512 thereon or therein may be used as is, diced into individual devices or structures, or aligned and stacked (on a device or structure scale, or on a wafer scale) to form a vertically integrated device.

[0116] Accordingly, according to the methods of Figures 2 and 3, a layered structure is formed generally includes a first layer suitable for having a useful element formed therein or T/US2006/030849

thereon releasably attached or bonded to a second layer, e.g., a substrate. A method to form a layered structure generally comprises releasably adhering a first layer to a second layer. Further, according to the methods of Figures 4A-5F, a layered structure is formed generally includes a first layer suitable for having a useful element formed therein or thereon selectively attached or bonded to a second layer, e.g., a substrate, with regions of weak bonding and regions of strong bonding. The layered structure may be used for production of various devices including probes and/or probe precursors as provided for herein. Alternatively, a layered structure may be used as a source of one or more probes and/or probe precursors, for example, when the device layer is used as the probe, whereby the capability to produce and remove with little or no damage allows for ultra thin layers that may be used for ultra high resolution probes.

[0117] The separation, for example, shown at steps of Figures 2E, 3F, 4E and 5E, may comprise various separation techniques. These separation techniques includes those described in further detail in Applicant's copending the '909 and '814 applications, incorporated by reference herein. The separation may be multi-step, for example, chemical etching parallel to the layers followed by knife edge separation. The separation step or steps may include mechanical separation techniques such as peeling, cleavage propagation; knife edge separation, water jet separation, ultrasound separation or other suitable mechanical separation techniques. Further, the separation step or steps may be by chemical techniques, such as chemical etching parallel to the layers; chemical etching normal to the layers; or other suitable chemical techniques. Still further, the separation step or steps may include ion implantation and expansion to cause layer separation.

[0118] The material for the layers used herein, as the device layer, the release layer and the substrate layer, may be the same or different materials, and may include materials including, but not limited to, semiconductor, insulator, one or more layers of carbon materials, such as one or more layers of graphene derived from lamellar graphite (e.g., as described in U.S. Application Serial No 11/ filed on July 28, 2006, under

Express Mail Label Number EV443782155US (Attorney Docket Number REVEO- 0260USAAPN38) entitled "Material Comprising Predetermined Number of Atomic Layers and Method For Manufacturing Predetermined Number of Layers", which is incorporated by reference herein) or formed according to other methods, plastic (e.g., polycarbonate), metal, biological (e.g., DNA based films) or a combination comprising at least one of the foregoing types of materials. Further, the materials may be in various forms (unless described as a particular form in certain embodiments above) such as monocrystalline, amorphous, or noncrystalline.

[0119] Further, the release layer may comprise a material layer having certain amounts of dopants mat excite at known resonances. When the resonance is excited, the material may locally be heated thereby melting the areas surrounding the dopants. This type of release layer may be used when processing a variety of materials, including organic materials and inorganic materials.

[0120] The device layer and the substrate layer may be derived from various sources, including thin films described herein, wafers or fluid material deposited to form films and/or substrate structures. Where the starting material is in the form of a wafer, any conventional process may be used to derive the device layer and/or the substrate layer. For example, the substrate layer may consist of a wafer, and the device layer may comprise a portion of the same or different wafer. The portion of the wafer constituting the device layer may be derived from mechanical thinning (e.g., mechanical grinding, cutting, polishing; chemical- mechanical polishing; polish-stop; or combinations including at least one of the foregoing), cleavage propagation, ion implantation followed by mechanical separation (e.g., cleavage propagation, normal to the plane of the layers, parallel to the plane of the layers, in a peeling direction, or a combination thereof), ion implantation followed by heat, light, and/or pressure induced layer splitting), chemical etching, or the like. Further, either or both the device layer and the substrate layer may be deposited or grown, for example by chemical vapor deposition, epitaxial growth methods, or the like. [0121] The dimensions of the device layers may also vary in thickness and surface area. For example, fabrication of nanoscale devices may benefit from the methods and embodiments herein whereby devices may be formed on layers that are a few tenths of a nanometer to a few nanometers. Fabrication of microscale devices may be formed on layers that are a few nanometers to a few microns in thickness. [0122] The surface areas for the methods and embodiments of the present invention may be die-scale, wafer scale, or in larger sheets; accordingly, surface areas may be on the order of nanometers) squared to a few microns squared for nano- and micro- die-scale; on the order of a centimeters squared for wafer-scale; and on the order of centimeters squared to a meters squared for sheet scale. [0123] The embodiments herein showing useful devices upon or within a device layer upon a substrate allow for processing of multiple chips on a wafer as is known and allows the device layer of the wafer to be readily removed, preferably without mechanical grinding or other etch-back techniques. This device layer then may be stacked on another device layer or alternatively, the chip layer may be diced into individual chips and stacked. [0124] Various embodiments herein utilize a release layer having regions of weak bonding and regions of strong bonding, whereby processing is performed on or in the regions of weak bonding and removal of the device layer is possible while minimizing or eliminating damage to useful devices formed thereon or therein. This is detailed below and is further described in the '909 and '814 applications. [0125] Referring now to Figures 6A-8B, various methods and structures are shown using strong bonds at the edges of release layers and/or stacks. These strong bonds are provided at the edges of the layers, in contrast to embodiments herein where the strong bond regions are provided at the interface between the device layer and the substrate, or as the release layer. [0126] Referring now to Figures 6A-6E, a method is shown of forming a supported device layer that is strongly bonded to a substrate yet readily releasable therefrom. Figure 6A shows a device layer 620 bonded to s substrate 602 with a release layer 618 therebetween. Referring now to Figure 6B, strong bond regions 632 are formed at the edge of the release layer 618 in a manner to provide a strong bond (relative to the remainder of Ae release layer 618, whereby the remainder of the release layer 618 can also be weak bond regions.

[0127] In particular, this strong bond region 632 may be formed to minimize or eliminate the likelihood of delaminating of device layer 620 from substrate 602 during processing of devices 622, shown in Figure 6C.

[0128] Referring to Figures 6D and 6E, the device layer 620' (having devices 622 therein or thereon) may be separated from substrate 602 by processing from the edges of the release layer. For example, the strong bond regions may be etched (in a direction parallel to the layers). By processing for separation only the strong bond regions 632, with minimal force required to peel, cleave or otherwise remove the device layer after processing of the strong bond regions 632, detriment to the devices 622 formed on the device layer 620 is minimized or eliminated. Processing for separation (or debonding) may occur as described herein. [0129] In one embodiment, the release layer 632 comprises a porous layer, such as porous Si. The strong bond 632 may be formed, for example, by growing single crystal Si at the edge of the porous release layer 618. The edge of the porous release layer 618 serves as a seed to grow single crystal Si. Under suitable conditions, e.g., within well known CVD reactors, a single crystal structure may be formed, providing a very strong bond relative the remainder of the porous Si release layer 618.

[0130] In another embodiment, the release layer 632 comprises a strained layer, such as SiGe. The strong bond 632 may be formed, for example, by growing single crystal Si at the edge of the release layer 618. The edge of the porous release layer 18 serves as a seed to grow single crystal Si. Under suitable conditions, e.g., within well known CVD reactors, a single crystal structure may be formed, providing a very strong bond relative the remainder of the SiGe release layer 618.

[0131] Referring to Figures 7A-7E, a similar method is described as compared to Figure 6A-6E, wherein a strong bond region 734 is formed at the edge of the device layer 720, the release layer 718 and the substrate 702. In certain embodiments, this will serve to further enhance the resistance to delamination during processing of devices 722 on device layer 720. [0132] In another embodiment, wherein strong bonding may be provided at the edges, either between device layer and substrate (Figures 6A-6E) or along an edge encompassing device layer and/or substrate edge(Figures 7A-7E), the release layer (relatively the weak bond region) comprises a porous release layer having a sub-layer region of relatively large pores Pl proximate the substrate and a sub-layer region of relatively small pores P2 proximate the device layer.

[0133] Referring to Figures 8A and 8B, alternative configurations for the edge grown strong bond regions are shown. For example, singe crystalline Si is grown an entire periphery of the release layer (or alternatively the stack including the device layer, release layer and substrate), as shown schematically in Figure 8A. Alternatively, singe crystalline Si can be grown at certain locales at the edge of the release layer (or alternatively the stack including the device layer, release layer and substrate), as shown schematically in Figure 8B. The structure of Figure 8B may be grown separately, or alternatively etched, cut, or otherwise subtracted.

[0134] Referring to Figure 9, a selectively bonded multiple layer substrate 100 is shown.

The multiple layer substrate 100 includes a layer 1 having an exposed surface IB, and a surface IA selectively bonded to a surface 2A of a layer 2. Layer 2 further includes an opposing surface 2B. In general, to form the selectively bonded multiple layer substrate 100, layer 1, layer 2, or both layers 1 and 2 are treated to define regions of weak bonding 5 and strong bonding 6, and subsequently bonded, wherein the regions of weak bonding 5 are in a condition to allow processing of a useful device or structure. [0135] Generally, layers 1 and 2 are compatible. That is, the layers 1 and 2 constitute compatible thermal, mechanical, and/or crystalline properties. In certain preferred embodiments, layers 1 and 2 are the same materials. Of course, different materials may be employed, but preferably selected for compatibility.

[0136] One or more regions of layer 1 are defined to serve as the substrate region within or upon which one or more structures, such as microelectronics may be formed. These regions may be of any desired pattern, as described further herein. The selected regions of layer 1 may then be treated to minimize bonding, forming the weak bond regions 5.

Alternatively, corresponding regions of layer 2 may be treated (in conjunction with treatment of layer 1, or instead of treatment to layer 1) to minimize bonding. Further alternatives include treating layer 1 and/or layer 2 in regions other than those selected to form the structures, so as to enhance the bond strength at the strong bond regions 6.

[0137] After treatment of layer 1 and/or layer 2, the layers may be aligned and bonded.

The bonding may be by any suitable method, as described further herein. Additionally, the alignment of the layers may be mechanical, optical, or a combination thereof. It should be understood that the alignment at this stage may not, be critical, insomuch as there are generally no structures formed on layer 1. However, if both layers 1 and 2 are treated, alignment may be required to minimize variation from the selected substrate regions. [0138] The multiple layer substrate 100 may be provided to a user for processing of any desired structure in or upon layer 1. Accordingly, the multiple layer substrate 100 is formed such that the user may process any structure or device using conventional fabrication techniques, or other techniques that become known as the various related technologies develop. Certain fabrication techniques subject the substrate to extreme conditions, such as high temperatures, pressures, harsh chemicals, or a combination thereof. Thus, the multiple layer substrate 100 is preferably formed so as to withstand these conditions. [0139] Useful structures or devices may be formed in or upon regions 3, which partially or substantially overlap weak bond regions 5. Accordingly, regions 4, which partially or substantially overlap strong bond regions 6, generally do not have structures therein or thereon. After a user has formed useful devices within or upon layer 1 of the multiple layer substrate 100, layer 1 may subsequently be debonded. The debondingmay be by any known technique, such as peeling, without the need to directly subject the useful devices to detrimental delamination techniques. Since useful devices are not generally formed in or on regions 4, these regions may be subjected to debonding processing, such as ion implantation, without detriment to the structures formed in or on regions 3.

[0140] To form weak bond regions 5, surfaces IA, 2A₅ or both may be treated at the locale of weak bond regions 5 to form substantially no bonding or weak bonding.

Alternatively, the weak bond regions 5 may be left untreated, whereby the strong bond region 6 is treated to induce strong bonding. Region 4 partially or substantially overlaps strong bond region 6. To form strong bond region 4, surfaces IA, 2A, or both may be treated at the locale of strong bond region 6. Alternatively, the strong bond region 6 may be left untreated, whereby the weak bond region 5 is treated to induce weak bonding. Further, both regions 5 30849

and 6 may be treated by different treatment techniques, wherein the treatments may differ qualitatively or quantitatively.

[0141] After treatment of one or both of the groups of weak bond regions 5 and strong bond regions 6, layers 1 and 2 are bonded together to form a substantially integral multiple layer substrate 100. Thus, as formed, multiple layer substrate 100 may be subjected to harsh environments by an end user, e.g., to form structures or devices therein or thereon, particularly in or on regions 3 of layer 1.

[0142] For purposes of this specification, the phrase "weak bonding" or "weak bond" generally refers to a bond between layers or portions of layers that may be readily overcome, for example by debonding techniques such as peeling, other mechanical separation, heat, light, pressure, or combinations comprising at least one of the foregoing debonding techniques. These debonding techniques minimally defect or detriment the layers 1 and 2, particularly in the vicinity of weak bond regions 5.

[0143] The treatment of one or both of the groups of weak bond regions 5 and strong bond regions 6 may be effectuated by a variety of methods. The important aspect of the treatment is that weak bond regions 5 are more readily debonded (in a subsequent debonding step as described further herein) than the strong bond regions 6. This minimizes or prevents damage to the regions 3, which may include useful structures thereon, during debonding. Further, the inclusion of strong bond regions 6 enhances mechanical integrity of the multiple layer substrate 100 especially during structure processing. Accordingly, subsequent processing of the layer 1, when removed with useful structures therein or thereon, is minimized or eliminated.

[0144] The ratio of the bond strengths of the strong bond regions to the weak bond regions (SB/WB) in general is greater than 1. Depending on the particular configuration of the strong bond regions and the weak bond regions, and the relative area sizes of the strong bond regions and the weak bond regions, the value of SB/WB may approach infinity. That is, if the strong bond areas are sufficient in size and strength to maintain mechanical and thermal stability during processing, the bond strength of the weak bond areas may approach zero. However, the ratio SB/WB may vary considerably, since strong bonds strengths (in typical silicon and silicon derivative, e.g., SiO₂, wafers) may vary from about 500 millijoules per squared meter (mj/m²) to over 5000 mj/m² as is taught in the art (see, e.g., Q.Y. Tong, U. Goesle, Semiconductor Wafer Bonding, Science and Technology, pp. 104-118, John Wiley and Sons, New York, NY 1999, which is incorporated herein by reference). However, the weak bond strengths may vary even more considerably, depending on the materials, the intended useful structure (if known), the bonding and debonding techniques selected, the area of strong bonding compared to the area of weak bonding, the strong bond and weak bond configuration or pattern on the wafer, and the like. For example, where ion implantation is used as a step to debond the layers, a useful weak bond area bond strength may be comparable to the bond strength of the strong bond areas after ion implantation and/or related evolution of microbubbles at the implanted regions. Accordingly, the ratio of bond strengths SBAVB is generally greater than 1, and preferably greater than 2, 5, 10, or higher, depending on the selected debonding techniques and possibly the choice of the useful structures or devices to be formed in the weak bond regions.

[0145] The particular type of treatment of one or both of the groups of weak bond regions 5 and strong bond regions 6 undertaken generally depends on the materials selected. Further, the selection of the bonding technique of layers 1 and 2 may depend, at least in part, on the selected treatment methodology. Additionally, subsequent debonding may depend on factors such as the treatment technique, the bonding method, the materials, the type or existence of useful structures, or a combination comprising at least one of the foregoing factors. In certain embodiments, the selected combination of treatment, bonding, and subsequent debonding (i.e., which may be undertaken by an end user that forms useful structures in regions 3 or alternatively, as an intermediate component in a higher level device) obviates the need for cleavage propagation to debond layer 1 from layer 2 or mechanical thinning to remove layer 2, and preferably obviates both cleavage propagation and mechanical thinning. Accordingly, the underlying substrate may be reused with minimal or no processing, since cleavage propagation or mechanical thinning damages layer 2 according to conventional teachings, rendering it essentially useless without further substantial processing. [0146] Referring to Figures 1OA and 1OB, wherein similarly situated regions are referenced with like reference numerals, one treatment technique includes use of a slurry containing a solid component and a decomposable component on surface IA, 2A, or both IA and 2A. The solid component may be, for example, alumina, silicon oxide (SiO(x)), other solid metal or metal oxides, or other material that minimizes bonding of the layers 1 and 2. The decomposable component may be, for example, polyvinyl alcohol (PVA), or another suitable decomposable polymer. Generally, a slurry 8 is applied in weak bond region 5 at the surface IA (Figure 10A), 2A (Figure 10B), or both IA and 2A. Subsequently, layers 1 and/or 2 may be heated, preferably in an inert environment, to decompose the polymer. Accordingly, porous structures (comprised of the solid component of the slurry) remain at the weak bond regions 5, and upon bonding, layers 1 and 2 do not bond at the weak bond regions 5. [0147] Referring to Figures 1 IA and 1 IB, another treatment technique may rely on variation in surface roughness between the weak bond regions 5 and strong bond regions 6. The surface roughness may be modified at surface IA (Figure HA), surface 2A (Figure 1 IB), or both surfaces IA and 2A. In general, the weak bond regions 5 have higher surface roughness 7 (Figures HA and HB) than the strong bond regions 6. hi semiconductor materials, for example the weak bond regions 5 may have a surface roughness greater than about 0.5 nanometer (nm), and the strong bond regions 4 may have a lower surface roughness, generally less than about 0.5 nm. In another example, the weak bond regions 5 may have a surface roughness greater than about 1 nm, and the strong bond regions 4 may have a lower surface roughness, generally less than about 1 nm. In a further example, the weak bond regions 5 may have a surface roughness greater than about 5 nm, and the strong bond regions 4 may have a lower surface roughness, generally less than about 5 nm. Surface roughness can be modified by etching (e.g., in KOH or HF solutions) or deposition processes (e.g., low pressure chemical vapor deposition ("LPCVD") or plasma enhanced chemical vapor deposition ('TECVD")). The bonding strength associated with surface roughness is more fully described in, for example, Gui et al., "Selective Wafer Bonding by Surface

Roughness Control", Journal of The Electrochemical Society, 148 (4) G225-G228 (2001), which is incorporated by reference herein.

[0148] In a similar manner (wherein similarly situated regions are referenced with similar reference numbers as in Figures 1 IA and 1 IB), a porous region 7 may be formed at the weak bond regions 5, and the strong bond regions 6 may remain untreated. Thus, layer 1 minimally bonds to layer 2 at locale of the weak bond regions 5 due to the porous nature thereof. The porosity may be modified at surface IA (Figure HA), surface 2A (Figure HB), or bom surfaces IA and 2A. In general, the weak bond regions 5 have higher porosities at the porous regions 7 (Figures 1 IA and 1 IB) than the strong bond regions 6. [0149] Another treatment technique may rely on selective etching of the weak bond regions 5 (at surfaces IA (Figure HA), 2A (Figure 11B), or both IA and 2A), followed by deposition of a photoresist or other carbon containing material 7 (e.g., including a polymeric based decomposable material) in the etched regions. Upon bonding of layers 1 and 2, which is preferably at a temperature sufficient to decompose the carrier material, the weak bond regions 5 include a porous carbon material 7 therein, thus the bond between layers 1 and 2 at the weak bond regions 5 is very weak as compared to the bond between layers 1 and 2 at the strong bond region 6. One skilled in the art will recognize that depending on the circumstances, a decomposing material will be selected that will not out-gas, foul, or otherwise contaminate the substrate layers 1 or 2, or any useful structure to be formed in or upon regions 3.

[0150] A further treatment technique may employ irradiation to attain strong bond regions 6 and/or weak bond regions 5. In this technique, layers 1 and/or 2 are irradiated with neutrons, ions, particle beams, or a combination thereof to achieve strong and/or weak bonding, as needed. For example, particles such as He⁺, H⁺, or other suitable ions or particles, electromagnetic energy, or laser beams may be irradiated at the strong bond regions 6 (at surfaces IA (Figure 90), 2A (Figure 14B), or both IA and 2A). It should be understood that this method of irradiation differs from ion implantation for the purpose of delaminating a layer, generally in that the doses and/or implantation energies are much less (e.g., on the order of 1/100* to 1/1000* of the dosage used for delaminating). [0151] Referring to Figures 13A and 13B, a still further treatment technique involves etching the surface of the weak bond regions 5. During this etching step, pillars 9 are defined in the weak bond regions 5 on surfaces IA (Figure 13A), 2A (Figure 13B), or both IA and 2A. The pillars may be defined by selective etching, leaving the pillars behind. The shape of the pillars may be triangular, pyramid shaped, rectangular, hemispherical, or other suitable shape. Alternatively, the pillars may be grown or deposited in the etched region. Since there are less bonding sites for the material to bond, the overall bond strength at the weak bond region 5 is much weaker then the bonding at the strong bond regions 6. [0152] Yet another treatment technique involves inclusion of a void area 10 (Figures 15A and 15B), e.g., formed by etching, machining, or both (depending on the materials used) at the weak bond regions 5 in layer 1 (Figure 15A), 2 (Figure 15B). Accordingly, when the first US2006/030849

layer 1 is bonded to the second layer 2, the void areas 10 will minimize the bonding, as compared to the strong bond regions 6, which will facilitate subsequent debonding. [0153] Referring again to Figures 1OA and 1OB, another treatment technique involves use of one or more metal regions 8 at the weak bond regions 5 of surface IA (Figure 10A), 2A (Figure 10B), or both IA and 2 A. For example, metals including but not limited to Cu, Au, Pt, or any combination or alloy thereof may be deposited on the weak bond regions 5. Upon bonding of layers 1 and 2, the weak bond regions 5 will be weakly bonded. The strong bond regions may remain untreated (wherein the bond strength difference provides the requisite strong bond to weak bond ratio with respect to weak bond layers 5 and strong bond regions 6), or may be treated as described above or below to promote strong adhesion.

[0154] A further treatment technique involves use of one or more adhesion promoters 11 at the strong bond regions 6 on surfaces IA (Figure 90), 2A (Figure 14B), or both IA and 2A. Suitable adhesion promoters include, but are not limited to, TiO(x), tantalum oxide, or other adhesion promoter. Alternatively, adhesion promoter may be used on substantially all of the surface IA and/or 2 A, wherein a metal material is be placed between the adhesion promoter and the surface IA or 2A (depending on the locale of the adhesion promoter) at the weak bond regions 5. Upon bonding, therefore, the metal material will prevent strong bonding a the weak bond regions 5, whereas the adhesion promoter remaining at the strong bond regions 6 promotes strong bonding. [0155] Yet another treatment technique involves providing varying regions of hydriphobicity and/or hydrophillicity. For example, hydrophilic regions are particularly useful for strong bond regions 6, since materials such as silicon may bond spontaneously at room temperature. Hydrophobic and hydrophilic bonding techniques are known, both at room temperature and at elevated temperatures, for example, as described in Q. Y. Tong, U. Goesle, Semiconductor Wafer Bonding, Science and Technology, pp.49-135, John Wiley and Sons, New York, NY 1999, which is incorporated by reference herein. [0156] A still further treatment technique involves one or more exfoliation layers that are selectively irradiated. For example, one or more exfoliation layers may be placed on the surface IA and/or 2A. Without irradiation, the exfoliation layer behaves as an adhesive. Upon exposure to irradiation, such as ultraviolet irradiation, in the weak bond regions 5, the adhesive characteristics are minimized. The useful structures may be formed in or upon the weak bond regions 5, and a subsequent ultraviolet irradiation step, or other debonding technique, may be used to separate the layers 1 and 2 at the strong bond regions 6. [0157] Referring to Figures 12A and 12B, an additional treatment technique includes an implanting ions 12 (Figures 12A and 12B) to allow formation of a plurality of microbubbles 13 in layer 1 (Figure 12A), layer 2 (Figure 12B), or both layers 1 and 2 in the weak regions 3, upon thermal treatment Therefore, when layers 1 and 2 are bonded, the weak bond regions 5 will bond less than the strong bond regions 6, such that subsequent debonding of layers 1 and 2 at the weak bond regions 5 is facilitated.

[0158] Another treatment technique includes an ion implantation step followed by an etching step. In one embodiment, this technique is carried out with ion implantation through substantially all of the surface IB. Subsequently, the weak bond regions 5 may be selectively etched. This method is described with reference to damage selective etching to remove defects in Simpson et al., "Implantation Induced Selective Chemical Etching of Indium Phosphide", Electrochemical and Solid-State Letters, 4(3) G26-G27, which is herein incorporated by reference.

[0159] A still further treatment technique realizes one or more layers selectively positioned at weak bond regions 5 and/or strong bond regions 6 having radiation absorbing and/or reflective characteristics, which may be based on narrow or broad wavelength ranges. For example, one or more layers selectively positioned at strong bond regions 6 may have adhesive characteristics upon exposure to certain radiation wavelengths, such that the layer absorbs the radiation and bonds layers 1 and 2 at strong bond regions 6. [0160] One of skill in the art will recognize that additional treatment technique may be employed, as well as combination comprising at least one of the foregoing treatment techniques. The key feature of any treatment employed, however, is the ability to form one or more region of weak bonding and one or more regions of strong bonding, providing SB/WB bond strength ratio greater than 1.

[0161] The geometry of the weak bond regions 5 and the strong bond regions 6 at the interface of layers 1 and 2 may vary depending on factors including, but not limited to, the type of useful structures formed on or in regions 3, the type of debonding/ bonding selected, the treatment technique selected, and other factors. Referring to Figures 16A-16G, the multiple layer substrate 100 may have weak bond and strong bond regions which may be concentric (Figures 16A, 16C, 16E ), striped (Figure 16B), radiating (Figure 16D), checkered (Figure 16G), a combination of checkered and annular (Figure 16F), or any combination thereof. Of course, one of skill in the art will appreciate that any geometry may be selected. Furthermore, the ratio of the areas of weak bonding as compared to areas of strong bonding may vary. In general, the ratio provides sufficient bonding (i.e., at the strong bond regions 6) so as not to comprise the integrity of the multiple layer structure 100, especially during structure processing. Preferably, the ratio also maximizes useful regions (Le., weak bond region 5) for structure processing.

[0162] After treatment of one or both of the surfaces IA and 2A in substantially the locale of weak bond regions 5 and/or strong bond regions 6 as described above, layers 1 and 2 are bonded together to form a substantially integral multiple layer substrate 100. Layers 1 and 2 may be bonded together by one of a variety of techniques and/or physical phenomenon, including but not limited to, eutectic, fusion, anodic, vacuum, Van der Waals, chemical adhesion, hydrophobic phenomenon, hydrophilic phenomenon , hydrogen bonding, coulombic forces, capillary forces, very short-ranged forces, or a combination comprising at least one of the foregoing bonding techniques and/or physical phenomenon. Of course, it will be apparent to one of skill in the art that the bonding technique and/or physical phenomenon may depend in part on the one or more treatments techniques employed, the type or existence of useful structures formed thereon or therein, anticipated debonding method, or other factors.

[0163] Alternatively, a buried oxide layer may be formed at the bottom surface of the device layer. The oxide layer may be formed prior to selective bonding of the device layer to the bulk substrate. Further, the oxide layer may be formed by oxygen implanting to a desired buried oxide layer depth.

[0164] There are various techniques for forming an oxide layer on the multiple layer substrate. A first technique consists of forming the buried SiO₂ layer in a silicon substrate by implanting oxygen at high dose followed by annealing at a temperature greater than 1300° C. Through ion implantation, desired thicknesses of buried SiO₂ layer can be formed. [0165] An alternate technique for forming a buried oxide layer consists of forming a thin SiO₂ film on a surface of the multiple layer substrate, then bonding the substrate to a second silicon substrate by means of the SiO₂ film. Known mechanical grinding and polishing processes are then used to form a desired thickness silicon layer above the buried silicon oxide layer. The silicon oxide layer on the multiple layer substrate is formed by successively oxidizing the surface followed by etching the oxide layer formed in order to obtain the desired thickness.

[0166] Another technique for forming a buried oxide layer consists of forming, by oxidation, a thin silicon oxide layer on a first multiple layer substrate, then implanting H⁺ ions in the first multiple layer substrate in order to form a cavity plane under the thin silicon oxide layer. Subsequently, by means of the thin silicon oxide layer, this first body is bonded to a second multiple layer substrate and then the entire assembly is subjected to thermal activation in order to transform the cavity plane into a cleaving plane. This makes it possible to recover a usable SOI substrate.

[0167] Multiple layer substrate 100 thus may be provided to an end user (with or without a buried oxide layer). Alternatively, certain patterns of conductors may be formed integral with the multiple layer substrate. The end user may subsequently form one or more useful structures (not shown) in or upon regions 3, which substantially or partially overlap weak bond regions 5 at the interface of surfaces IA and 2A. The useful structures may include one or more active or passive elements, devices, implements, tools, channels, other useful structures, or any combination comprising at least one of the foregoing useful structures. For instance, the useful structure may include an integrated circuit or a solar cell. Of course, one of skill in the art will appreciate that various microtechnology and nanotechnology based device may be formed.

[0168] For instance, active devices may be formed on the multiple layer SOI wafer or substrate. These active devices are formed in the monocrystalline silicon active layer on the buried oxide film of the SOI substrate. The thickness of the silicon active layer is dependent on the purpose of the active devices formed therein. If the SOI elements are CMOS elements operating at high speed and low power consumption, the thickness of the active layer is about 50 to 100 nm. If the SOI elements are high breakdown voltage elements, the thickness of the active layer may be several micrometers. An example of an active device is a protective diode. A protective diode is a semiconductor element provided to a semiconductor device, to guide an over current from a connection pin to a substrate and to the outside of the semiconductor device, to thereby protecting an internal circuit of the semiconductor device. [0169] It will be apparent to one skilled in the art that other active devices may be fabricated with selective doping and masking of active regions of the either the monocrystalline silicon substrate or SOI substrate. These active devices may include, but are not limited to, bipolar junction transistors, metal-oxide-semiconductor transistors, field effect transistors, diodes, insulated gate bipolar transistors, and the like.

[0170] Another active device which may be fabricated on the multiple layer substrate are MEMS devices. Generally, MEMS devices have comprise electrodes and actuatable elements disposed opposite electrodes fabricated on a substrate. The actuatable elements transfer controls from the electrodes to provide electrical control over machine structures. One technique for manufacturing MEMS devices is by bulk micromachining the substrate using deep etch processing, which is considered a subtractive fabrication technique because it involves etching away material from a single substrate layer to form the MEMS structure. The substrate layer can be relatively thick, on the order of tens of microns, and the sophistication of this process allows for the micromachining of different structures in the substrate such as cantilevers, bridges, trenches, cavities, nozzles and membranes.

[0171] Another technique for manufacturing MEMS devices on the multiple layer substrate is by surface micromachining techniques. It is considered an additive process because alternate structural layers and sacrificial spacer layers are "built-up" to construct the MEMS structure with the necessary mechanical and electrical characteristics. Polycrystalline silicon (polysilicon) is the most commonly used structural material and silicon oxide glass is the most commonly used sacrificial material. In traditional micromachining processes, these layers are formed in polysilicon/oxide pairs on a silicon substrate isolated with a layer of silicon nitride. The layers are patterned using photolithography technology to form intricate structures such as motors, gears, mirrors, and beams. As the layers are built up, cuts are made through the oxide layers and filled with polysilicon to anchor the upper structural layers to the substrate or to the underlying structural layer.

[0172] After one or more structures have been formed on one or more selected regions 3 of layer I, layer 1 may be debonded by a variety of methods. It will be appreciated that since the structures are formed in or upon the regions 4, which partially or substantially overlap weak bond regions 5. debonding of layer 1 can take place while minimizing or eliminating typical detriments to the structures associated with debonding, such as structural defects or deformations.

[0173] Debonding may be accomplished by a variety of known techniques. In general, debonding may depend, at least in part, on the treatment technique, bonding technique, materials, type or existence of useful structures, or other factors.

[0174] Referring in general to Figures 17A-20C, debonding techniques may be based on implantation of ions or particles to form microbubbles at a reference depth, generally equivalent to thickness of the layer 1. The ions or particles may be derived from oxygen, hydrogen, helium, or other particles 14. The impanation may be followed by exposure to strong electromagnetic radiation, heat, light (e.g., infrared or ultraviolet), pressure, or a combination comprising at least one of the foregoing, to cause the particles or ions to form the microbubbles 15, and ultimately to expand and delaminate the layers 1 and 2. The implantation and optionally heat, light, and/or pressure may also be followed by a mechanical separation step (Figures 17C, 18C, 19C, and 20C), for example, in a direction normal to the plane of the layers 1 and 2, parallel to the plane of the layers 1 and 2, at another angle with to the plane of the layers 1 and 2, in a peeling direction (indicated by broken lines in Figure 17C, 26, 29, 32), or a combination thereof. Ion implantation for separation of thin layers is described in further detail, for example, in Cheung, et al. United States Patent No. 6,027,988 entitled "Method Of Separating Films From Bulk Substrates By Plasma Immersion Ion Implantation", which is incorporated by reference herein.

[0175] Referring particularly to Figures 17A-17C and 18A-18C, the interface between layers 1 and 2 may be implanted selectively, particularly to form microbubbles 17 at the strong bond regions 6. In this manner, implantation of particles 16 at regions 3 (having one or more useful structures therein or thereon) is minimized, thus reducing the likelihood of repairable or irreparable damage that may occur to one or more useful structures in regions 3. Selective implantation may be carried out by selective ion beam scanning of the strong bond regions 4 (Figures 18A-18C) or masking of the regions 3 (Figures 17A-17C). Selective ion beam scanning refers to mechanical manipulation of the structure 100 and/or a device used to direct ions or particles to be implanted. As is known to those skilled in the art, various apparatus and techniques may be employed to carry out selective scanning, including but not limited to focused ion beam and electromagnetic beams. Further, various masking materials and technique are also well known in the art. [0176] Referring to Figures 19A-19C, the implantation may be effectuated substantially across the entire the surface IB or 2B. Implantation is at suitable levels depending on the target and implanted materials and desired depth of implantation. Therefore, where layer 2 is much thicker than layer 1, it may not be practical to implant through surface 2B; however, if layer 2 is a suitable implantation thickness (e.g., within feasible implantation energies), it may be desirable to implant through the surface 2B. This minimizes or eliminates possibility of repairable or irreparable damage that may occur to one or more useful structures in regions 3.

[0177] In one embodiment, and referring to Figures 20A-20Cin conjunction with Figure 16E, strong bond regions 6 are formed at the outer periphery of the interface between layers 1 and 2. Accordingly, to debond layer 1 form layer 2, ions 18 may be implanted, for example, through region 4 to form microbubbles at the interface of layers 1 and 2. Preferably, selective scanning is used, wherein the structure 100 may be rotated (indicated by arrow 20), a scanning device 21 may be rotated (indicated by arrow 22), or a combination thereof, hi this embodiment, a further advantage is the flexibility afforded the end user in selecting useful structures for formation therein or thereon. The dimensions of the strong bond region 6 (i.e.₅ the width) are suitable to maintain mechanical and thermal integrity of the multiple layer substrate 100. Preferably, the dimension of the strong bond region 6 is minimized, thus maximizing the area of weak bond region 5 for structure processing. For example, strong bond region 6 may be about one (1) micron on an eight (8) inch wafer. [0178] Further, debonding of layer 1 from layer 2 may be initiated by other conventional methods, such as etching (parallel to surface), for example, to form an etch through strong bond regions 6. In such embodiments, the treatment technique is particularly compatible, for example wherein the strong bond region 6 is treated with an oxide layer that has a much higher etch selectivity that the bulk material (i.e., layers 1 and 2). The weak bond regions 5 preferably do not require etching to debond layer 1 from layer 2 at the locale of weak bond regions 5, since the selected treatment, or lack thereof, prevented bonding in the step of bonding layer 1 to layer 2.

[0179] Alternatively, cleavage propagation may be used to initiate debonding of layer 1 from layer 2. Again, the debonding preferably is only required at the locale of the strong bond regions 6, since the bond at the weak bond regions 5 is limited. Further, debonding may be initiated by etching (normal to surface), as is conventionally known, preferably limited to the locales of regions 4 (i.e., partially or substantially overlapping the strong bond regions 6). [0180] In another embodiment, and referring now to Figure 21, a method of debonding is shown with reference to a sectional views of a multiple layered substrate. The method includes providing a multiple layered substrate 100 shown in step 2120. One or more useful structures are processed (not shown) in the WB regions 5 of device layer 4 selectively bonded to substrate 2. Material is etched away at a portion 12 the SB regions 6 as shown in step 2122, preferably at a tapered angle (e.g., 45 degrees), leaving a portion 14 of the thickness of the SB regions 6 attached to the substrate 2. The device layer 4, preferably only the etched SB region 6, is subjected to low energy ion implantation. The device layer portions at the WB region are peeled or otherwise readily removing as shown in step 2124. Note that while two sections of device layer 4 at the WB layer are shown as being removed, it is understood that this may be used to facilitate release of one device layer portion. The tapered edge of the WB region mechanically facilitates removal. Beneficially, much lower ion implant energy may be used as compared to implant energy required to penetrate the original device layer thickness.

[0181] The separation or debonding may also be multi-step, for example, chemical etching parallel to the layers followed by knife edge separation. The separation step or steps may include mechanical separation techniques such as peeling, cleavage propagation; knife edge separation, water jet separation, ultrasound separation or other suitable mechanical separation techniques. Further, the separation step or steps may be by chemical techniques, such as chemical etching parallel to the layers; chemical etching normal to the layers; or other suitable chemical techniques. Still further, the separation step or steps may include ion implantation and expansion to cause layer separation. [0182] An important benefit of the instant method and resulting multiple layer substrate, or thin film derived from the multiple layer substrate is that the structures are formed in or upon the regions 3, which partially or substantially overlap the weak bond regions 5. This substantially minimizes or eliminates likelihood of damage to the useful structures when the layer 1 is removed from layer 2. The debonding step generally requires intrusion (e.g., with ion implantation), force application, or other techniques required to debond layers 1 and 2. Since, in certain embodiments, the structures are in or upon regions 3 that do not need local intrusion, force application, or other process steps that may damage, reparably or irreparable, the structures, the layer 1 may be removed, and structures derived therefrom, without subsequent processing to repair the structures. The regions 4 partially or substantially overlapping the strong bond regions 6 do generally not have structures thereon, therefore these regions 4 may be subjected to intrusion or force without damage to the structures. [0183] The layer 1 may be removed as a self supported film or a supported film. For example, handles are commonly employed for attachment to layer 1 such that layer 1 may be removed from layer 2, and remain supported by the handle. Generally, the handle may be used to subsequently place the film or a portion thereof (e.g., having one or more useful structures) on an intended substrate, another processed film, or alternatively remain on the handle.

[0184] One benefit of the instant method is that the material constituting layer 2 is may be reused and recycled. A single wafer may be used, for example, to derive layer 1 by any known method. The derived layer 1 may be selectively bonded to the remaining portion (layer 2) as described above. When the thin film is debonded, the process is repeated, using the remaining portion of layer 2 to obtain a thin film to be used as the next layer 1. This may be repeated until it no longer becomes feasible or practical to use the remaining portion of layer 2 to derive a thin film for layer 1. [0185] In one example of a method to form a device layer that avoids delaminating from the substrate, device regions of the device layer are weakly bonded to the substrate. Further, patterns of weak bonding are created between the devices, such that upon separation of the device layer from the substrate, several devices are attached to one another with device layer material, for example. The remainder of the interface between the substrate and the device layer is strongly bonded. [0186] Referring to Figures 22A-22B, a structure 10 includes a device layer 4 supported on a substrate 2, with an interface 6 therebetween. Strong bond regions 32 are formed on the substrate 2. Further, weak bond regions 28 and 29 are provided on the substrate 2. In general, the device layer 4 includes device regions 21 at the locales of the weak bond regions 28. Further, device layer 4 includes connecting regions 38 at the locales of weak bond regions 29. Devices (not shown) are formed in or upon the device layer 4 at the device regions 21. Upon processing for separation primarily or entirely at the locales of strong bonding 32 (e.g., by removal of material at the locales of strong bonding in the device layer 4 and the release layer 6 as shown in Figure 22C), where device regions 21 and connecting regions 38 are not present, the device layer 4 including a group of device regions 21 may be removed or peeled with the connecting regions 38 as shown in Figure 22D. The device regions 21 may then be easily separated from one another and may be used as is or stacked, for example, as shown in Figure 22E.

[0187] Since regions between the device regions 21 are strongly bonded to the substrate 2, a large amount of bonding force will exist. Therefore, during harsh conditions, e.g., temperatures, pressures, exposure to etchants, etc., the likelihood of delaminating of the device layer 4 from the substrate 2 is minimized or eliminated. [0188] Additionally, another area where advantages of the present group of device regions and method of forming the groups exist is in alignment of device regions for forming vertically integrated devices. Since the device regions 21 are removed with the interconnection regions 38 therebetween, rather than a portion of the layer that is typical in wafer scale processing, a physical space remains between the devices. Thus, the devices layers 4 may be aligned as in other systems described herein (optically, with resonant enhancements, mechanically at the layer interfaces), and also mechanically (typically a course alignment step) from the edge of the stack or with a spindle-type structure through the center of the device regions. The stack of device layers 4 including device regions 21 with the interconnection regions 38 therebetween may then be cut, for example, to form a vertically integrated device shown in Figure 22E. [0189] Referring now to Figures 23 A-23B, another embodiment of a method and structure for forming device regions with enhanced features is shown, wherein the group of devices is further supported with a peripheral connector portion 34. Other processing steps are similar to those shown in Figures 22A-22D.

[0190] Referring to Figure 24A-24E, another processing method is provided. Figure 24A shows a top view of a further embodiment of the present invention for enhanced processing. In this example, device regions 21 are left behind as well as periphery regions 34 and connector regions 38. Figure 24B shows that areas where the device regions 21, periphery regions 34 and connector regions 38 are not present are etched or otherwise removed. Figure 24C shows that on the edges of the device regions, periphery regions and/or connector regions, strong bond regions may be formed or grown. For example, strong bond regions may be epitaxially grown as single crystal silicon between the device layer and the release layer. Further, strong bond regions may be formed or connected at the outer edge of the structure, as shown in Figure 24D. In this manner, the device regions remain strongly supported during processing. To separate the device layer, only the strong bond regions need to be subject to harsh separation processing steps. [0191]

[0192] Accordingly, layered structure generally includes a first layer suitable for having a useful element formed therein or thereon selectively attached or bonded to a second layer, e.g., a substrate. A method to form a layered structure generally comprises releasably adhering a first layer to a second layer. The layered structure may serve as a starting wafer for production of various devices including semiconductor devices, thin film devices, or vertically integrated devices. Processing techniques including, inter alia, alignment, bonding and interconnecting are detailed herein. [0193] Separating the layers formed according to the various embodiments herein may include one or more of the following processes: mechanical separation; chemical etching parallel to layers; chemical etching normal to layers; cleavage propagation; ion implantation (e.g., as described above with respect to the release layer including regions of strong bonding and regions of weak bonding); water jet; and ultrasound. [0194] The material for the layers used herein, as the device layer and the substrate layer, may be the same or different materials, and may include materials including, but not limited to, plastic (e.g., polycarbonate), metal, semiconductor, insulator, monocrystalline, amorphous, noncrystalline, biological (e.g., DNA based films) or a combination comprising at least one of the foregoing types of materials. For example, specific types of materials include silicon (e.g., monocrystalline, polycrystalline, noncrystalline, polysilicon, and derivatives such as Si3N4, SiC, SiO2), GaAs, InP, CdSe, CdTe, SiGe, GaAsP, GaN, SiC, GaAlAs, InAs, AlGaSb, InGaAs, ZnS, AlN, TiN, other group IHA-VA materials, group IIB materials, group VIA materials, sapphire, quartz (crystal or glass), diamond, silica and/or silicate based material, or any combination comprising at least one of the foregoing materials. Of course, processing of other types of materials may benefit from the process described herein to provide multiple layer substrates having a device layer and substrate of desired composition. Preferred materials which are particularly suitable for the herein described methods include semiconductor material (e.g., silicon) as the device layer, and semiconductor material (e.g., silicon) as the substrate layer, other combinations include, but are not limited to; semiconductor (the device layer) or glass (the substrate layer); semiconductor (the device layer) on silicon carbide (the substrate layer) semiconductor (the device layer) on sapphire (the substrate layer); GaN (the device layer) on sapphire (the substrate layer); GaN (the device layer) on glass (the substrate layer); GaN (the device layer) on silicon carbide (the substrate layer); plastic (the device layer) on plastic (the substrate layer), wherein the device layer and the substrate layer may be the same or different plastics; and plastic (the device layer) on glass (the substrate layer).

[0195] The device layer and the substrate layer may be derived from various sources, including wafers or fluid material deposited to form films and/or substrate structures. Where the starting material is in the form of a wafer, any conventional process may be used to derive the device layer and/or the substrate layer. For example, the substrate layer may consist of a wafer, and the device layer may comprise a portion of the same or different wafer. The portion of the wafer constituting the device layer may be derived from mechanical thinning (e.g., mechanical grinding, cutting, polishing; chemical-mechanical polishing; polish-stop; or combinations including at least one of the foregoing), cleavage propagation, ion implantation followed by mechanical separation (e.g., cleavage propagation, normal to the plane of the layers, parallel to the plane of the layers, in a peeling direction, or a combination thereof), ion implantation followed by heat, light, and/or pressure induced layer splitting), chemical etching, or the like. Further, either or both the device layer and the substrate layer may be deposited or grown, for example by chemical vapor deposition, epitaxial growth methods, or the like.

[0196] In additional embodiments, and referring now to Figure 25, a process is shown for forming single crystalline silicon wafers, for example, out of a cylindrical boule. Grooves are etched in one or more cleave planes. These cleave planes preferably correspond with natural cleave plane within crystalline structure, such that upon exposure to a suitable shock wave, cleavage propagation occurs. These grooves need not be extremely deep. In certain embodiments, these grooves may be deep enough such that shock waves are created by mechanical cracking, whereby propagation is facilitated along the cleave plane. In other embodiments, the shock wave may be created by ultrasonic waves, water jets, other sudden bursts of particles providing a shock wave through the cleave plane, shape memory alloy material that expands upon application of a burst of electrical pulse to heat the material to induce a shape change. In other embodiments, these etched grooves are filled with an expandable material that rapidly expands upon sudden bursts of radiation that is absorbed. For example, materials that absorb light (e.g., photo-absorbers) at certain wavelengths will expand when pulsed with that light. Thus, these materials, upon expansion, will expose the cleave plane to a shock wave thereby propagating at the cleave plane, thereby releasing a layer. This layer may be used in various embodiments herein, e.g., bonded to a support via a release layer to facilitate separation after processing of one or more useful devices. Alternatively, this layer may be used in conventional wafer processing techniques. [0197] Referring now to Figure 26, a method is shown for growing a single crystal silicon layer. A method is shown whereby the chip seeds used as starting materials are derived from a substrate formed of highly strained material (steps A-C). In step A, a porous or strained layer is provided. Regions are oxidized (step B). Upon the non-oxidized regions, single crystalline silicon flakes may be grown, shown in step C. Single crystalline silicon layers may then be grown on a substrate formed of highly strained material or porous material, using the material from step C. From the end result, (step E), if the substrate is insulating, the an SOI structure is provided. If the substrate is non-porous and non-strained, single crystal Si on another substrate is provided, where the other substrate can be amorphous Si, metal, other semiconductor, or the like.. If substrate is porous or a strained layer, the single crystal layer may be peeled or otherwise readily removed. [0198] Having thus described in detail various methods of formation of a selectively bonded multiple layer substrates in, formation of vertically integrated devices such as three- dimensional integrated circuits now will be described using the selectively bonded multiple layer substrate or the multiple layer substrate including a release layer. [0199] Referring to Figure 27, an isometric schematic of a stack of 1...N wafers and a die cut therefrom is shown. For clarity, coordinates are provided. The die and the stack of wafers generally have top and bottom surfaces, and interlayers, extending in the x and y coordinate directions, generally referred to herein as planar directions. Note that the planar directions include any direction extending on the surfaces or interlayers. The several layers are stacked in the z direction, generally referred to herein as vertically or in three dimensions. After die cutting, the die has, in addition to the interlayers and top and bottom surfaces, four edge surfaces extending generally in the z direction, for example, when rectangular shaped dies are cut

[0200] Referring now to Figure 28, a general method of forming a vertically integrated device is shown. A handler temporarily secures a first layer A and stacks and bonds layer A to a substrate. The same or a different handler temporarily secures a second layer B and aligns, stacks and bonds layer B to layer A. The process continues until a desired number of layers is provided. Using conventional vertical integration methods, the number of practical layers to be stacked is limited. However, the inventor hereof has invented several techniques and systems that facilitate aligning, stacking and bonding of 10s, 100s or event 1000s of layers as described herein and in the above-mentioned related applications. [0201] Further, a method to make vertically integrated devices, for example, utilizing the release layer described above with respect to Figures 2-5 generally includes the following steps. A structure A with 3 layers IA, 2A, 3A is provided, wherein layer IA is a device layer, layer 2 A is a release layer, and layer 3 A is a support layer. In this manner, layer IA is releasable firom layer 3A. One or more useful devices is fabricated on the device layer IA. Then, device layer IA may be released from support layer 3A. A structure B with 3 layers IB, 2B, 3B is provided, wherein layer IB is a device layer, layer 2B is a release layer, and layer 3B is a support layer. In this manner, layer IB is releasable from layer 3B. One or more useful devices is fabricated on the device layer IB. Then, device layer IB may be released from support layer 3B. The device layers IA and IB may then be aligned, stacked and bonded to form a vertically integrated device. The devices layers IA and IB may interact via one or more via-interconnects, edge interconnects, channels (e.g., in a microfluidic device or for thermal dissipation), electrode interactions (e.g., in a MEMS device), or other suitable interaction.

[0202] Still further, a method to make vertically integrated devices, for example, utilizing the release layer described above with respect to Figures 2-5 generally includes the following steps, described with respect to Figures 29A-29B. Figure 29A shows a structure 2910a having three layers 2920a, 2918a, 2902a, wherein layer 2920a is a device layer, layer 2918a is a release layer, and layer 2902a is a support layer. In this manner, layer 2920a is releasable from layer 2902a. One or more useful devices 2922a is fabricated on the device layer 2920a. Further, Figure 29A also shows a structure 2910b having three layers 2920b, 2918b, 2902b, wherein layer 2920b is a device layer, layer 2918b is a release layer, and layer 2902b is a support layer. In this manner, layer 2920b is releasable from layer 2902b. One or more useful devices 2922b is fabricated on the device layer 2920b.

[0203] Referring to Figure 29B, structures 2910a and 2910b are oriented so thatthe device layers 2920a, 2920b they face one another. In certain embodiments, they will be directly aligned and bonded together to form a vertically integrated device, or a wafer stack having plural vertically integrated devices thereon. In alternative embodiments, an interface layer, e.g., including interconnection wiring features, thermal management , oxide layer, or other suitable interface.

[0204] Referring to Figure 29C, one of the support layers 2902b may be removed. Thus, the remaining structure includes a support layer 2902a, release layer 2918a, device layer 2920a, device layer 2920b and a optionally a portion of release layer 2918b. The portion of release layer 2918b may remain or may be removed in a manner known, preferably in such a way as to minimize or eliminate damage to devices formed on the device layer 2920b. In an further alternative, the remaining portion of release layer 2918b may be processed to form on oxide layer. The structure of Figure 29C may be subject to further processing, including but not limited to inclusion of additional layers on device layer 2920b (either with or without release layer 2918b remaining therebetween).

[0205] Referring to Figure 29D, in another alternative, both of the support layers 2902b and 2902a may be removed. Thus, the remaining structure includes optionally a portion of release layer 2918a, device layer 2920a, device layer 2920b and a optionally a portion of release layer 2918b. The portion of release layers 2918a, 2918b may remain or may be removed in a manner known, preferably in such a way as to minimize or eliminate damage to devices formed on the device layers 2920a, 2920b. In an further alternative, the remaining portion of release layers 2918a, 2918b may be processed to form an oxide layer. The structure of Figure 29D may be subject to further processing, including but not limited to inclusion of additional layers on device layers 2920a, 2920b (either with or without release layer 2918b remaining therebetween).

[0206] Referring now to Figure 30, a multilayer structure 3000 is provided including a device layer 3001 attached to a substrate layer 3002, with a release layer (not shown) according to various embodiments described herein. In certain embodiments, as shown, the structure 3000 is provided with strongly bonded regions 3004 and weakly bonded regions 3003, as described above, as the release layer. Although the embodiment shown has a certain strong bonding pattern, it is understood that any pattern of strong bond regions 3004 and weak bond regions 3003 may be utilized, wherein the circuitry or other useful devices are formed at the weak bond regions as described and mentioned above. Further, although the embodiment shown uses the strong bond regions and weak bond regions as a release layer, other release layers may be provided, including but not limited to one or more porous layers or a strained layer. For exemplary purposes, a region of Figure 30 is shown with a dashed circle, and alternatives of this region will be described in various exploded views to explain formation of circuit regions suitable for three-dimensional stacking. [0207] Referring to Figure 31A, a portion of a device layer 3001 is shown highlighting one example of a circuit portion having chip edge interconnect architecture suitable for three- dimensional integration. Examples of various chip edge interconnect architectures may be found, for example, in Faris U.S. Patent Nos. 5,786,629 and 6,355,976, both of which are incorporated by reference herein. A circuit portion 3120 is formed within an insulating region 3122 of the device layer of the selectively bonded layered substrate. A conductor 3124, which may be an electrical or an optical conductor, is formed, operably originating at the circuit portion and extending to the edge of the circuit package, represented by the dash- dot lines. The conductor 3124 may extend in any direction generally in the x-y plane. The bulk region 3002 serves as mechanical and thermal support during processing of the circuit portion and the conductor.

[0208] It should be appreciated that while only a single conductor 3124 is shown (in all of the embodiments hereinbefore and hereinafter), a plurality of conductors 3124 may be provided associated with each circuit portion 3120 extending in any direction generally in the x-y plane. These conductors 3124 may serve to encode each circuit portion with its own address; receive address information from external address lines; bring data and power to each circuit portion; receive data from circuit portions (memory); or other desired functionality. When multiple conductors are used, they may be independent or redundant. [0209] In one embodiment, particularly wherein several independent conductors 3124 are formed, overlapping regions are insulated as is known in semiconductor processing. [0210] The circuit portions 3120 may be the same or different, and may be formed from various transistor and diode arrangements. These devices include (within the same vertically integrated circuit) the same or different microprocessors (electrical or optical) (bipolar circuits, CMOS circuits, or any other processing circuitry), memory circuit portions such as one-device memory cells, DRAM, SRAM, Flash, signal receiving and/or transmission circuit functionality, or the like. Thus, various products may be formed with the present methods. Integrated products may include processors and memory, or processors, memory signal receiving and/or transmission circuit functionality, for a variety of wired and wireless devices. By integrating vertically (in the z direction), extremely dense chips may improve processing speed or memory storage by a factor of up to N (N representing the total number of integrated layers, and may be in the 10s, 100s or even 1000s in magnitude).

[0211] As described above, handler may be used to assist in removal of the device layer. As described above, the strong bond regions generally are subjected to steps to facilitate debonding, such as ion implantation. The device layer may then readily be removed as described herein without conventional grinding and other etch-back steps. Since the circuit portions and conductors are formed in weak bond regions, these are generally not damaged during this removal step. In one preferred embodiment, the handler used is that described in PCT Patent Application Serial PCT/US/02/31348 filed on October 2, 2002 and entitled "Device And Method For Handling Fragile Objects, And Manufacturing Method Thereof, which is incorporated by reference herein in its entirety. [0212] The device layer 3001 having plural circuit portions 3120 and edge extending conductors 3124 are then aligned and stacked as shown in Figure 3 IB and described in further detail herein. The layers 3001 are aligned and stacked such that plural circuit portions 3120 form a vertically integrated stack. Depending on the desired vertically integrated device, the circuit portions 3120 for each layer may be the same or different. In a preferred embodiment, the N layers 3001 are stacked, and subsequently all N layers 3001 are bonded in a single step. This may be accomplished, for example, by using UV or thermal cured adhesive between the layers. Note that, since interconnects 3124 are at the edges of each chip, in certain embodiments it may not be detrimental to expose the circuit portion itself to adhesive, though not required, which may reduce processing steps and ultimately cost. [0213] Referring now to Figure 31C, each stack of circuit portions 3120 are diced according to known techniques. La the event that the dicing does not provide a smooth, planar edge, the wiring edge may be polished to expose the conductors 3124 for each circuit portion 3120. [0214] Figure 31D shows edge interconnection of the plural circuit portions 3120 with a conductor 3126. This may be accomplished by masking and etching a deposited thin-film of conducting material in a well known manner to electrically contact the conductor of each circuit portion. Other interconnection schemes, including Massive Selection Architecture (MSA) addressing, are described in more detail in the aforementioned U.S. Patent Nos. 5,786,629 and 6,355,976.

[0215] Of notable importance is that the edge interconnects can provide functionality during processing of the vertically integrated chip and in the end product (the vertically integrated chip). During processing, the edge interconnects may be used for diagnostic purposes. Malfunctioning circuit portions may then be avoided during interconnection of the plural circuit portions. Alternatively, such malfunctioning circuit portions may be repaired. As a still further alternative, a stack of N circuit portions may be reduced (Le., cut horizontally along the plane of the circuit portion) to eliminate the malfunctioning circuit portion, providing two or more stacks less man N. This may dramatically increase overall yield of known good dies (KGD)₅ as instead of discarding a stack N with one or more malfunctioning circuit portions, two or more stacks each having less than N circuit portion layers may be used for certain applications.

[0216] Further, note that the conductors 3124, 3126 or other conductors described further herein may comprise conventional electrical conductors, such as conductive traces. Alternatively, the conductors may comprise electromagnetic conductors, for example, optical conductors to conduct an optical signal from one circuit portion 3120 to another circuit portion.

[0217] Referring back to Figure 3 ID, in an alternative embodiment, a vertically integrated stack of edge interconnects 3124 can provide vertical integration with a second vertically integrated chip as described herein. As can be seen in Figure 3 ID, the integrated stack of edge interconnects 3126 is rotated about its vertical axis to form, in effect, a wiring stack. By bonding the rotated integrated stack of edge interconnects to the second vertically integrated chip, wiring flexibility can be achieved. For instance, the rotated integrated stack of edge interconnects can provide more than one layer of wiring flexibility on a horizontal scale. This is useful, for instance, with control circuitry needed for a massive data storage chip where multiple address lines and control circuitry is required for addressability and control.

[0218] In a further embodiment, edge interconnects may be used for Massive Selection Architecture (MSA) addressing, are described in more detail in the aforementioned U.S. Patent Nos. 5,786,629 and 6,355,976. [0219] Referring to Figure 32A, another example of a circuit portion is shown having chip edge interconnect architecture suitable for three-dimensional integration. Further details for edge interconnect architectures may be found in the aforementioned Fans U.S. Patent Nos. 5,786,629 and 6,355,976. In this embodiment, a circuit portion C is formed within an insulating region I of the device layer of the selectively bonded layered substrate. Here, conductors are formed on multiple edges of each circuit portion, represented as WL, WR and WR/WL. Note, however, that conductors may also or optionally extend in directions perpendicular to the layer in all directions (e.g., to all four major edges of me circuit portion). [0220] The device layer having plural circuit portions and multiple edge extending conductors are then aligned and stacked as shown in Figure 32B. The layers are aligned and stacked such that plural circuit portions form a vertically integrated stack. Depending on the desired vertically integrated device, the circuit portions for each layer may be the same or different. Further, although edge interconnects are shown on each layer, it is contemplated that certain layers may have one, two, three or four edge interconnects. It is further contemplated that some layers may have only through interconnects (one or more). It is still further contemplated that some layers may have one, two, three or four edge interconnects and one or more through interconnects.

[0221] In a preferred embodiment, the N layers are stacked, and subsequently all N layers are bonded in a single step. This may be accomplished, for example, by using UV or thermal cured adhesive between the layers. Note that, since interconnects are generally at the edges of each chip, in certain embodiments it may not be detrimental to expose the circuit portion itself to adhesive, though not required, which may reduce processing steps and ultimately cost. [0222] Referring now to Figure 32C, each stack of circuit portions are diced according to known techniques. In the event that the dicing does not provide a smooth, planar edge, the wiring edge may be polished to expose the conductors for each circuit portion. [0223] Referring to Figure 32D there is shown edge interconnection of the plural circuit portions with conductors WR and WL (electrical or optical), although it is contemplated that some or all layers may also have edge interconnects perpendicular to the page (to and/or fro). This may be accomplished by masking and etching a deposited thin-film of conducting material in a well known manner to electrically contact the conductor of each circuit portion. Other interconnection schemes are described in more detail in the aforementioned U.S. Patent Nos. 5,786,629 and 6,355,976.

[0224] Of importance is that the edge interconnects can provide functionality during processing of the vertically integrated chip and in the end product (the vertically integrated chip). During processing, the edge interconnects may be used for diagnostic purposes. Various options are available. For example, one or more of the edge interconnects may be for diagnosis and the other(s) for power, data, memory access, or other functionality of the individual circuit portion. One or more of the edge interconnects may be redundant, to improve device yield. The edge interconnects may independently access different areas of the circuit portion for increased functionality. Massive storage addressing is also capable, as customized interconnects may be provided in high density storage devices. [0225] Figure 32E shows an isometric view of a vertically integrated chip, shown without interconnects W. Figure 32F shows a possible vertically integrated chip shown with interconnects W. Note that various combinations of interconnections W may be provided, depending on the desired functionality. The use of one, two, three or four edges, as well as optional through conductors (e.g., at the top and bottom layers of the stack), further allows for orders of magnitude more interconnect locations (as compared to through interconnects alone) and very high traffic interconnect, using up to all 6 sides (or more if other geometries are provided) of the three dimensional vertically integrated chip. Further, multiple conductors may extend from each edge, e.g., associated with different portions of the circuit portion at the particularly layer, or redundant. [0226] Referring to Figure 33, another example of a circuit portion is shown having chip edge interconnect architecture suitable for three-dimensional integration. In this embodiment, a circuit portion C is formed within an insulating region I of the device layer of the selectively bonded layered substrate. Here, one or more conductors are formed across the surface of the device layer atop the circuit portions. Generally, the portions extending (right and left as shown in the Figure 33,) across the chip portion are provided for redundancy, to increase yield in the event that one side malfunctions or is not able to be interconnected in fabrication of the vertically integrated chip. Note that, as described above, multiple conductors may be provided across the wafer, e.g., to access different regions of the circuit portions. [0227] Referring to Figure 34A, another example of a device layer 3001 is shown, having through interconnect architecture suitable for three-dimensional integration. A circuit portion 3420 is formed within an insulating region 3422 of the device layer 3001 of the structure 3000. A conductor 3428, which may be an electrical or an optical conductor, is formed, operably originating at the circuit portion 3420 and extending to the bottom of the device layer 3001 of the structure 3000. Each circuit package is represented by the dash-dot lines. The bulk region 3002 serves as mechanical and thermal support during processing of the circuit portion 3420 and the conductor 3428. The conductors 3428 (a plurality of which may be associated with each circuit portion 3420, as mentioned above) may extend to the edge of the bottom of the device layer 3001, or alternatively may extend in the direction of the edge of the bottom of the device layer 3001, whereby polishing steps are performed to expose the conductors 3428 for vertical interconnect. A handler then may be utilized to remove the device layer 3001 generally as described herein.

[0228] The device layer 3001 having plural circuit portions 3420 and through conductors 3428 are then aligned and stacked as shown in Figure 34B and described in further detail herein. The layers are aligned and stacked such that plural circuit portions 3420 form a vertically integrated stack. Depending on the desired vertically integrated device, the circuit portions 3420 for each layer may be the same or different.

[0229] In one embodiment, the N layers 3001 are stacked, and subsequently all N layers 3001 are bonded in a single step. This may be accomplished, for example, by using UV or thermal cured adhesive between the layers 3001. To avoid contact problems between vertical layers, adhesive at the contacts should be avoided. As best shown in Figure 34C, each stack of circuit portions is diced according to known techniques.

[0230] Alternatively, and referring to Figure 35, the circuit portion 3520 may be formed first on or in the device layer 3001, and the through conductor W 3528 extending from the top of the circuit portion 3520 to the top of the device layer 3001. The region above the circuit portion may be processed to provide the conductor 3528 and insulating material 3522 (e.g., the same material as the insulator for optimal compatibility) as shown. [0231] Referring now to Figure 36, another optional feature to enhance interconnection of the vertical circuit portions is shown. Generally at the top of each circuit portion 3620, a conductor 3630 is provided. This conductor 3630 serves to optimize conduction from the through conductor 3628 of the layer above upon stacking. This conductor 3630 may comprise solidified material such that the contact derived upon stacking is sufficient to provide contact between layers. Alternatively, the conductor 3630 may comprise a solder bump, such that adjacent conductors may be joined by heating. Further alternatively, the conductor 3630 may comprise electrical connection between adjacent circuit portions 3620. Still further, the conductor 3630 may comprise optical waveguides for purely optical connections. The joinder of the conductors may be accomplished as each layer is stacked, or preferably after all N layers have been stacked so as to minimize detriment to conducting connections caused by several reflow operations as reported in the aforementioned U.S. Patent No.6,355,501.

[0232] In another method to form the through conductors (shown, for example, in Figures 34 and 38), and referring now Figures 37A-(TC6)C, separate device layers 3001', 3001" may form the circuit portion layer. Referring to Figure 37A, there is shown a device layer 3001' having circuit portions each having a conductor 3732 intended for contact with another device layer having the through contacts. The conductor 3732 may have a solder bump or a solidified permanent conductor. Note that a second conductor portion 3732 may be provided as described hereϊnabove with reference to Figure 36 for conduction from the through conductor of the layer above upon stacking. Figure 37B shows a device layer 3001" having through connects 3734. The layers may be stacked, bonded, and electrical contacts joined, as shown in Figure 37C to provide a sub-stack comprising the circuit portion layer 3001' and the conductor layer 3001".

[0233] Referring to Figure 38A₅ another example of a device layer 3001 is shown, having a hybrid edge interconnect and through interconnect architecture suitable for three- dimensional integration. A circuit portion 3820 is formed within an insulating region 3822 of the device layer 3001 of the structure 3000. A conductor 3828, which may be an electrical or an optical conductor, is formed, operably originating at the circuit portion and extending to the bottom of the device layer 3001 of the structure 3000. It will be understood that 3828 may also be a mechanical coupler for use in, for example, a MEMS device. Another conductor 3824 is provided operably originating at the circuit portion 3820 and extending to the edge of the circuit package, represented by the dash-dot lines. The bulk region 3002 serves as mechanical and thermal support during processing of the circuit portion 3820 and the conductor 3824, 3828. The conductors 3828 (a plurality of which may be associated with each circuit portion, as mentioned above) may extend to the edge of the bottom of the device layer 3001, or alternatively may extend in the direction of the edge of the bottom of the device layer 3001, whereby polishing steps are performed to expose the conductors 3828 for vertical interconnect. It will be understood that the 3828 and 3824 can be fabricated to predetermined locations along the wafer so that edge extending conductors can be fabricated anywhere along the wafer edge. [0234] A handler then may be utilized to remove the device layer, generally as described herein. The device layer 3001 having plural circuit portions 3820, edge extending conductors 3824 and through conductors 3828 are then aligned and stacked as shown in Figure 38B and described in further detail herein. The layers are aligned and stacked such that plural circuit portions 3820 form a vertically integrated stack. Depending on the desired vertically integrated device, the circuit portions 3820 for each layer may be the same or different. [0235] In certain embodiments, the N layers 3001 are stacked, and subsequently all N layers 3001 are bonded in a single step bonded. This may be accomplished, for example, by using UV or thermal cured adhesive between the layers 3001. [0236] Referring now to Figure 38C, each stack of circuit portions 3820 are diced according to known techniques. In the event that the dicing does not provide a smooth, planar edge, the wiring edge may be polished to expose the conductors 3824 for each circuit portion 3820.

[0237] Figure 38D shows one aspect of the overall interconnection, the edge interconnection of the plural circuit portions with a conductor 3826 (electrical or optical). This may be accomplished by masking and etching a deposited thin-film of conducting material in a well known manner to electrically contact a conducting portion of each circuit portion. Other interconnection schemes are described in more detail in the aforementioned

U.S. Patent Nos. 5,786,629 and 6,355,976.

[0238] Note that when both edge and through interconnects are used, one or both types may be used to interconnect the circuit portions. The different interconnects may be redundant or independent. Alternatively, the edge interconnects may be provided mainly for diagnostic purposes, as described above. In a further alternative embodiment, both types of interconnect may be used to provide redundancy, thereby reducing the likelihood of vertically integrated chip malfunctions due to interconnect between chip portions.

[0239] To form the through conductors (as shown in Figures 34 and 38), each through conductor for each chip portion may first be formed (e.g., by etching a hole and filling the hole with conductive material), and the circuit portion subsequently formed atop the conductor.

[0240] Referring now to Figure 39A, an alternative circuit portion layer is shown. A buried oxide layer (BOx) is formed in the device layer generally at the interface of the bulk substrate and the device layer. This buried oxide layer may be formed by various methods known, in the art, such as ion implantation of O⁺ ions. Further, the buried oxide layer may be formed before or after the device layer is selectively bonded to the bulk substrate. [0241] In embodiments where the buried oxide layer is formed before the device layer is selectively bonded to the bulk substrate, an a SiO_x layer may be formed at the surface of the device layer prior to selective bonding to the bulk substrate. The device layer is then selectively bonded to the bulk substrate. Note that it may be desirable to treat the oxide layer prior to bonding to enhance strong bonding.

[0242] In embodiments where the buried oxide layer is formed after the device layer is selectively bonded to the bulk substrate, the device layer may be, for example, oxygen implanted to form the oxide layer at the desired depth, i.e., at the interface of the bulk substrate and the device layer. It may be desirable to mask the intended strong bond regions of the device layer to locally prevent oxidation of the strong bond regions. [0243] After formation of the buried oxide layer, circuit portions C are formed adjacent the buried oxide layer in the weak bond region of the device layer. Conductors W2 are formed (e.g., deposited) in electrical or optical contact with the circuit portions, and conductors Wl are in electrical or optical contact with the conductors W2. Note that conductors Wl and W2 may be formed in one step, or in plural steps. Also, while the conductors Wl and W2 are shown to form a T shape, these conductors (or a single conductor serving the same purpose) may be L-shaped, rectangular, or any other suitable shape. [0244] After the device layer is removed from the bulk substrate (as described above), the buried oxide layer is then exposed. As shown in Figure 39B, a region of the buried oxide layer may be etched away, and a through conductor W3 formed therein. This conductor W3 serves to interconnect with a conductor Wl of an adjacent device layer upon stacking. [0245] Referring now to Figure 40A, an embodiment of an alternative circuit portion layer and associated conductors is shown. A buried oxide layer (BOx) is formed in the device layer generally at the interface of the bulk substrate and the device layer. A conductor is formed on the BOx at the region where the circuit portion is to be formed. The circuit region is formed, and conductors W2 and W3 (or an integral conductor) is formed atop the circuit portion. Note that the conductor (or conductor portion) Wl is formed with tapered edges and a protruding ventral portion.- this serves to, among other things, facilitate alignment and enhance mechanical integrity of the conductor.

[0246] Referring now to Figure 4OB, after the device layer is removed from the bulk substrate (as described above, preferably by peeling), the buried oxide layer is then exposed (e.g., etched away) to form W3 regions. Preferably, these regions match the shape and size of the tapered edged conductor or conductor portion Wl . [0247] As shown in Figure 4OC, a solder plug is provided to ultimately form the conductor W3, in the W3 region. This conductor W3 serves to interconnect with a conductor Wl of an adjacent device layer upon stacking, as shown in Figure 4OD. In one embodiment, the stacked layers may be reflowed as the layers are stacked. In a preferred embodiment, the entire stack is subject to reflow processing after N layers are formed. In still another embodiment, the stack may be reflowed in sections. It will be noted that the shape and taper of the conductors Wl and W3 of separate layers further serve to assist in mechanically aligning the stacked layers.

[0248] Referring now to Figure 41, a further embodiment of a device layer for forming a three-dimensional circuit or memory device is shown. A buried oxide layer (BOx) is formed in the device layer generally at the interface of the bulk substrate and the device layer. This buried oxide layer may be formed by various methods known in the art. Further, the buried oxide layer may be formed before or after the device layer is selectively bonded to the bulk substrate. Note that the device layer having the BOx layer may be removed as described above to derive a "raw" SOI wafer layer that may be provided to a customer or stored for later processing.

[0249] In embodiments where the buried oxide layer is formed before the device layer is selectively bonded to the bulk substrate, an a SΪO₂ layer may be formed at the surface of the device layer prior to selective bonding to the bulk substrate. The device layer is then selectively bonded to the bulk substrate. Note that it may be desirable to treat the oxide layer prior to bonding to enhance strong bonding, or to mask the intended strong bond regions of the device layer to locally prevent oxidation.

[0250] In embodiments where the buried oxide layer is formed after the device layer is selectively bonded to the bulk substrate, the device layer may be, for example, oxygen implanted to form the oxide layer at the desired depth, i.e., at the interface of the bulk substrate and the device layer.

[0251] After formation of the buried oxide layer, circuit portions C are formed adjacent the buried oxide layer in the weak bond region of the device layer. One or more conductors W are formed (e.g., deposited) in electrical or optical contact with the circuit portions, and may extend to any dimensional edge of the chip, as described above. [0252] After the device layer is removed from the bulk substrate (as described above), the buried oxide layer is then exposed. The BOx layer may serve as a transparent insulator layer, and may serve to shield one layer from another when layers are stacked, as described herein. Further, the Box layer provides a ready insulator for use in isolating circuit portions or to provide noise shielding among the conductors. Further, holes may be etched in the BOx layer, as described above with reference to, e.g., Figures 39B and 4OB. [0253] In certain embodiments, it may be desirable to enhance the interconnect of wafer scale or chip scale stacked devices described herein, by increasing size (contact area), conductivity (reducing resistivity), or both. Referring now to Figure 41, one embodiment of enhancing edge interconnect conductivity is shown. In general, ion implantation provide excessive doping (n++ or p++) in the region of the (e.g., under) metallization layer. Such n++ or p++ doping is known in the art. Thus, interconnects provided in this manner enhance overall conductivity, e.g., for connecting to edge exposed conductors. This step may occur before or after metallization, and generally before the device layer including circuit portions having metallization is removed (or before individual devices are removed). [0254] In another method to form interconnects, particularly through interconnects, thermo-electric migration processing may be used. Referring now to Figure 42, a conductive metal 4240 capable of thermo-electric migration (e.g., aluminum) is deposited on top of a substrate 4244, e.g., a silicon layer. Upon application of an electrical field at elevated temperatures (e.g., above 200 C), conductive metal 4240 migrates through the substrate providing a conductive path. This process may be used to form through interconnects of at least up to 10 micrometers in thickness (migration direction). The thermo-electric migration processing is performed on a device layer of a multiple layer substrate, leaving through interconnects for circuit portions to be formed on the device layer. Alternatively, the layer may be subject to thermo-electric migration prior to selectively bonding the device layer to the bulk layer. Alternatively, this could be a separate layer as an interconnect. The voltage required for the thermo-electric migration may range from about 10V to about 1000V, depending on the thickness of migration. [0255] Referring to Figure 43, a plug fill method of enhancing contact area and conductivity is shown. A tapered etch, e.g., generally at a 45 degree angle for preferential etching, is formed in the substrate. A conductor is formed across the top of the substrate, and traversed into the tapered etched region. Note that small angles (preferably less than 60, more preferably less than 45 degrees) are desired to minimize the likelihood of mechanical failure of the conductor. The tapered etched region is then plug filled with suitable conductive material. This tapered etched portion is preferably located at edges dies as will be apparent. The plug is cut along the cut line, exposing the conductive plug material and the conductor. Several layers may be stacked and edge connected, whereby contact resistance is significantly minimized by the existence of the conductive plug portions. [0256] Via holes may be etched (e.g., preferably a tapered etch of about 45 degrees) for access to metallization on vertically integrated devices. The via hole is plugged with meltable or sinterable conductive material. Referring to Figure 44, a through interconnect formed with the present method is described. Note that the metallization extending in the x-y plane may extend as edge connects. A tapered via hole is etched in the lower layer. Metallization is formed therein, and the via is plug filled with meltable or sinterable material. A subsequent layer is formed atop the first layer. A tapered via hole is etched in the upper layer. Metallization is formed on the top layer, and the via is plug filled with meltable or sinterable material.

[0257] In one embodiment, the conductive plug material is sintered or melted as the layers are stacked. This may further serve for alignment bonding, Le., not temporary bonding, in that it will not be removed as the joint is a contact, and not always sufficient bond strength to serve as the sole permanent bond.

[0258] Preferably, the meltable or sinterable conductive material is not melted or sintered until the final bonding step, preferably fusion or other bonding suitable to also melt or sinter the conductive plug material. The customer may be provided with the layered devices after fusion and conductive melting/sintering, or before fusion and conductive melting/sintering. [0259] Referring to Figure 45, shielding layers may be provided between adjacent layers. This prevents cross noise between circuit portion layers. With through connects, noise radiates from one layer to the next. This is a known problem in vertically stacked circuits. Because certain embodiments of the present invention rely on edge connects, a shielding layer is provided. The shielding layer is formed of a material such as copper, tungsten, molybdenum, or other conductive material. In certain embodiments, this shielding layer further serves to remove heat. The shielding layer and the adjacent metallization layers are suitably insulated as is known in the art. Beneficially, any noise created by one layer is not transmitted to adjacent layers. This is particularly desirable for mixed vertically integrated circuits, including combinations selected from the group of useful devices consisting of power, analog, RF, digital, optical, photonic, MEMs, microfluidics, and combinations comprising at least one of the foregoing types of useful devices. The shielding layer may further be used in optical connected circuits so as to form cladding layers. This shielding layer may also serve as a ground plane to create ultra high speed and ultra wide bandwidth transmission lines as is well known in the art.

[0260] Referring to Figure 46, channels may be provided between layers, to allow for heat dissipation. The channels for heat removal may carry fluid (liquid or gas) for heat removal. For example, the channels may allow for passive air or other separate cooling fluid to flow through the layers for cooling. Alternatively, microfluidics pumps or other devices may be included to provided ah- or other optional fluid cooling as discreet layer. [0261] Generally, for purposes of this discussion, it will be understood that in the multilayer structure of the invention, mϊcrofluϊdic devices can additionally be fabricated on the multilayer substrate. It will be understood that interconnects and via holes serve similar electrical fiinctions to grooves, wells and channels of microfluidic devices. Aside from some electrokinetic microfluidic devices which required electrical or optical controls, most microfluidic devices are mechanical devices composed of microscale structures, with fabrication techniques commonly used in integrated circuit fabrication. Therefore, one skilled in the art will understand that, as used herein, terms such as interconnects, conductors, electrodes and via holes may refer to ports, grooves, wells, and microchannels in the case of microfluidic devices.

[0262] For both MEMs devices and microfluidic devices, there must be a deconstruction of the desired device into a series of thin horizontal slices. Generally, the desired thickness is anywhere between 2 and 10 microns. Each of these slices is created on a silicon wafer using one of the many MEMS or microfluidic known wafer processing techniques. Once the MEMS or microfluidic slice has been created on the top surface of a wafer, the slice is peeled off the wafer and stacked on the top of the other slices making up the MEMS or microfluidic structure. Through this successive peeling and stacking, a MEMS or microfluidic device up to a centimeter high, having complex internal structure and geometry, can be created. [0263] Referring to Figure 47, these channels may include heat conductive portion (i.e., deposited metal) to further assist in heat dissipation. Alternatively, these channels may be formed as a waffle like structure.

[0264] Referring now to Figure 48, the channels or other heat conductive portions associated with each circuit portion may be formed on the underside of the device layer when it is maintained by the handler.

[0265] These channels may be formed after formation of the circuit portions and conductors as described above. The shielding layer may optionally be formed directly on these channels to form the structures shown in Figures 46and 47. [0266] Alternatively, the shield and/or heat conductive portions may be formed on the underside of the device layer prior to selective bonding of the device layer to the bulk substrate. Further, the shield and/or heat conductive portions may be formed as one or more separate layers that are aligned, stacked and bonded to form the structures shown in Figures 45^8. [0267] In another embodiment, the channels may be formed prior to selectively bonding the device layer to the bulk substrate. For example, as described above, one treatment technique for forming the weak bond regions involves etching the surface of the weak bond regions. During this etching step, pillars are defined in the weak bond regions on one or both surfaces. The pillars may be defined by selective etching, leaving the pillars behind. The shape of the pillars may be triangular, pyramid shaped, rectangular, hemispherical, or other suitable shape. Alternatively, the pillars may be grown or deposited in the etched region. Another aforementioned treatment technique involves inclusion of a void area, e.g., formed by etching, machining, or both (depending on the materials used) at the weak bond regions in one or both layers. Accordingly, when the first layer is bonded to the second layer, the void areas will minimize the bonding, as compared to the strong bond regions, which will facilitate subsequent debonding. For selective bonding purposes, both for the pillars and the void areas, since there is less bonding surface area for the material to bond, the overall bond strength at the weak bond region is much weaker then the bonding at the strong bond regions. For heat dissipation, these pillars or void areas also define channels. Optionally, these channels may include heat conducting materiel deposited therein as described above. [0268] As described above, the conductors may be formed by depositing suitable conducting material in operable electrical or optical contact with the circuit portion. In addition, or alternatively, conductors may be formed inherently in the process of forming the device layer. [0269] As described above, one of the treatment techniques for forming the strong bond region involves use of one or more metal regions at the weak bond regions of one or both surfaces. For example, metals including but not limited to Cu, Au, Pt, or any combination or alloy thereof may be deposited on the weak bond regions. Upon bonding of the layers , the weak bond regions will be weakly bonded. The strong bond regions may remain untreated (wherein the bond strength difference provides the requisite strong bond to weak bond ratio with respect to weak bond layers and strong bond regions), or may be treated as described above or below to promote strong adhesion.

[0270] With the conducting layer preformed at the weakly bonded side of the device layer, it is ready for processing of the circuit portion. In certain embodiments, the circuit portion may be formed to a depth sufficient to contact the preformed conducting layer. In certain other embodiments, the preformed conducting layer may serve as at least a portion of the conductor for the subsequent level. It will be appreciated that the preformed conducting layer may be left as is, or may be etched to form a desired conducting pattern. [0271] Alternatively, instead of forming a metal layer for weak bonding purposes at the underside of the device layer, plural treatment techniques may be used to form the metal laj'er in the desired pattern of the conducting layer. Metal layers may be formed after one or more other treatment techniques (e.g., roughening). Further, metal layers may be formed prior to one or more other treatment techniques.

[0272] In a further embodiment, a separate layer of the stack may be provided devoted to interconnection. This layer operably allows for routing and bridging to avoid congestion while minimizing the need for overlaid (insulated) edge wires. For example, the horizontal (x direction) connection on Figure 32F may be formed inside the layer if that layer was a congestion layer as described herein.

[0273] The various methods described herein are preferably carried out as described on a wafer scale. However, it is contemplated that many of the features are very useful even for vertically integrated chip fabrication on a chip scale.

[0274] Bonding as described herein may be temporary or permanent. Temporary bonds may be formed, for example, as described above with reference to alignment — that is, after the layer is properly aligned, a temporary bond is formed at local regions of the layer. Note that this bond may remain after final processing, or it may be decomposed as described herein. Further, this bonding step, generally occurring after alignment, may be sufficient to serve as a "permanent^"' bond.

[0275] Generally, permanent bonding of the separate layers after alignment as described herein may be accomplished by a variety of techniques and/or physical phenomenon, including but not limited to, eutectϊc, fusion, anodic, vacuum, Van der Waals, chemical adhesion, hydrophobic phenomenon, hydrophilic phenomenon, hydrogen bonding, coulombic forces, capillary forces, very short-ranged forces, or a combination comprising at least one of the foregoing bonding techniques and/or physical phenomenon. [0276] In one embodiment, radiation (heat, UV, X-ray, etc) curable adhesives are used for simplicity of fabrication. The UV bonding may be carried out as each layer is stacked, or as a single step.

[0277] In certain embodiments, when UV bonding is carried out as single step, the edge portions of the wafer, or of the chip if fabrication is on a chip scale, are UV transparent, for horizontal UV access. To cure the adhesive via radiation from the top of the wafer, radiation transparent regions may be provided at various layers to expose the adhesive to suitable radiation.

[0278] In other embodiments, the layers are cured layer by layer. In still other embodiments, adhesive may be applied from the edges.

[0279] Preferably, portions of the die include adhered sections, and accordingly may include radiation transparent regions.

[0280] In another embodiment, to avoid glue exposure to the metallized areas where interconnects are to be formed, or to avoid glue exposure to the circuit or other useful device portions, glue may be patterned on the surface(s) to be adhered. In one embodiment, masking the areas to avoid and depositing adhesive there around may provide a patterned adhesive. Alternatively, controlled deposition may be used to selectively deposit the adhesive. Note that the tolerance for the adhesive may be greater than tolerances at other process steps.

[0281] To cure the adhesive, edge radiation transparent portions may be provided, generally as described in aforementioned U.S. Patent No. 6,355,976. Alternatively, as described above, radiation transparent windows may be provided in optical alignment with the patterned adhesive regions.

[0282] The patterned adhesive is advantageously decomposable such that the adhesion may be temporary. Thus, after the entire stack is formed, the temporary bonds may optionally be decomposed, and the stack permanently bonded by other means, such as fusion. [0283] After the stack is diced, the edges are metallized. The metallization may comprise at least one layer/pattern. Plural metallization layers may be provided, which are preferably insulated as is known in the art.

[0284] Various products and devices may be formed using the processes disclosed herein. As mentioned above, "blanks", both as single layer and vertically integrated layers (complete with interconnections and optional addressing and encoding functionality), generally of identical layers. Another series of products and devices may be formed from different layers. These may be standard (e.g., MEMs or microfluϊdics with integrated processors and/or memory), or alternatively may be "made to order" based on needs. For example, GPS, RF, power cells, solar cells, and other useful devices may be integrated in the vertical stacks. [0285] Vertically integrated microelectronics may contain a variety of useful structures or devices formed therein. For example, very high speed processing may be accomplished by stacking a multitude of processing circuits according to the methods herein. Even more speed may be derived if the MSA architecture is utilized. [0286] In another embodiment, massive data storage (e.g., capable of 64 GB) devices may be formed according to the methods herein. Such devices may optionally incorporate vertically integrated memory with wired and/or wireless external connection, for communication and data transfer to and from PCs, TVs, PDAs, or other memory requiring devices. [0287] Li further embodiments, a vertically integrated device and/or a thin layer formed according to the methods herein may include one or more types of display devices, for example, based on thin film transistors. Notably, the herein processes allow various materials to be stacked, aligned and bonded to form common display devices. [0288] In another embodiment, a vertically integrated device formed according to the methods herein may include one or more processors and/or memory devices in conjunction with optical processing, communication or switching functionality. [0289] In another embodiment, a vertically integrated device formed according to the methods herein may include one or more processors and/or memory devices in conjunction with RF transmission and/or receiving functionality.

[0290] In another embodiment, a vertically integrated device formed according to the methods herein may include one or more processors and/or memory devices in conjunction with a global positioning system receiver and/or transmitter. [0291] In still further embodiments, a vertically integrated device formed according to the methods herein may include one or more processors and/or memory devices in conjunction with optical processing, communication or switching functionality; RF transmission and/or receiving functionality; and/or a global positioning system receiver and/or transmitter.

[0292] For example, one exemplary product may include a micro-jukebox, providing a user with 100+ hours of customized programming per week on media formed with me herein disclosed methods.

[0293] Other memory storage systems include optical, scan tolling microscopic/nano storage; and holographic storage.

[0294] Microfluϊdic devices may serve many purposes. Reductions in costs and increases in quality and functionality may be derived with the present methods and systems.

Microfluidics may be provided for various end uses, including but not limited to biotechnology, chemical analysis, scent producing apparatus, micro and nano scale material deposition, heat transfer (e.g., as described herein).

[0295] Microfluidic devices may also be formed by stacking channels, e.g., as described in part in the context of a handler in aforementioned PCT Patent Application Serial PCT/US/02/31348 filed on October 2, 2002 and entitled "Device And Method For Handling Fragile Objects, And Manufacturing Method Thereof.

[0296] In addition to stacking of channels, other microfluidic devices may be readily integrated, either by forming those devices according to known techniques, preferably on the weak bond regions of the device layer for easy removal, or by sectional assembly, generally described below with respect to MEMs. These devices may include, but are not limited to, micro flow sensors (e.g., gas flow sensors, surface shear sensors, liquid flow sensors, thermal dilution flow sensors, thermal transit-time sensors, and differential pressure flow sensors), microvalves with external actuators (e.g., solenoid plunger, piezoelectric actuators, pneumatic actuators, shape memory alloy actuators), microvalves with integrated actuators (e.g., electrostatic actuators, bimetallic actuators, thermopneumatic actuators, electromagnetic actuators), check valves, mechanical micropumps (e.g., piezoelectric micropumps, pneumatic micropumps, thermopneumatic micropumps, electrostatic micropumps), nonmechanical pumps (e.g., ultrasonically driven micropump, electro-osmosis micropump, electrohydrodynamϊc micropumps).

[0297] Using the processes described herein, an integrated device including microfluidics as well as processors), memory, optical processing, communication or switching functionality; RF transmission and/or receiving functionality; MEMs; and/or a global positioning system receiver and/or transmitter. [0298] PCT Application Serial No. PCT/US02/26090 filed on August 15, 2002 and entitled "Mems And Method Of Manufacturing Mems", which is incorporated by reference herein, discloses a method to form a vertically integrated stack including MEMs and other functionality. In general, the methods therein for forming each MEMs device at the weak bond regions of the device layer (as described herein). Preferably, on a wafer scale, the device layer is removed with minimal damage to the MEMs devices, and the wafer is generally stacked, aligned and bonded with other MEMs, or layers having other useful devices.

[0299] Referring now to Figure 49A, views of a cross section, a cantilever bearing edge, an electrical contact edge, and top views of plural layers formed in or on selectively bonded device regions of a multiple layer substrate are shown. In general, the FIG. represents a MEMs device that is formed by stacking cross sectional portions of the device. The bottom layer 1 generally serves as a substrate. Layer 2 includes an edge extending contact. Layer 3 includes a portion of the edge extending contact and an opening, generally to avoid restriction of movement of the mechanical components of the MEMs device. Layer 4 includes an opening. Layer 5 is a portion of a mechanical component (e.g., a cantilever) that is positioned within the stack for contact with the contact portion of layer 3. Layer 6 is another potion of the mechanical component of layer 5. Layer 7 is an opening to allow contact between the mechanical device in layer 6 and that in layer 8. Layer 8 includes openings and another mechanical component. Layer 9 shows an opening. Layer 10 shows the mechanical component extending to the edge of the vertically integrated chip.

[0300] Figures 49B and 49C show enlarged sectional views of processing certain steps in the MEMs device of Figure 49A. Note that each layer is generally very simple as a cross section, as opposed to micro-machining the desired cantilevered structure. This remains true for any MEMs device, as they may readily be broken down in cross section based on physical and mechanical characteristics.

[0301] Optionally, to support layers during stacking, a decomposable material may be provided in the areas to be voided and that require mechanical support. [0302] In further embodiments, logic circuits, memory, RF circuits, optical circuits, power devices, microfluidics, or any combination comprising at least one of the foregoing useful devices may be integrated in the stack (generally depicted in Figure 49A in cross section)

[0303] MEMs may include, but are not limited to, cantilevered structures (e.g., as resonators or resonance detectors), micro-turbines, micro-gears, micro-turntables, optical switches, switchable mirrors (rigid and membrane based), V-groove joints (e.g., for curling structures, bending structures, or for robotic arms and/or legs); microsensors that can measure one or more physical and non-physical variables including acceleration, pressure, force, torque, flow, magnetic field, temperature, gas composition, humidity, acidity, fluid ionic concentration and biological gas/liquid/molecular concentration; micro-actuators; micro- pistons; or any other MEMs device.

[0304] As mentioned, the MEMs devices may be broken down according to cross section and fabricated from several layers according to the teachings herein. However, it is understood that an entire MEMs device may be fabricated on the device layer, and transferred and stacked to another device, or used as a stand-alone device. [0305] Using the processes described herein, an integrated device including MEMs as well as processors), memory, optical processing, communication or switching functionality; RF transmission and/or receiving functionality; microfluidics; and/or a global positioning system receiver and/or transmitter. [0306] Other devices that may be formed according to the methods described herein include, but are not limited to, micro-jets (e.g., for use in micro-satellites, robotic insects, biological probe devices, directed smart "pills" (e.g., wherein a micro-jet coupled with suitable sensors is capable of locating certain tissue, for example, and with built in microfluidics, and a payload of pharmaceuticals, may direct the pharmaceuticals to the affected tissue)). Further devices that may be formed according to the methods described herein include bit sliced processors, parallel processors, modular processors, micro engines with microfluidics, IC, memory, MEMS, or any combination thereof [0307] A vertically integrated stack of lX2n (or 2nXl) crossbar switching trees is provided using the methods described herein (wherein n is the number of stages in a single layer). For example, referring now to the figures, N (N is the total number of layers) layers are stacked and assembled as described herein. This stack may be configured as N separate and distinct lX2n (or 2nXl) crossbar switching trees. Alternatively, with suitable interconnection between adjacent layers, it is possible to form aNX(N*2n)(or (N*2n)XN) switching system. [0308] A schematic example of each layer is shown in Figure 5OB. For example, each layer has one input coupled, via a binary logic tree configuration, to 2n outputs (or vice versa) through n binary stages (wherein the example shows 4 stages (n=l, 2, 3 and 4) wherein 2n=N= 24=16 outputs). Each succeeding stage contains twice as many branches as a preceding stage. By activating certain switches, inputs applied to the first stage of a binary logic tree are delivered as a suitable signal to the last stage of the logic tree. The switches may include electrical switches such as transistors, CMOS switches, well known analog switches, electro-mechanical switches such as MEMS switches or GaAs switches, optical switches, or magnetic tunneling switches.

[0309] Of course, other types of crossbar switch systems may be employed, including but not limited to tertiary systems, quaternary, or other decision making tree configurations. In general, at each stage, a decision is made from one branch to another.

[0310] The vertically integrated stack of lX2n (or 2nXl) crossbar switch layers may be used in various applications, including but not limited to network telephones, voice over

Internet protocol applications, video-on-demand applications, search engine applications, and other various computing applications. [0311] In preferred embodiments, the switches provide non-blocking capability, are capable of passing analog or digital signals, are capable of two-direction communication from stage n-1 to stage n, or from stage n to stage n-1.

[0312] Figure 51 shows an isometric view of a device having a first vertically integrated stack of lX2n crossbar switching trees arranged with respect to a second vertically integrated stack of lX2n crossbar switching trees. As shown, first stack and second stack may be substantially identical, except they are arranged in a rotated configuration. That is, first stack and second stack are oriented about 90 degrees relative one another. In this manner, 2n outputs of first stack may communicate with 2n inputs of second stack . Each stack may be configured as N separate and distinct lX2n (or 2nXl) crossbar switching trees; or alternatively, with suitable interconnection between adjacent layers, it is possible to form a NX(N*2n)(or (N*2n)Xl) switching system.

[0313] The interconnection between first stack and second stack may be by various interconnection structures or methods, such as electrical interconnection or optical interconnection.

[0314] The device may be particularly useful in various applications, including but not limited to network telephones, voice over Internet protocol applications, video-on-demand applications, search engine applications, and other various computing applications. [0315] One particular advantage of the present switching device is the ability to maintain open lines. Further, several outputs may be connected to one input, or vice versa.

[0316] In one embodiment, and referring to Figure 52A, a suitable configuration for a switch is provided, whereby one branch has a switch value that is a complement to the other, e.g., C and C(bar). This is useful in a one to one system, e.g., one input to one output. In another embodiment, and referring now to Figure 52B, added flexibility may be provided, such that Cl and C2 can be independent of each other. Therefore, in a network communications system, for example, one party can communicate to^' multiple parties, therefore forming a multi-channel switching network based on a binary tree configuration [0317] Referring to Figure 53A-53D, steps are shown to create a conductive post of coaxial configuration. A layer 5302 is provided having regions of conductive posts 5352. This layer 5302 is particularly suitable for use as a coaxial electrical interconnection layer between layers of a vertically integrated device. The device includes "bulk" regions (gray outside of rings), ring regions 5352 (annulus of ring) and post regions 5350 (gray within rings). Optionally, referring to Figure 53D, channels may be formed on one or both surfaces of the layer (away from the rings and posts), for example, as a heat sink structure. During formation, metal capable of thermoelectric migration is applied at regions corresponding with the bulk conductive regions and the post regions, as shown in Figure 53B. Upon thermoelectric migration, the conductor material migrates though the layer and forms the device shown in Figure 53C.

[0318] Referring to Figure 54A, an integrated system 5400 includes multiple vertically integrated devices 5402, 5404 according to the present invention (or multiple stacks, as the term is used herein) are interconnected through a layer 5406, e.g., through one edge. The stacks may be interconnected with an intermediate wiring layer and/or buffer layer and/or amplifier layer and/or shielding layer and/or cooling channels. The interconnecting layer(s) 5406 are typically orthogonal in relation to the plane of the layers of the stacks 5402, 5404. Figure 54B shows a method to make system 5400 . Stacks 5402, 5404 are provided. Layer 5406 is connected to an edge of stack 5402, for example, using a handler 5410 to assist in stacking, aligning and bonding. Stack 5404 is then aligned and bonded to layer 5406, for example, also using a handler 5410 (which may be the same or different device) to assist in stacking, aligning and bonding). [0319] Figure 55A shows an integrated system 5500, generally comprising a structure similar to the system 5400, further including a surface spanning layer 5508. This surface spanning layer may provide a wiring layer and/or a buffer layer and/or an amplifier layer and/or a shielding layer and/or cooling channels. Figure 55B shows a method of making the system 5500, starting with a structure similar to system 5400, and attaching the surface spanning layer 5508, e.g., with a handler 5510.

[0320] Referring to Figure 56A, an integrated system 5600 includes multiple vertically integrated devices 5602, 5604 according to the present invention (or multiple stacks, as the term is used herein) are interconnected through a layer 5606, e.g., between the top layer of stack 5604 and the bottom layer of stack 5602. The stacks may be interconnected with an intermediate wiring layer and/or buffer layer and/or amplifier layer and/or shielding layer and/or cooling channels. The interconnecting layer(s) 5606 are typically parallel in relation to the plane of the layers of the stacks 5602, 5604. Figure 56Bshows a method to make system 5600. Stacks 5602, 5604 are provided. Layer 5606 is connected to the top layer of stack 5402, for example, using a handler 5610 to assist in stacking, aligning and bonding. Stack 5604 is then aligned and bonded to layer 5606, for example, also using a handler 5610 (which may be the same or different device) to assist in stacking, aligning and bonding). Further edge connections may be made between certain or all layers of one of the stacks to certain or all layers of the other stack. The intermediate layer 5606 may facilitate edge interconnection, for example, if the intermediate layer 5606 is provided with suitable edge interconnects.

[0321] Figure 57A shows an integrated system 5700, generally comprising a structure similar to the system 5600, further including an edge interconnect layer 5708. This edge interconnect layer may provide a wiring layer and/or a buffer layer and/or an amplifier layer and/or a shielding layer and/or cooling channels. Figure 57B shows a method of making the system 5700, starting with a structure similar to system 5600, and attaching the edge interconnect layer 5708, e.g., with a handler 5710.

[0322] Referring to Figure 58A, an integrated system 5800 includes multiple vertically integrated devices 5802, 5804 according to the present invention (or multiple stacks, as the term is used herein) are interconnected through a layer 5806, e.g., between the top layer of stack 5804 and an edge of stack 5602. The stacks may be interconnected with an intermediate wiring layer and/or buffer layer and/or amplifier layer and/or shielding layer and/or cooling channels. The interconnecting layer(s) 5806 are typically parallel in relation to the plane of the layers of the stacks 5804 and orthogonal in relation to the plane of the layers of the stacks 5802. Figure 58Bshows a method to make system 5800. Stacks 5802, 5804 are provided. Layer 5806 is connected to the edge of stack 5802, for example, using a handler 5810 to assist in stacking, aligning and bonding. Stack 5804 is then aligned and bonded to layer 5806, for example, also using a handler 5810 (which may be the same or different device) to assist in stacking, aligning and bonding). Further edge connections may be made between certain or all edges of layers of one of the stacks to certain or all layers of edges of the other stack. The intermediate layer 5806 may facilitate edge interconnection, for example, if the intermediate layer 5806 is provided with suitable edge interconnects. [0323] Figure 59Ashows an integrated system 5900, generally comprising a structure similar to the system 5800, further including an interconnect layer 5908 spanning the surface of the top layer of stack 5902 and an edge of stack 5904. This interconnect layer may provide a wiring layer and/or a buffer layer and/or an amplifier layer and/or a shielding layer and/or cooling channels. Figure 59B shows a method of making the system 5900, starting with a structure similar to system 5800, and attaching the edge interconnect layer 5908, e.g., with a handler 5910. [0324] Certain aspects of the multiple stack systems described herein may be formed on a wafer scale. Of course, each individual stack comprising vertically integrated device layers may be formed on a wafer scale. Further,

[0325] In a further embodiment, and referring now to Figures 60A-60C, a vertically integrated device system 6000, or stack of stacks 6000, is shown including a first and second group 6002', 6002" of one or more layers interconnected by one or more third groups 6004 of one or more layers. In a preferred embodiment, the first group comprises a first stack 6002', the second group comprises a second stack 6002" and the one or more third groups comprise plural third stacks 6004. An important feature of the vertically integrated device 6000 is that the plural third stacks 6004 serve to interconnect one or more layers from the first stack 6002' and the second stack 6002" . The third stack 6004 provides smaller dimension layers and device features (e.g., 5-50% of the dimensions of first and second stacks 6002% 6002"), thereby capable of operating at higher speeds. For example, the 1^st and 2^nd stack may be cubes, parallelepiped, or similar structures having dimensions of about 1- several centimeters on edge (1 -several cc), and the 3^rd stack may be cubes, parallelepiped, or similar structures having dimensions of about 1-several millimeters (1-several mm") In certain preferred embodiments, these third stacks 6004 are dedicated to functions of the highest speed, which usually consume the most power. However, since the size of the third stack 6004 is smaller, the absolute power is relatively small. Further, the propagation delay is relatively small to achieve the highest speed.

[0326] In certain preferred embodiments, plural third stacks are provided and positioned relative one another so that spaces remain therebetween. These spaces may be used for cooling air or gas, or any one of many known cooling techniques. [0327] The one or more third stacks may include interconnection for communication between the first and second stacks. This serves to simplify the construction of the first and second stack, in that the need for via holes, edge connections or other connections between the first and second stacks may be minimized or altogether obviated. Further, as discussed above, the propagation delay is minimized between the first and second stack, since the third stack or stacks have substantially smaller dimensions thereby resulting in shorter propagation delays.

[0328] In certain preferred embodiments, the third stacks, or groups of second type layers, are oriented. For example, referring to Figure 6OA, the third stacks 6004 may be oriented substantially perpendicular to the orientation of the layers of the first and second stacks 6002% 6002". Interconnect layers (e.g., conductors) may be exposed on the edges of the third stacks, connecting with suitable connection locations on the first and/or second stacks 6002', 6002".

[0329] In a further embodiment, and referring now to Figure 6OB, the third stacks 6004 may be oriented substantially parallel to the orientation of the layers of the first and second stacks 6002', 6002". The extremity layers of the third stacks 6004 may include suitable interconnection locations for connecting with suitable connection locations on the first and/or second stacks 6002', 6002". Within the third stacks 6004, edge connects or via connects may be used to pass through multiple layers of the third stacks 6004. [0330] In certain embodiments, channels between plural 3^r stacks, particularly when oriented parallel to the 1^st and 2^nd stacks, may be used for interconnecting (wirelessly (e.g., optically) or wired) an additional functionality. For example, additional control singles, addressing signals, power lines, or other features may be added through this 3^rd stack. [0331] In a still further embodiment, and referring now to Figure 60C, the third stacks 6004 may be oriented at an angle with respect to the orientation of the layers of the first and second stacks 6002', 6002". Interconnect layers (e.g., conductors) may be exposed on the edges of the third stacks 6004, connecting with suitable connection locations on the first and/or second stacks 6002% 6002". This may be desirable for interconnecting at 6 feces of the 3^rd stack. Further, known propagation delays be be used. In certain embodiments, channels between plural 3^rd stacks, particularly when oriented at an angle relative to the 1^st and 2^nd stacks, may be used for interconnecting (wirelessly (e.g., optically) or wired) an additional functionality — on all six edges of the parallelepiped. For example, additional control singles, addressing signals, power lines, or other features may be added through this 3^rd stack.

[0332] In still further embodiments, the third stacks 6004 may be dimensioned, positioned and configured between the first and second stacks 6004 to provide shielding between the first and second stacks 6002% 6002".

[0333] The first and second stacks are preferably multilayer stack device. For example, the first and second stacks may be fabricated according to the methods described herein, or by other three dimensional device fabrication methods. The layers of each of the first and/or second stack may be heterogeneous or homogenous. [0334] In heterogeneous embodiments, analog devices, digital devices, optical devices, power electronic devices, RF layers, magnetic circuits, passive devices, power sources such as batteries, capacitors, and super-capacitors, wiring layers, buffer layers, transmission line layers, shielding layers, heat removal channels, memory devices, microprocessor layers, system on chip (SoC) and combinations comprising at least one of the foregoing types of devices may be mixed to form virtually any desired vertically integrated device.

[0335] Any of the l^-θ¹*¹ stacks may include buffer layers, wiring layers, amplifier layers, shielding layers, or cooling channels. In certain preferred embodiments, all of the layers of the 3^rd stacks are dedicated to these functionalities to serve primary device functionality based in the first and second stacks. Stack of Stacks

Small Stacks as connection for Large Stacks integrated device comprising one or more small feature stacks interconnected to a large feature stack, wherein said small feature stack has stack layers and/or features within these layers that are much smaller than the features and/or layers in the large feature stack

In one embodiment, and referring to Figure 61, a mechanical alignment method is provided for use in conjunction with the device layer wafer stacking. Mechanical protrusions or posts are provided on one layer, and receiving holes are provided on the other layer. When they mechanically fit, alignment is achieved.

In another embodiment, alignment may be performed with the method disclosed in aforementioned U.S. Patent No.6,355,976. As shown therein, a fixed reference is used at an alignment station, the layers are aligned with comparison to a reference, UV curable adhesive applied, and the layer is stacked on the previously stacked layers (or a substrate) maintain precise alignment based on the fixed reference, as compared to referencing marks on previous layers, which induces cumulative error build-up. UV light is applied as each layer is stacked. A method and system for of aligning plural layers generally utilizes a projected image of the layer to be aligned, wherein the projected image may be aligned with an alignment reference apart from the layer or stack of layers to be aligned, thereby eliminating inter-layer alignment induced error amplification described above and providing first order alignment

The method includes placing a first layer on a mechanical substrate. Between the first layer and the mechanical substrate, in a preferred embodiment, a low viscosity adhesive materials is included. This low viscosity adhesive material is preferably polymerizable (e.g., upon exposure to UV radiation), and optionally, this adhesive material may be decomposable, wherein alternative adhesives may be used to permanently bond a multitude of layers together after they have been formed according to the steps described herein.

The system further includes a polarizing reflector generally aligned at a 45-degree angle with respect to the first layer. A source of light is directed towards the polarizing reflector and is directed toward the first layer. Additionally, a quarter wave phase retarder is placed between the polarizing reflector and the first layer. This quarter wave phase retarder is optional, so that polarized light reflected from the reflector may subsequently reflect from layer one and transmit through the polarizing reflector, since the polarization state is reversed by the quarter wave phase retarder.

Layer one further includes one or more alignment markings. These alignment markings may be etched regions, materials applied to the layer, shaped regions, or other known alignment markings. When polarized or unpolarized light is transmitted toward the polarizing reflector, light reflects from these alignment markings, and, in certain embodiments, back through the quarter wave phase retarder and subsequently through the polarizing reflector to project an image of the positions of the alignment marks.

The image of the position of the alignment markings is compared with an alignment reference. This alignment reference includes alignment marks that correspond to the alignment marks on the first layer. If the first layer is properly aligned, as determined, for example, by a comparator, no further action is required. However, in the event that the layer is not aligned, light will pass through the alignment reference can be detected by a comparator or a detector, and an appropriate X-Y-theta subsystem system will serve to reposition the first layer in the x direction, the y direction, and/or the angular direction until the alignment markings in the alignment reference from the reflected light reflected through the polarizing reflector are aligned. When the detector detects a null value (i.e., the light from the first layer in alignment with the alignment markings on the alignment reference) the layers are aligned.

Alternatively, the alignment markings may be such that polarized light does not reflect, and a certain wavelength of polarized light is chosen that does reflect from the remaining unmarked portions of the layer. Thus, a null value will be attained when light is reflected at all portions except at the position of the alignment mark on the alignment reference.

In a preferred embodiment, the null detector or comparator is operably coupled to the

X-Y-theta subsystem, such that an automated alignment process may be attained. That is, if the null detector detects light, the X-Y-theta subsystem will be adjusted until a null value is detected.

In further alternative embodiment, instead of detecting a null value when alignment is correct, light may be transmitted through, for example, an aperture or transparent portion

(with respect to the light used) in the alignment reference corresponding to the alignment marking may be provided, wherein light passes through only when alignment is proper.

The described process may be repeated for a second layer, a third layer, etc. through an Nth layer. One alternative projecting system may including a scanning process, whereby the surface is scanned by a laser beam which has been reflected by the reflected been may be processed through appropriate software or through another comparator to an alignment reference. This may include use of known Fourier optics and other scanning and detection systems.

An important benefit of this system is that error due to error in the proceeding layer(s) is eliminating, since the alignment reference remains constant or known throughout the alignment and stacking operation. The N layers will all have been individually aligned with the alignment reference, thus the desired end product having a stack of N layers will be in proper alignment. With this method, extreme accuracies may be attained, since each individual layer is aligned with respect to a known or constant reference, as opposed to being aligned with respect to the preceding layer. Therefore, extreme accuracy may be attained, since, in the worst-case, alignment may be off due to a single error as opposed to an error multiplied for each of up to N layers.

When N layers have been stacked in aligned, they may be bonded together by the adhesives described above, and as mentioned, those adhesives may also be decomposed and substituted with another adhesive.

Referring to Figure 62, an exemplary system and method is described. The method includes placing a first layer 150 including an alignment marking 170 on a mechanical substrate 102. The alignment marking 170 may comprise a dot, line, curve, shape, or other marking formed on or within the layer by depositing, etching, or the like. As described further, the alignment marking 170 generally reflects light of a certain polarization.

The system further includes a polarizing reflector 104, generally aligned at a 45- degree angle with respect to the first layer 150. A source of light 106 is directed towards the polarizing reflector 104 and is polarized light 108 is directed toward the alignment marking 170 on the first layer 150. Additionally, a quarter wave phase retarder 110 is placed between the polarizing reflector 104 and the first layer 150. This quarter wave phase retarder 110 allows polarized light 108 reflected from the reflector 104 may subsequently reflect back 112 from alignment marking 170 and transmit through the polarizing reflector 104, as the polarization state is reversed by the quarter wave phase retarder 110.

When polarized light 108 transmitted from the polarizing reflector 104 having a first polarization state, polarized light with the same first polarization state reflects from these alignment markings through the quarter wave phase retarder 110, where the light is converted to a second polarization state, enabling the light reflected from the alignment markings to be transmitted through the polarizing reflector 104 to project an image 112 of the positions of the alignment marks.

The image 112 of the position of the alignment markings is compared with an alignment reference 114. This alignment reference 114 includes alignment marks that correspond to the alignment marks on the first layer. If the first layer is properly aligned, as determined, for example, by a null value within a comparator or detector 116, no further action is required. However, in the event that the layer is not aligned, light that passes through the alignment reference 114 can be detected by the comparator or a detector 116, and mechanical alignment of the layer 150 is required. Referring to Figure 63, a pair of alignment markings 270 may be provided to increase accuracy.

Referring to Figure 64, a pair of light sources may be directed to the polarizing reflector to decrease energy, each light source being directed to an area where the alignment marking is estimated to be, accounting for expected alignment error. Referring to Figure 65 in conjunction with Figure 66, X-Y-theta subsystems 490 and

590 are provided, which are controllable coupled to the detector or comparator. The X-Y- theta subsystem repositions the first layer in the x direction, the y direction, and/or the angular direction until the alignment markings in the alignment reference from the reflected light reflected through the polarizing reflector are aligned, as indicated by the detector or comparator. In a preferred embodiment, the null detector or comparator is operably coupled to the X-Y-theta subsystem, such that an automated alignment process may be attained. That is, if the null detector detects light, the X-Y-theta subsystem will be adjusted until a null value is detected.

When a low viscosity, polymerizable adhesive is used to adhere the layer 150 to the substrate (or a subsequent layer atop a preceding layer), the adhesive allows repositioning of the layer by the X-Y-theta subsystem. When alignment is attained, such adhesive material may then be polymerized to "set" the aligned layer in position.

As shown in Figure 65, X-Y-theta subsystems 490 includes a motion control system coupled to the wafer or to appropriate handles, for example, at the edges of the wafer. The motion control system may comprise one or more vacuum handlers attached to the edges or a designated annular area proximate the edge of the wafer layer, for example. Further, holes may be formed in the wafer to allow for access via an arm from the motion control system.

As shown in Figure 66, a pair of X-Y-theta subsystems 590 are provided on opposite sides of the layer to be repositioned in response to non-alignment detection by the detector or comparator.

In another embodiment, and referring now to Figure 67, plural optics systems (each of which is substantially similar to that of Figure 62) are provided to coincide with plural alignment marks for increased accuracy.

Referring now to Figure 68, a device 700 is shown that is suitable for one or more alignment process functionalities. The device includes plural sub-systems 710 therein. In one embodiment, the sub-systems serve single functionality, e.g., to write alignment marks or to detect alignment marks. For example, one device may includes plural sub-systems for writing alignment marks, and another device may include plural sub-systems for detecting alignment marks. To ensure alignment accuracy, such separate devices should be fabricated so that the writing position and the detection reference positions are substantially identical, or at least within the requisite device tolerance.

In one method of aligning using an alignment device, alignment marks may be positioned on a device layer during processing of the circuit portions. Here, alignment marks may be included on one or more of the mask(s) used for circuit portion processing, such that the alignment marks correspond to plural sub-systems for detecting alignment marks in the alignment mark detection device.

In another method of using an alignment mark detection device and a writing device, the devices themselves are positioned in alignment. Further, the devices may be bonded together to ensure accuracy of alignment. The sequence (Le., relative the layers to be aligned) in insignificant, so long as the device between the other device and the layer to be aligned is transparent to the other device. For example, if the outermost device is the alignment mark detection device, then the writing device should be optically transparent, for example, if optical reference mark detection is used or if other scanning is used. If the outermost device is the writing device, then the alignment device should be transparent to the writing signal, for example, if alignment mark writing is effectuated by exposing the layer to have marks written thereon to certain wavelength of light. Alternatively, mark writing can be at a known angle to allow bypass of the detection device.

In another embodiment, writing and alignment may be performed with the same device. For example, on optical array as described above can be used to both expose the layer to a marking light signal, and to subsequently detect the formed marks.

The alignment mark writing and/or writing and detection device, or an identical copy thereof, may also be used to mark and/or etch alignment marks in the one or more masks used to form circuit portions on each device layer. Conventionally, IC, MEMs, or other useful devices are formed of several different layers whereby the mask for each layer is aligned to previous mask. Here, the mask for the Nth layer is not aligned to the (N-l)th layer, but rather to a common writer/detector. In another embodiment, the writer/aligner may also be integrated into a device having mask writing functionality.

In a further embodiment a device layer may be provided with alignment marks, prior to circuit portion processing. The same or a substantially identical alignment mark writing device, as described herein, or other writing devices, is used to mark the mask(s) and or exposure devices to be used for forming at least a portion of the circuit, MEMs or other useful device region. Accurate alignment of first the device layer, then the mask(s) and/or exposure devices, is readily possible using a reference alignment mark detector that is matched with the alignment writer, thereby providing well defined patterns of useful devices on the device layer with matched alignment marks. Alternatively, as described herein, an integral alignment mark writer/detector may be used to ensure alignment accuracy.

This device 700 will allow one to achieve nano-scale accuracy. Using known nano- tools, or accurate lithographic methods, nano-sized holes can be drilled. In one example, the tunneling current may be detected through said nano-sized holes, e.g., for ultra precise alignment

In one method of using the device 700, nano scale electrode conductive marks may be provided on a layer 1. Layer 1 is preferably a non- oxidizable insulative substrate. A corresponding layer 2 includes insulative replica marks (e.g., oxidized) on a conductive substrate. The insulative replica marks may be made by the conductive layer 1.

Alternatively, nano-accuracy is made by tools described in commonly owned U.S. Patent Application Serial No. 11/077,542 entitled "Nanolithography and Microlithography Devices and Method of Manufacturing Such Devices", filed on March 10, 2005, which is incorporated by reference herein. During operation, layer 1 writes layer 2 on a device layer. Subsequently, layer 1 reads the increased resistance at the same layer 2 during stacking and aligning. Optionally, a different reader and writer may be used. Preferably, the same reader is used for all layers, to avoid cumulative misalignment and maintain first order alignment described herein.

Note that the device itself may be formed using the herein described multiple layer substrates to form each layer (not shown), and aligning, stacking and bonding plural layers. The subsystems 710 may include, but are not limited to, polarizing based systems, lens systems, light funnel, STM tip system, electron beam through aperture, cameras, apertures with light source, photodetector, apertures for electrons, ions and x-rays, and combinations comprising at least one of the foregoing. In a further embodiment, the alignment marks that are written may further include mapping lines or marks surrounding the center, for example. This is particularly desirable when scanning techniques are used, for example, whereby the scanner/comparator may not only detect when there is or is not alignment, but mapping instructions may be provided by detecting the known mapping marks. This, the systems and time requirements to "focus" in on an alignment mark is significantly reduced. For example, the comparator may determine that movement of the X-Y-theta subsystem(s) should position the layer -.1 microns X and +.05 microns Y, based on reading the mapping marks.

The above described novel alignment technique may result in aligning N layers with unprecedented nm accuracy. Such an alignment method, incorporated with the other multiple layer processing techniques and exemplary applications described herein, may substantially facilitate a multitude of 3-D micro and nano devices.

[0336] Referring now to Figure 69, another alignment method is disclosed. Here, a tapered hole 861 (e.g., having approximately 45 degree taper) is provided at an alignment position (e.g., in lieu of an alignment mark) on the plural device layers 862, 863, 864, 865, 866 to be stacked on a base layer 867. Such alignment holes 861 may be formed prior to formation of the useful structures or after formation of the useful structures (not shown). When the layers 862, 863, 864, 865, 866 are stacked, a light beam 868 is attempted to transmit through the holes. When the layer is not aligned, the light will not pass through. The layer is then shifted until light reflects 869 from the base layer 867. [0337] Alternatively, the tapered holes 861 may be filled with optically transparent material, for example, such as SiOx. Further, while not preferred as cumulative errors may occur, a layer may be aligned with the adjacent layer. [0338] Referring now to Figures 70A-70B, an alignment and interconnection method for wafer level stacking is provided. First, referring to Figure 7OA, a group of devices 22 are formed (generally upon or within a release layer; or upon or within weak bond regions of a strong bond/weak bond release layer. These devices 22 include associated conductors 42 , for example, for edge interconnect functionality. [0339] As described herein with respect to various alignment processes, a mask may be provided with alignment functionality. However, perfect grid alignment may still not be attained. For example, the relative positions of circuit portions and associated contacts may end up offset, i.e., out of perfect alignment, as shown by the dashed reference lines in Figure 7OA. This random skewing of the useful structure portions may be problematic for wafer level stacking, since hundreds of useful devices may be processed on a wafer and many wafer layers may be aligned and stacked prior to dicing individual vertically integrated devices (vertically integrated die).

[0340] To resolve this potential problem, at the wafer level, global interconnects or metallization may be provided. Generally, as shown in Figure 7OB, global metallization regions 44 comprise oversized metallization. That is, the metallization regions 44 are oversized as compared to the conductors 42, to ensure contact In general, these global metallization regions 44 are formed using the same mask at each level. The global metallization regions 44 are sufficiently large to compensate for any local die position offset. [0341] In one method of making a device layer having global metallization regions 44, after processing of the devices 22 with conductors 42, a mask having the set pattern of the global metallization regions 44 is provided, and the global metallization regions 44 are formed. Thus, the global metallization regions 44 form part of the device layer including devices 22 with conductors 42.

[0342] In another method of making a device layer having global metallization regions 44, a device layer is formed including processed devices 22 with conductors 42. As a separate layer, the global metallization regions 44 are formed, e.g., using a mask having the set pattern of the global metallization regions 44 to form a layer with the global metallization regions 44 are formed. Thus, the global metallization regions 44 are part of a separate layer that is aligned and bonded with the device layer having processed devices 22 with conductors 42. Note that since the global metallization regions 44 are oversized as compared to the conductors 42, the required alignment precision may be kept at an easily achievable value. [0343] Further, the global metallization also serves to provide edge interconnection as described above. Note that the cut line is shown at the end of the global metallization. This global metallization will facilitate edge interconnection or through interconnection for vertically integrated devices. For example, when a second layer is stacked with respect to a first layer having global metallization, the likelihood for a "missed" connection is minimized or eliminated if global metallization regions are formed at the contact portions of the useful devices. Note that the global metallization regions may be formed on one or both layers to be vertically integrated. In particular, if the global metallization layers are formed on both multiple layers to be vertically integrated, alignment error may be minimized especially if the same mask is used to form the global metallization regions 44 on each layer (or as a separate layer).

[0344] Referring now to Figure 71, a further optical alignment technique is provided. A first wafer and a second wafer are each provided with a matching pair of alignment windows, in the form of a pair of rectangles, for example, perpendicular one another. When the second wafer is moved over the first wafer, as shown, only a square is visible. Based on this pattern, movement is in the x direction until the second attempt pattern is seen. Then, movement is in the y direction until the light matches the alignment holes.

[0345] Alternatively, the handler may include a resonant layer, thereby serving as a handler and an alignment device. The handler may comprise any known handler, including that described in aforementioned PCT Patent Application Serial PCT/US/02/31348 filed on October 2, 2002 and entitled "Device And Method For Handling Fragile Objects, And Manufacturing Method Thereof.

[0346] An embodiment of this hybrid handler/LC aligner is shown in Figure 72, along with an alignment method using the handler. An LC circuit is partially formed in the handler. Note the open circuit. The layer includes a conductor matching the open circuit region, which serves as the alignment mark. The layer including the matching alignment conductor is handled as is known in the handler art. The device layer is fed RF signals from the open LC circuit in the handler. When the devices are near alignment, RF excitation increases, and generally reaches a maximum at the aligned position, Le., the LC circuit is completely closed. The handler device bears the open LC circuit in the present embodiment using the hybrid handler/LC aligner, and the device layer closes the circuit with the conductor.

[0347] Referring to Figure 73, various conductor patterns (and accordingly varied hybrid handler/LC aligner systems, not shown) may be provided for sub-micron or nano-scale alignment. [0348] A problem that others encounter, particularly with wafer scale stacking and integration, relates to useful device yield. Herein, this is overcome by suitable diagnostic operations after dicing and sorting, based, e.g., on the number of functioning layers. This method may allow yields approaching 100%. [0349] The method may advantageously be applied to vertically integrated circuits and other vertically integrated devices formed by the processes described hereinabove, or other suitable processes that may achieve high quality alignment.

[0350] The method includes: providing a plurality of vertically integrated devices having unknown device health status (generally in the form of "blanks" ready for vending, but having interconnection wiring and substantially ready for, e.g., microprocessing, modular processing, bit sliced processors, parallel processors or storage applications); performing diagnostics on the vertically integrated devices; and sorting the vertically integrated devices based on the number of known good layers. [0351] In other embodiments, the method comprises sorting a plurality of vertically integrated devices on a wafer, e.g., prior to forming vertically integrated device die. Accordingly, diagnostics may be performed on one or all devices on the wafer. The wafer stacks then may be sorted based on various conditions. For example, in one embodiment, the wafer stacks may be sorted based on how many vertically integrated devices (to be subsequently diced) of the wafer stack have a predetermined number of known good layers. In another embodiment, the wafer stacks may be sorted based on the minimum number of known good layers of all of the devices populated on the wafer stack. [0352] The devices or wafer stacks may be provided by one or more of the processes described herein, or alternatively by other known methods of forming vertically integrated devices. The methods herein are preferred in certain embodiments for various reasons. The edge interconnects of the present methods allow for external diagnostic procedure. [0353] By stacking and dicing vertically integrated devices on a wafer level, economies of scale may be taken advantage of. The present methods also facilitate redundancy of connection. [0354] During diagnostics, known diagnostic methods may be used to determine how many layers of a device are good. Based on the number of good layers, the vertically integrated devices are sorted or categorized into bins corresponding with a numerical range of good layers. Alternatively, or in combination, the vertically integrated devices may be sorted or categorized based on device speed. The different bins thus represent product that is suitable for different users.

[0355] For example, and referring to Figure 74, assume the goal is to achieve 1000 stacked layers on a wafer scale of a wafer producing 500 die. Bins are provided for those with 1000 known good layers; 500 known good layers; 250 known good layers; 100 known good layers; 50 known good layers; and 1 known good layer.

[0356] Further, assume that only 10% of the die meet the standards for the 1000 stacked layers. These are sorted into "1000" bin. Obviously, these are the most expensive die stacks, having the desired number of layers. Still further, assume that 10% of the die have greater than 900 but less 1000 known good layers. These are sorted in the "500" bin. Of the 80% remaining, assume 40 % are between 500 and 900 known good layers. These also go in to the "500" bin. Note that, of course, the levels for each bin may vary depending, for example, on the demands of the customers. Assume 20% have between 250 and 499 known good layers. These go to the "250" bin. Further, assume 10% have between 100 and 249 known good layers, 5% have between 50 and 99 known good dies and the remaining 5% have between 1 and 49 known good dies, which are sorted to the "100" bin, the "50" bin and the "1" bin, respectively.

[0357] Each of the bins being priced accordingly, and demand should exist for each of the various die with a certain number of known good layers. Thus, the commercial yield may be extraordinarily high. [0358] Still using the above example, assume that a customer specifies at least 100 known good layers. Any of the die stacks in the "100" bin are suitable. Alternatively, and referring to Figure 75, a device with 259 layers may be sliced horizontally to form one stack of 135 layers and another stack of 124 layers. The cut may be generally in the x-y plane to reduce the z dimension of the stack. In a preferred embodiment, the cut is formed at one of the known bad die layers to minimize waste.

[0359] In another example, and referring to Figure 76, assume a customer specifies a device with 200 operable layers. A stack of 110 known good die and a stack of 95 known good die may be vertically stacked together in the z direction to form a device having 205 known good layers. Of course, it is contemplated that more than two die stacks may be stacked. Accordingly, in manufacturing it is possible to take from one bin to fix a die that is lacking a full stack.

[0360] Referring to Figure 77, it is also possible to edge stack the die stacks. This is operably provided herein with the plural edge connectors, generally as described above. [0361] In a further embodiment, after diagnostics and prior to stacking, one layer or a portion of one layer may serve to stores health or test result information. Further, programming and addressing functionality may also be provided in the stacked die. Note that when these are stacked, two layers are used for the health or test result information, although it is contemplated that these may be reprogrammed with updated health and status information. This method is advantageously useful when the layers are identical layers.

[0362] A statistical analysis, will describe the merits of the yield increase of the present invention. Assuming that the yield of each good die on a wafer is a constant p, which may vary from 0.7 to 0.99, depending on the fabrication process, as shown in Figure 78. Assuming we desire a stack N=20 wafers together, and the stack is diced, the probability of having k good dies in each diced unit is given in Figure 79. Cumulative error is preferably eliminated, e.g., by using various alignment techniques described herein (e.g., with reference to Figure 68).

[0363] While not wishing to be bound by theory, the herein system should follow the binomial probability mass function:

JPk_ftn) = ( ^* } (pf (1 -pγ^»→ for . =0,1,2, — ,«

where

and wherein x = the number of succession (the number of good layers), n = the number of trials (total stacked layers), and p = the probability of success of a single trial (the probability of all die on a layer to be good).

[0364] Clearly, when the yield p is close to 1, the distribution will be closing to a delta function as expected. As the yields becomes lower, the mean (peak) of the probability distribution moves to lower k, so that the yield to have 20 good dies in each unit is getting lower. Figure 3 shows statistical distribution results for stacking 200 layers with varying the p. A similar behavior on the statistical distribution is verified. The only difference is the overall probabilities are lower than the previous case, as expected.

[0365] Further provided is a method to achieve a desired number of good layers, such as 20 good layers or even 25, 35, and 40 good layers in each stacked unit, without losing any good dies. One approach is to stack two units randomly together as shown in Figure 81. The probability distributions to have 20, 25, 30, 35, and even 40 good dies in one device unit are shown in Figure 82, where the yield of good die on each wafer p varies from 0.7 to 0.99. [0366] In a preferred embodiment, the vertically integrated device use periphery interconnection. Thus, the probability of having 20-good-die (layer) device unit is about 100% in the whole range. If the manufacture yield of good die is about 90%, the yield to have 30 good die device unit is still near 100%. Furthermore, if we test each 20 layer stacked unit and determine the number of good layers in each unit, we can select proper 20 layers stacked units and stack them together to have any numbers of good layers we want in each final product. For example, if we select one unit from such units with 13 good layers and one unit with 17 good layers, and then stack them together, we can have a final product with 30 good layers, as described above with respect to Figures 76 and 77. [0367] Of course, although the described examples are based on stacks of 20 or 200 layers, the number of layers may be increased to over 1000. The same principles will apply. For example, the cut-off points for the number of known good layers is very sharp, as shown, e.g., in Figure 80. IfN were increased to 1000, based on the present invention, the likelihood that only 100 layers would be good is very small. Indeed, the mean number of good layers would be at least between 300 and 600, depending on p, the yield of good die per wafer. Still further, even the stacks with less than an ideal number of good layers may be used by the methods described herein, for example, with respect to Figures 76, 77 and 81. [0368] While preferred embodiments have been shown and described, various modifications and substitutions may be made thereto without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the present invention has been described by way of illustrations and not limitation.

Claims

What is Claimed is;

1. A method of making a thin layer having a useful device therein or thereon comprising providing a device layer on a substrate with a release layer between the device layer and the substrate; forming one or more devices on the device layer; and separating said device layer from said substrate via processing of said release layer while minimizing or obviating damage to said devices formed on said device layer.

2. The method as in claim 1, wherein said release layer comprises a porous release layer.

3. The method as in claim 1, wherein said release layer comprises a layer having sub- regions on the layer varying in directions normal to the plane of the layer, said release layer having a first sub-layer region of relatively large pores proximate the substrate and a second sub-layer region of relatively small pores proximate the device layer.

4. The method as in claim 3, wherein at least a portion of the first sub-layer region is formed on said substrate.

5. The method as in claim 3. wherein at least a portion of said second sub-layer region is grown on said first sub-layer region.

6. The method as in claim 3, wherein at least a portion of said second sub-layer region are converted to single crystalline material when said device layer formed thereon or therein.

7. The method as in claim I₅ wherein said release layer comprises a strained layer.

8. The method as in claim 1, wherein said release layer comprises SiGe.

9. The method as in claim 1, wherein said release layer comprises a thermal strain layer.

10. The method as in claim 1, wherein said release layer comprises a layer having sub- regions on the layer varying in directions parallel to the plane of the layer including a weak bond sub-region and a strong bond sub-region, wherein weak bond sub-regions are at locations where useful structures will be formed.

11. The method as in claim 1, wherein said release layer is formed by selectively creating strong bond sub-regions and weak bond sub-regions varying in directions parallel to the plane of the layer; creating devices on or within said device layer, said devices corresponding to said weak bond sub-regions.

12. The method as in claim 10, said weak bond sub-regions includes sub-sub-regions varying in directions normal to the plane of the layer, said sub-sub-regions including a first sub-sub-region of relatively large pores proximate the substrate and a second sub-sub-region of relatively small pores proximate the device layer.

13. The method as in claim 10, wherein said weak bond sub-regions comprises a strained region.

14. The method as in claim 10, wherein said weak bond sub-regions comprises SiGe.

15. The method as in claim 10, wherein said weak bond sub-regions comprises a thermal strain layer.

16. The method as in claim 11, said weak bond sub-regions includes sub-sub-regions varying in directions normal to the plane of the layer, said sub-sub-regions including a first sub-sub-region of relatively large pores proximate the substrate and a second sub-sub-region of relatively small pores proximate the device layer.

17. The method as in claim 11, wherein said weak bond sub-regions comprises a strained region.

18. The method as in claim 11, wherein said weak bond sub-regions comprises SiGe.

19. The method as in claim 11, wherein said weak bond sub-regions comprises a thermal strain layer.

20. A method of making a thin layer having a useful device therein or thereon comprising providing a single crystalline material substrate with a release layer between the device layer and the substrate; forming a porous sub-region on a surface of the substrate and leaving a sub-region of single crystalline material; growing a device layer atop the porous sub-region and the sub-region of single crystalline material; forming one or more devices on the device layer; removing the device layer atop the sub-region of single crystalline material and the sub-region of single crystalline material; processing at least a portion of the porous sub-region to facilitate separation of the remainder of said device layer.

21. The method as in claim 20, wherein the porous sub-region includes a region of first porosity adjacent the device layer and a region of second porosity, wherein processing comprises removing at least a portion of the region of second porosity.

22. A method of making a thin layer having a useful device therein or thereon comprising providing a device layer on a substrate with a release layer between the device layer and the substrate to form an intermediate structure; forming one or more regions of strong bonding at an edge of the intermediate structure thereby providing structural support thereto; and forming one or more devices on the device layer; and separating said device layer from said substrate via processing of strong bond regions and said release layer while minimizing or obviating damage to said devices formed on said device layer.

23. The method as in claim 22, wherein the one or more regions of strong bonding comprises grown Si.

24. The method as in claim 22, wherein the releasable layer comprises a strained material layer.

25. The method as in claim 22, wherein the releasable layer comprises a porous layer

26. The method as in claim 22, wherein the one or more regions of strong bonding span the device layer, the release layer and the substrate at the edge of the intermediate structure.

27. The method as in claim 22, wherein said release layer comprises a porous release layer.

28. The method as in claim 22, wherein said release layer comprises a layer having sub- regions on the layer varying in directions normal to the plane of the layer, said release layer having a first sub-layer region of relatively large pores proximate the substrate and a second sub-layer region of relatively small pores proximate the device layer.

29. The method as in claim 28, wherein at least a portion of the first sub-layer region is formed on said substrate.

30. The method as in claim 28, wherein at least a portion of said second sub-layer region is grown on said first sub-layer region.

31. The method as in claim 28, wherein at least a portion of said second sub-layer region are converted to single crystalline material when said device layer formed thereon or therein.

32. The method as in claim 22, wherein said release layer comprises a strained layer.

33. The method as in claim 22, wherein said release layer comprises SiGe.

34. The method as in claim 22, wherein said release layer comprises a thermal strain layer.

35. The method as in claim 22, wherein said release layer comprises a layer having sub- regions on the layer varying in directions parallel to the plane of the layer including a weak bond sub-region and a strong bond sub-region, wherein weak bond sub-regions are at locations where useful structures will be formed.

Ill

36. The method as in claim 22, wherein said release layer is formed by selectively creating strong bond sub-regions and weak bond sub-regions varying in directions parallel to the plane of the layer; creating devices on or within said device layer, said devices corresponding to said weak bond sub-regions.

37. The method as in claim 35, said weak bond sub-regions includes sub-sub-regions varying in directions normal to the plane of the layer, said sub-sub-regions including a first sub-sub-region of relatively large pores proximate the substrate and a second sub-sub-region of relatively small pores proximate the device layer.

38. The method as in claim 35, wherein said weak bond sub-regions comprises a strained region.

39. The method as in claim 35, wherein said weak bond sub-regions comprises SiGe.

40. The method as in claim 35, wherein said weak bond sub-regions comprises a thermal strain layer.

41. The method as in claim 36, said weak bond sub-regions includes sub-sub-regions varying in directions normal to the plane of the layer, said sub-sub-regions including a first sub-sub-region of relatively large pores proximate the substrate and a second sub-sub-region of relatively small pores proximate the device layer.

42. The method as in claim 36, wherein said weak bond sub-regions comprises a strained region.

43. The method as hi claim 36, wherein said weak bond sub-regions comprises SiGe.

44. The method as in claim 36, wherein said weak bond sub-regions comprises a thermal strain layer.rocessing the region of second porosity.

45. A method of making a thin layer having a useful device therein or thereon comprising providing a device layer on a substrate to form an intermediate structure; forming one or more regions of strong bonding at an edge of the intermediate structure thereby providing structural support thereto, or forming one or more regions of strong bonding intermediate the device layer and the substrate; and forming one or more devices on the device layer; and separating said device layer from said substrate via processing of strong bond regions and said release layer while minimizing or obviating damage to said devices formed on said device layer.

46. A structure comprising a device layer bonded to a substrate with regions of weak bonding and regions of strong bonding, wherein devices are formed at device regions of the device layer that are weakly bonded to the substrate, further wherein interconnection regions are provided at weakly bonded regions, said interconnect regions structurally interconnecting one or more device regions.

47. A method to form a structure having a first layer removable from a second layer, the first layer removable in a manner so as not to substantially cause detriment to structures formed on said first layer, the method comprising: selectively bonding a first layer to a second layer, wherein selective bonding comprises forming strong bond regions and weak bond regions, said weak bond regions forming a pattern of device regions corresponding to structures to be formed, and connecting regions between said device regions, and forming structures in or about weak bond regions.

48. A method to form a plurality of useful structures on a thin layer comprising providing a structure having a first layer removable from a second layer; selectively bonding the first layer to the second layer, wherein selective bonding comprises forming strong bond regions and weak bond regions between said first layer and said second layer, said weak bond regions forming a pattern of device regions corresponding to structures to be formed, and connecting regions between said device regions; forming structures on or in the first layer at locales corresponding to the device regions; separating said first layer from said second layer by applying detrimental separation processing substantially to the strong bond regions; wherein portions of said first layer including device regions and connecting regions are removed from said second layer; and wherein detriment to structures formed on said first layer is minimized or eliminated.

49. The method as in claim 47, further wherein said pattern of weak bond regions and strong bond regions includes a peripheral connecting region.

50. The method as in claim 48, further wherein said pattern of weak bond regions and strong bond regions includes a peripheral connecting region.

51. The method as in claim 50, wherein said peripheral connecting region is removed during separating step.

52. A method of making a vertically integrated device comprising: providing a first multilayer structure comprising a first substrate, a first mechanically weak layer and a first material layer; providing a second multilayer structure comprising a second substrate, a second mechanically weak layer and a second material layer; bonding the first structure to second structure; detaching the first substrate from the first weak layer; removing the remnants of the first weak layer; making a device structure in the first material ; detaching the second substrate from the second weak layer; optionally removing the remnant of the second weak layer; bonding the first and the second material layers to form a first device layer to a third substrate; preparing the first and the second substrate for reuse; repeating the above steps to make a second device layer; and making a multi device-layer structure by aligning and bonding the second device layer to first device layer;

53. A method of making a vertically integrated device comprising: providing a structure A with 3 layers IA₅ 2A, 3A, wherein layer 2A is a release layer such that a layer lA is releasable from a substrate layer 3 A; making a device A on layer IA; separating device layer IA; providing a structure B with layers IB, 2B, 3B, wherein layer 2B is a release layer and a layer IB is releasable from a substrate layer 3B; making a device B on layer IB; releasing device layer IB; and aligning and bonding layers IA and IB.

54 The method as in claim 53, further comprising: providing a structure C with layers 1C, 2C, 3C, wherein a layer 2C is a release layer and a layer 1C releasable from a substrate layer 3C making a device C on layer 1C; releasing device layer 1C; bonding layer 1C to bonded layers IA and IB.

55. The method as in claim 53, further comprising reusing layer 3A and/or layer 3B.

56. A method of making a vertically integrated device comprising: forming a first multi-device layer structure including providing a structure A with 3 layers IA, 2A, 3A, wherein layer 2A is a release layer such that a layer IA is releasable from a substrate layer 3A; making a device A on layer IA; separating device layer IA; providing a structure B with layers IB, 2B, 3B, wherein layer 2B is a release layer and a layer IB is releasable from a substrate layer 3B; making a device B on layer IB; releasing device layer IB; and aligning and bonding layers IA and IB; and forming a second multi-device layer structure including providing a structure C with 3 layers 1C, 2C, 3C, wherein layer 2C is a release layer such that a layer 1C is releasable from a substrate layer 3C; making a device C on layer 1C; separating device layer 1C; providing a structure D with layers ID₅ 2D, 3D, wherein layer 2D is a release layer and a layer ID is releasable from a substrate layer 3D; making a device D on layer ID; releasing device layer ID; and aligning and bonding layers 1C and ID; and aligning and bonding layers 1A/1B with layers 1C/1D.

57. A first device layer bonded to a second device layer, wherein said first device layer and said second device layer each having a plug-filled contact region, further wherein said plug-filled contact regions include mating conductive contacts.

58. A method of making a vertical integrated device comprising: forming a first device layer on a base layer; forming a tapered aperture with a bottom surface and aperture wall surfaces, defining plateau surfaces proximate a top of the aperture; metallizing at least a portion of the plateau surfaces, at least a portion of the aperture wall surface, and optionally at least a portion of the bottom surface; filling said tapered aperture with a fusible material; additionally forming a second device layer on said first layer; forming a second tapered aperture with a bottom surface and aperture wall surfaces; defining plateau surfaces proximate a top of the aperture; metallizing at least a portion of the plateau surfaces, at least a portion of the aperture wall surface, and at least a portion of the bottom surface; aligning the metallized plateau surface of the first tapered aperture with the metallized bottom surface of the second tapered aperture; filling said second tapered aperture with a fusible material; wherein the second tapered aperture is formed on said first layer prior to the fusible material being fused.

59. The method as in claim 58, wherein fusing the fusible material of the first layer and the second layer is performed in one fusing step.

60. The method as in claim 58, wherein the second tapered aperture is formed on said first layer after the fusible material of the first layer has been fused.

61. The method as in claim 58, wherein fusing the fusible material of the first layer and the second layer is performed in separate fusing steps

62. The method as in claim 58, wherein said metallization plateau surface of the first layer and/or the second layer extends to an edge of the device in a position for edge connection to a vertically integrated layer.

63. The method as in claim 58, wherein said base layer may be device layer below or support layer

64. The method as in claim 58, wherein said fusible material comprises a meltable material

65. The method as in claim 58, wherein said fusible material comprises a sinterable material

66. A method of forming a vertically integrated device including a shielding layer comprising: providing a structure A with layers IA, 2A, 3A, wherein layer 2A is a release layer and layer IA is releasable; making device A on layer IA; releasing device layer IA; providing a structure B with layers IB, 2B, 3B, wherein 2B is release layer and layer IB releasable; forming a shielding device B on layer IB; releasing device layer IB aligning and bonding layers IA and IB.

67 A device comprising a first structure to be edge interconnected to a second structure in a vertically integrated manner, wherein at least the first structure has a thickness and an area, including; a metallization region having a thickness and area less then the thickness and area of the structure; a doped region having a thickness and area greater then the thickness and area of the metallization region and less then the thickness and area of the structure.

68. A method of making an edge connected device comprising: providing a device layer having one or more useful device regions doping a region of one or more useful device regions metallizing within the doped regions.

69. A method of making an edge connected device comprising: providing a device layer having one or more useful device regions metallizing a region within one or more useful device regions doping a region surrounding the metallized region

70. The method as in claim 68, wherein doping is at an edge of the useful device region hi position for edge interconnect.

71. The method as in claim 69, wherein doping is at an edge of the useful device region in position for edge interconnect.

72. A method of making an edge connected device comprising providing a first device layer having one or more useful device regions on an intermediate substrate with a release layer therebetween doping a region of one or more useful device regions of the first layer; metallizing within the doped regions of the first layer; providing a second device layer having one or more useful device regions on an intermediate substrate with a release layer therebetween, the one or more useful device regions of the first layer in positions corresponding to one or more useful device regions of the second layer; doping a region of one or more useful device regions of the second layer; metallizing within the doped regions of the second layer; stacking the first and second device layer and aligning the one or more useful device regions having doped regions with metallization of the first layer with the one or more useful device regions having doped regions with metallization of the second layer.

73. The method as in claim 72, wherein doping is prior to metallizing.

74. The method as in claim 72, wherein metallizing is prior to doping.

75. A method forming a device layer comprising: forming a device layer having one or more useful devices or useful structures thereon or therein; said one or more useful devices or useful structures having at least one conductor associated therewith; and forming oversized conductor regions in electrical contact with said conductors of said devices.

76. The method as in claim 75, wherein said conductor is positioned for edge interconnection of said useful device.

77. A method forming a device layer on a substrate comprising forming a device layer having one or more useful devices or useful structures thereon or therein upon a substrate separated by a release layer; said one or more useful devices or useful structures having at least one conductor associated therewith; forming oversized conductor regions in electrical contact with said conductors of said devices; separating said device layer having oversized conductor regions from said substrate by separation processing all or a portion of said release layer.

78. The method as in claim 77, wherein said conductor is positioned for edge interconnection of said useful device.

79. A method forming a vertically integrated device comprising: forming a first device layer having one or more first useful devices or useful structures thereon or therein; said one or more first useful devices or useful structures having at least one conductor associated therewith; forming oversized conductor regions in electrical contact with said conductors of said first devices; forming a second device layer having one or more second useful devices or useful structures thereon or therein; said one or more second useful devices or useful structures having at least one conductor associated therewith; stacking, aligning and bonding said second device layer to said first device layer having oversized conductor regions.

80. The method as in claim 79, wherein said conductor of said first useful devices or useful structures and said conductor of said second useful devices or useful structures are positioned for edge interconnection of said useful devices.

81. The method as in claim 79, further comprising forming a third device layer having one or more third useful devices or useful structures thereon or therein.

82 The method as in claim 81, said one or more third useful devices or useful structures having at least one conductor associated therewith.

83. The method as in claim 79, wherein forming the oversized conductor regions on the first device layer and forming the oversized conductor regions on the second device layer are performed using the same mask.

84. The method as in claim 79, further comprising dicing individual stacks of devices from said stack of device layers.

85. The method as in claim 84, further comprising edge connecting said conductors of said first device and said second device.

86. The method as in claim 79, wherein oversized conductor regions minimize failed connections due to misalignment.

87. The method as in claim 79, said forming comprising processing said conductor regions directly upon said device.

88. The method as in claim 79, said forming comprising stacking a layer comprising oversized conductor regions.

89. A method for making a layer having an insulated conductive region comprising: providing a layer having a first surface and a second surface; coating first regions of said first surface of said layer with a metal; said metal capable of thermo-electric migration at least partially through said layer and optionally to said second surface; applying electric field and heat, wherein the metal at the first region migrates at least partially through the layer, optionally to said second surface, further wherein portions of the layer corresponding to the first regions are conductive regions through the portion of the layer.

90. The method as in claim 89, further comprising coating second regions with a metal, which may be the same or different material than the metal of the first regions, wherein the metal at the first region and second region migrates at least partially through the layer, optionally to said second surface.

91. The method as in claim 89, wherein portions of the layer corresponding to uncoated regions remain insulative relative said conductive volumes.

92. A layer comprising one or more first conductive regions through said layer in the thickness direction, each said first conductive region encompassed by an insulative region through said layer in the thickness direction, and second conductive regions are provided between said insulative regions.

93. The layer as in claim 92, wherein said first conductive regions comprise shielded via interconnects.

93. The layer as in claim 92, wherein said second conductive regions comprise dissipation surfaces.

94. A method of making a vertically integrated device comprising: providing structure A with 3 layers 1A,2A, 3A, wherein 2A is a release layer such that layer IA is releasable; forming a device A on layer IA; releasing device layer IA; providing a structure B with layer IB, 2B, 3B, wherein 2B is release layer and layer

IB releasable; forming a dedicated wiring connection device B on layer IB; releasing device layer IB aligning and bonding layers IA and IB; and connecting layer IA to the wiring connection device B.

95. The method as in claim 94, further comprising aligning and bonding one or more additional device layer.

96. The method as in claim 95, said additional device layers connected to said wiring connection device B.

97. A crossbar switch comprising a stack of N switching trees each switching tree formed on a device layer and having u inputs and v outputs, wherein u=l, v=2^Λn, wherein n is number of stages and switching tree comprises binary switching elements, said N switching trees are separate from one another, whereby N uX v crossbar switches are provided, whereby activation of certain switches opens a signal path between one of u inputs and one of v outputs, or vice versa if a signal is in a reverse direction.

98. A system comprising a first stack of N uXv switching trees a second stack of N uXv switching trees wherein the first stack and the second stack are interconnected such that said v outputs (or inputs depending on signal direction) of said first stack correspond to one of said N layers of said second stack.

99. A vertically integrated device system comprising a first vertically integrated device (VID) operably coupled to a second vertically integrated device (VID), wherein said first VID is operably coupled to said second VID by an intermediate wiring layer and/or buffer layer and/or amplifier layer and/or shielding layer and/or cooling channel parallel to stack layers.

100. The system as in claim 99, wherein at least one of said first or second VID include an edge layer comprising wiring layer and/or buffer layer and/or amplifier layer and/or shielding layer and/or cooling channel.

101. The system as in claim 99, wherein the first and second VID are on same plane.

102. The system as in claim 101, wherein the intermediate wiring layer and/or buffer layer and/or amplifier layer and/or shielding layer and/or cooling channel are provided orthogonal to VID layers.

103. The system as in claim 101, wherein the first and second VID top or bottom surface spanning layer include wiring layer and/or buffer layer and/or amplifier layer and/or shielding layer and/or cooling channel.

104. The system as in claim 99, wherein the first and second VID are orthogonal.

105. The system as in claim 104, wherein intermediate wiring and/or buffer and/or amplifier and/or shielding and/or cooling channel span edges of first and second VED 105. The system as in claim 104, wherein an edge layer includes wiring layer and/or buffer layer and/or amplifier layer and/or shielding layer and/or cooling channel spanning edge of the first VID and a layer of the second VID.