TW200403962A - Wiring substrate and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a wiring substrate and manufacturing method thereof. It is to provide a wiring substrate without short-circuit, having low-resistance and narrow pitch, and manufacturing method thereof. The wiring substrate of the present invention is to etch the conductor layer 1A, 9 on the insulation layer 6 of the said substrate 1 or on the substrate 1 to obtain the electrode patterns 3, 14, the conductor is passivated by the electrolyte coated film to form the wiring pattern 4, 10. Its cross section is formed to have a width Wm1a wider than the width Wb1a of the contact portion of the insulation layer 6 or the substrate 1, and the width Wt1a of the end part on the opposite side. The manufacturing method of the present invention comprises: the process to etch the conductor 1A, 9 into the electrode patterns 3, 14 with the shape of cross section roughly like a plateau; the process of working on the said electrode patterns 3, 14 by soft etching, so that the electrode patterns 3, 14 have a width wider than the width Wb1 of the contact portion of the insulation layer 6 or the substrate 1, and the width Wt1 of the end part on the opposite side.

Description

200403962 (1) (ii) Description of the invention [Technical field to which the invention belongs] The present invention relates to a wiring template, particularly a wiring board having a narrow-pitch wiring pattern and a method for manufacturing the same. [Prior art] Wiring substrates with a wire pattern using a small motor and wiring boards such as BGA (Ball Grid Array) templates with wiring patterns for 1C are required to be formed at a higher density. Wiring pattern. In order to meet these requirements, conventionally, only a method of forming a wiring pattern formed on these wiring substrates by a plating film has been reviewed. One example is disclosed in Japanese Unexamined Patent Publication No. 6-350 0 224 (hereinafter, referred to as conventional example 1). This is as shown in FIG. 5. After the protective layer 10 02 is applied to the surface of the thin metal plate 101 except for the circuit portion, and the unpatterned portion is formed with a wiring pattern 103 having a predetermined thickness by copper plating, The metal thin plate 101 is removed to form a circuit board. By this method, even if the conductor pattern pitch P will be narrow, a wiring substrate with a low-resistance wiring pattern 103 can be obtained. In addition, other examples are disclosed in Japanese Patent Publication No. 7-9950 (hereinafter referred to as conventional example 2). This is a so-called subtraction method in which the copper film on the surface of the copper substrate 1 1 1 is removed by etching, as shown in FIG. 6, and the etching is over-etched to form a mountain shape or (2) (2) 200403962 Basic wiring pattern 1 1 2 having a slightly I-shaped cross-sectional shape. In addition, it is a wiring board in which a wiring pattern 1 1 3 having a predetermined cross-sectional shape is formed by coating a copper layer with an electrolytic plating film around the basic wiring pattern 112. Also by this method, a wiring board having a low-resistance wiring pattern 1 1 3 can be obtained from a high density. [Summary of the Invention] (Problems to be Solved by the Invention) However, when the wiring density is increased by narrowing the wiring pattern, it is important to narrow the interval between adjacent wiring patterns and reduce the resistance of the wiring pattern. . However, in the conventional example 1, in the cross-sectional shape of the wiring pattern 103, the protective layer 102 is embedded in the inner portion of the wiring pattern 103, that is, the projection of the pattern width W103 on the surface occupied by the surface of the metal sheet 101. The area has a space 102A that cannot be used as a conductor in the thickness direction. In addition, the formed pattern also has a slightly semicircular cross section. Therefore, the cross-sectional area occupied by the pattern in which the effective cross-sectional area of the pattern width W1 03 and the pattern height H1 03 is superimposed is only about 60%, and the so-called narrow-pitch low resistance has its limitation. . Further, since the protective layer 102 is a base after removing the thin metal plate 101, and it is necessary to ensure the strength, there is a problem that it is not easy to reduce the protective layer 102, and there is a limit in narrowing the pitch of the wiring pattern 103. On the one hand, although the conventional example 2 is over-etched, the amount of etching varies in the moment of the excessive worm (3) (3) 200403962, so the protective layer 1 1 4 needs to be coated with excess The width W 5 has a problem that the so-called narrow pitch of the wiring pattern 3 has a limit. In addition, the outline 1 15 on the substrate of the basic wiring pattern 1 12 formed by the etching cannot be linearly formed due to the etching residue. Therefore, as shown in the three-dimensional cross-section of the conventional example 2 in FIG. 7, the basic wiring pattern 1 1 2 is formed by coating the copper layer to form a wiring pattern. The contour on the substrate surface cannot be linear, In addition, the interval between adjacent patterns cannot be made constant, and particularly in the case of a narrow pitch, a connecting portion U 6 that connects adjacent patterns to each other is formed. In addition, since the connecting portion 1 16 shorts the circuit here, in order to prevent the occurrence of the connecting portion 1 16, it is necessary to have an excessive pattern pitch, and it has become difficult to narrow the pitch. Therefore, the problem of the present invention is to provide a wiring substrate with low resistance and a narrow pitch without causing short-circuit defects and a manufacturing method (means for solving the problem). In order to solve the above problems, the present invention has the following means. That is, the scope of application for the first item of the patent is a wiring board formed on an electrode pattern patterned by etching a conductor layer formed on a substrate or an insulating layer of the aforementioned substrate, and forming an electrode pattern by coating the conductor with an electrolytic plating film. A wiring substrate forming a wiring pattern in a predetermined longitudinal cross-sectional shape is characterized in that the predetermined longitudinal cross-sectional shape of the wiring pattern is that the wiring pattern is formed to have a contact that is in contact with the substrate or the insulating layer 200403962 ⑷ The width of the portion is larger than the width of the opposite end portion of the aforementioned contact portion. The second aspect of the patent application, such as the wiring substrate of the first aspect of the patent application, includes an insulating layer formed on the aforementioned wiring pattern ', and a conductive layer is laminated on the insulating layer to form a multilayer structure. The scope of application for patent No. 3, a method for manufacturing a wiring substrate is "coating an electrode pattern patterned by a uranium engraving on a conductor layer formed on a substrate or an insulating layer of the aforementioned substrate" by electrolytic plating. A method for manufacturing a wiring substrate in which a conductor has a wiring pattern having a predetermined vertical cross-sectional shape, comprising: a process of processing the conductive layer into an electrode pattern having a slightly vertical cross-sectional shape by etching; and After that, the vertical cross-sectional shape of the electrode pattern is formed to have a width wider than a width of a contact portion in contact with the substrate or the insulating layer and a width of an end portion on the opposite side of the contact portion by soft etching. The process of processing the aforementioned electrode pattern. The fourth scope of the patent application, such as the manufacturing method of the wiring board of the first scope of the patent application, further comprises: using a sheet-like insulating material that does not include an ink-like insulating material or a glass cloth layer on the wiring pattern. [Formation of Insulating Layer 'Layered by Laminating a Conductor Layer by Coating on the Insulating Layer [Embodiment] The wiring substrate of the present invention and a manufacturing method thereof will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing a manufacturing method of an example of a wiring board according to the present invention. -9- (5) (5) 200403962 Fig. 2 is a schematic cross-sectional view of a main part illustrating an embodiment of a wiring substrate of the present invention. Fig. 3 is a vertical cross-sectional view of a main part illustrating an example of a wiring substrate according to the present invention. Fig. 4 is a schematic cross-sectional view illustrating the effect of the wiring substrate of the present invention. Using Figs. 1 (a) to (j), a wiring substrate according to an embodiment of the present invention, and processes including (a) to (i) are described. Its manufacturing process. In this embodiment, the substrate (core material) is a double-sided copper-laminated laminated board (FR-4) 1 having a substrate 1B and a copper layer 1 A with a thickness of 35 μm. In Fig. 1, for simplicity, only one side of the double-sided copper-laminated laminated board is shown. However, a line pattern having the same arrangement is also formed on the opposite side. In addition, the cross section described below means a longitudinal cross section unless otherwise disclosed. Furthermore, in order to show the cross-sectional shape of the wiring pattern, the symbols of each dimension are defined as follows, and the description is added to the symbol (for example, P is Pi, Pia, etc.). P: Pitch between wiring patterns (pattern pitch)

Wb: The cross-sectional shape of the wiring pattern, and the outer shape is the width (bottom width) of the substrate at the contact portion.

Wt: cross-sectional shape of the wiring pattern, width (top width) of the substrate and the opposite end

Wm: The maximum width of the cross-sectional shape of the wiring pattern T: The thickness of the cross-sectional shape of the wiring pattern S: The distance (space) from the adjacent wiring pattern -10- (6) 200403962 Next, each process will be described in order. (1) Process A: Application of the photosensitive protective layer (refer to FIG. 1 (a)) The photosensitive protective layer 2 is applied to a portion of the wiring (including the lead-out wire) on the surface of the double-sided copper-laminated laminated board 1 which is not formed. (2) Process B: Etching (refer to FIG. 1 (b)) The basic wiring pattern is formed by removing the uncoated copper layer 1 A by etching the photosensitive protective layer 2. At this time, the etching is characterized in that the basic wiring pattern 3 is slightly cut on the photosensitive protective layer 2 side to form a narrow and slightly mountain shape. (3) Process C: peeling of the photosensitive protective layer (refer to FIG. 1 (c)) The photosensitive protective layer 2 is removed.详细 The details of the cross section of the basic wiring pattern 3 thus obtained are shown in Fig. 2 (a). This basic wiring pattern 3 is an electrode pattern in which an electrolytic plating film is formed into an electrode in a later process, and its cross-sectional shape is formed into a mountain shape as shown in the following dimensions. P 1 = 1 8 0 β m, S 1 = 1 0 0 β m, W b 1 = 8 0 β m, W t 1 = 6 0 // ni, T 1 = 3 5 // m 4) Process D: Soft Etching (Refer to Figure 1 (d)) A soft etching solution with a sulfuric acid / hydrogen peroxide-based soft etching solution is used for soft etching with an etching amount of about 1 -11-(7) (7) 200403962 V m. This soft etching has a function of making the thin layer portion more etched than the thick interior portion, so that the thin inner portion near the contact portion between the outer shape of the basic wiring pattern 3 and the base IB is cut to form a narrower portion on the inner side. Face 3 A is reversely tilted (refer to Figure 2 (b)). The top portion 3 B is formed on the side of the slightly mountain-like shape and becomes the widest maximum shape there. In addition to the above-mentioned soft uranium etching solution, a persulfuric acid-based soft etching solution may be used. (5) Process E: Electrolytic plating (refer to FIG. 1 (e)) In the copper sulfate coating solution used as the anode, the entire substrate 1 is immersed while applying the basic wiring pattern 3 as a cathode to perform electrolytic plating. The coating conditions are set such that the cathode current density is 3 A / dm2, and the thickness of the wiring pattern after coating is 7 0 // m. The cross-section of the wiring pattern 4 obtained by the electrolytic plating is shown in FIG. 2 (c). The cross-sectional shape of the wiring pattern 4 obtained by this process is a slightly mountain-like shape that narrows the substrate side as shown in the following dimensions. shape.

Pla = 180 β m 'Wmla = 150 β m > Sla = 30 β m ^ WblA = 115 / zm, Wt 1 a = 70 β m > T 1 a-7 2 // m Make the wiring pattern into a single layer In this case, the processes A to E described above are implemented. Finally, a protective layer such as pSR (photosensitive protective layer) 5 is formed on the surface as needed to complete the wiring substrate (see Figure 1 (e 1)). ). -12- (8) (8) 200403962 In the case where the wiring pattern is made in multiple layers, after the process E ', the stacking process F to process I described below are performed and the layers are multilayered. (6) Process F: formation of an insulating layer (refer to FIG. 1 (f)) After the single-layer wiring board obtained by E is subjected to a surface roughening treatment and a blackening treatment, an ink-like insulating material is applied to form an insulating layer. 6. The surface roughening process may be a CZ process. The coating thickness of the insulating layer 6 is 100 / zm from the surface of the substrate 1B. In addition, the insulating material may be an insulating sheet without a glass cloth layer, and the insulating layer may be formed by vacuum lamination. In any case, even if it is formed in a thin layer, it can completely fill a relatively deep and narrow space between wiring patterns. (7) Process G: formation of TH (perforation), LBH (laser perforation), etc. (refer to Figure 1 (g)). TH7 or LBH8 is formed at a predetermined position as required. (8) Process Η: Formation of a second copper layer (refer to Fig. 1 (h)) A second copper layer 9 having a thickness of 35 / zm is formed on the outside of the insulating layer 6 by an electroless plating film and an electrolytic plating film. TH or LBH is made of copper by this coating. (9) Process I ··· Formation of outer layer wiring pattern (refer to Fig. 1 (i)) Processes A to E are performed again, and a second wiring pattern 10 is formed on the outside of the insulating layer 6. -13-

I (9) I (9) 200403962 Through the above processes F to I, the i-th and second wiring patterns 4, 10 which are stacked in two layers are formed. The cross-sectional shape of this second wiring pattern 10 is a slightly mountain-like shape that is narrowed on the substrate side as shown in the following dimensions.

Plb = 180 // m, Wblb = 112 // m, Wtlb = 72 // m,

Wmlb = 153 // m, Tlb = 72 / z m, S 1 b = 2 7 // m After that, ′ can be multi-layered by repeating the same process A to process I. • After forming the wiring pattern of the final layer, if necessary, a protective layer such as PSR (photosensitive protection layer) 5 is formed on the surface to complete a multilayer wiring board (see Figure 1 (j)). -In order to evaluate the effect of reducing the resistance _ of the wiring pattern obtained by the above process, an effective cross-sectional area ratio as shown below was calculated. Specifically, the effective cross-sectional area ratio SY = (SZ / SR) is calculated from the actual cross-sectional area SZ of the wiring pattern and the maximum cross-sectional area SR of the maximum cross-sectional shape of the pattern and the thickness of the pattern. 100. | The effective cross-sectional area ratio SY, the closer it is to 100%, the higher the space utilization ratio of the wiring pattern, which means that the wiring pattern is formed by high density to form a pattern with excellent low resistance. Therefore, the wiring is evaluated. The degree of resistance reduction of the pattern is an effective index. As a result, the cross-sectional areas SZ of the first and second wiring patterns 4, 10 in the examples are 9600 // m2, 1 0000 // m2, and the ideal cross-sectional areas are 10800 // m2, 1 1 3 22 // m2, so the effective sectional area ratio SY is formed with high efficiency of 89% and 88% respectively. -14-200403962 do) Therefore, it can be confirmed that a high-density, non-resistance wiring pattern can be obtained by 'forming a slightly mountain-shaped wiring pattern with narrowed legs by electrolytic plating and soft etching as in Example 倂'. Further, As described above, because the outer shape of the first and second wiring patterns 4, 10 and the contact portion of the base body 1 B or the insulating layer 6 are cut by soft etching (process D), the inside is narrowed by forming The reverse-inclined faces 4A, 10A, so that the etching residues caused by the etching (process B) are removed. Therefore, as shown in the three-dimensional cross section of the wiring pattern of the embodiment shown in FIG. 3, the base 1B or the insulating layer 6 of the first and second wiring patterns 4, 10 is linear, so it can be securely secured. Substrate S, which significantly reduces short circuit failure. Next, a comparison is made between the wiring pattern of the example and the cross-sectional area of the mountain-shaped ridge [J-plane pattern of conventional example 2] in which the width of the wiring pattern in contact with the substrate is the maximum width of the cross-sectional shape. Figure 4 shows the cross-sectional shape of the wiring pattern of the example when the maximum width W b 0 is unified. The cross-sectional shape of the wiring pattern 4 0 A and 4 0B of the conventional example 2 is shown by a solid line. The maximum cross-sectional shape of the cross-sectional shape of the wiring patterns 4 and 10 of the embodiment is not shown at the portion in contact with the substrate, but at the tops 4B and 10B formed on the side of the slightly mountain shape. interval. From this, it can be seen that the cross-sectional areas of the wiring patterns 4, 10 of the example are portions that are almost widened by the area of the range of the spots in the figure.

-15- (11) (11) 200403962 According to the embodiment, even though the space of the adjacent pattern is the same, the cross-sectional area is large, so that a wiring substrate having a wiring pattern with low resistance can be obtained. Conversely, with the same resistance 値, a wiring board with high-density wiring having a narrower pitch than conventional wiring patterns can be obtained. Since the effect of this example was evaluated using a comparative example, it will be described in detail. The wiring board for evaluation was made of one side, two sides, and two sides and four layers, and produced: an embodiment manufactured by the foregoing process, and first and second wirings different from the foregoing embodiments. Method of Forming the Pattern of Comparative Example 2 by the method of forming the laminated insulating layer 6. The method of preparing the comparative example is described below. < Comparative Example 1 > The manufacturing process of the wiring board of Comparative Example 1 is that soft uranium etching is not performed on the process of the example (process F), and the method of forming the insulating layer during lamination is also different. Regarding the latter specifically, although the example is an ink-like insulating material, in Comparative Example 1, a prepreg and a copper foil were laminated by a press-fit punch. ①: In the case where the substrate 1B and the thickness of 35 μm were not formed A portion of the wiring (including lead wires) on the surface of the double-sided copper-laminated laminated board (FR-4) 1 of the copper layer 1A forms an etching protection layer width 2 (see Fig. 8 (a) see -16- (12) 200403962 1 -②: The basic wiring pattern 3 OA is formed by removing the copper layer 1 A where the etching protection layer 2 is not formed by etching (refer to FIG. 8 (b)). At this time, the characteristic of the etching is that the basic wiring pattern is formed. 30A is formed in a narrow and slightly mountain shape which is slightly cut on the side of the photosensitive protective layer 2. 1 -③: The etching protective layer 2 is removed (refer to FIG. 8 (c)).

1 -④: Electrolytic plating is performed by dipping the entire substrate while energizing the basic wiring pattern 30 A as a cathode in a copper sulfate coating solution for the anode (refer to FIG. 8 (d)). Set the conditions as follows: the cathode current density is 3 A / dm2, and the final pattern thickness is 70 // m. The first wiring pattern 40A obtained by the electrolytic plating is formed in a slightly mountain shape as shown in the following dimensions. P2a = l 80 β m, W m 2 a = W b 2 a = 1 5 0 β m, S2a = 3 0 β m, Wt2b = 70 / zm, T2a = 69 / zm 1-⑤: then blackening After that, a 100 μηι

The impregnating material 11 and the copper foil 12 having a thickness of 35 μm are laminated into a substrate by a laminating punch (see FIG. 8 (e)). 1-⑥: The second wiring pattern 40A is formed by performing the above 1-① ~ 1-④ again. The second wiring pattern 40A is formed into a slightly mountain shape as shown in the following dimensions. P2b = 180 // m, W m 2 b = W b 2 b = 1 5 0 // m 'S2b = 30 // m, Wt2b = 70 // m, T2b = 69 / zm -17- (13) ( 13) 200304962 < Comparative Example 2 > The method of forming the wiring pattern of the wiring substrate of Comparative Example 2 is the same as that of Comparative Example 1, and the method of forming the insulating layer during lamination is the same as that of the Example. The details of Comparative Example 2 will be described below using FIG. 9. 2-①: An etching protection layer 2 is formed on a portion of wiring (including lead wires) on the surface of a double-sided copper-laminated laminated board (FR-4) 1 having a substrate 1B and a copper layer 1A with a thickness of 35 μm. Figure 9 (a) reference)

2-②: The copper layer 1 A where the etching protection layer 2 is not formed is removed by etching to form a basic wiring pattern 3 0B (see FIG. 9 (b)). At this time, the etching is characterized in that the basic wiring pattern 30B is slightly cut on the side of the etching protection layer 2 to form a narrow mountain shape. 2-③: Remove the etching protection layer 2 (refer to FIG. 9 (c)). 2-④: In the copper sulfate coating solution that serves as the anode, the entire wiring pattern is immersed to apply electrolytic plating while energizing the basic wiring pattern 30 B as a cathode (refer to FIG. 9 (d)). Set the conditions as follows: the cathode current density is 3 A / dm2, and the final pattern thickness is 7 0 // m. The first wiring pattern 40B obtained by the electrolytic plating is formed in a slightly mountain shape as shown in the following dimensions. P3a = 180 β m, Wm3a = Wb3a = 149 β m, S 3 a = 3 1 β m, Wt3a = 70 // m, T 3 a = 7 1 β m 2-⑤: The blackening process is then performed, and thereafter, The ink-like insulating material is applied to form the insulating layer 6. The coating thickness is 100 μm from the surface of the substrate 1B -18- (14) 200403962 2-⑥: The second copper layer 9 with a thickness of 3 5 μm is formed on the outside of the insulating layer 6 by an electroless plating film and an electrolytic plating film (No. Figure 9 (e) reference). 2-⑦: Further, the processes ① to 2-④ are performed again to form the second wiring pattern 40B. This second wiring pattern 40B is formed in a slightly mountain shape as shown in the following dimensions.

P3b = 180 // m, Wm3b = Wb3b = 149 / zm, Wt3b = 71 / zm, T3b = 72 // m, S2b = 30 / zm. The wirings of the examples, comparative examples 1 and 2 will be prepared as described above. The specifications of the substrate are summarized in Table 1. [Table 1] Specifications of each wiring pattern: () indicates the total thickness of the soft-etched insulating layer material per unit layer type T (㈣ gap width Wb (// m) maximum width Wm (/ ^ m) top width wt (㈣ space S ( ym) Pitch P (^ m) Example 1 Ink in the first layer 72 115 150 70 30 180 Second layer 74 112 153 72 27 180 Comparative example 1 First layer without prepreg 69 150 150 70 30 180 Second layer 72 148 148 68 32 180 Comparative Example 2 First layer 4χττ That ink-like 71 149 149 70 31 180 Second layer 72 149 149 Ή 30 180

-19- (15) 200403962 < Evaluation > The wiring boards of the above-mentioned Examples, Comparative Examples 1 and 2 were used as test samples, and evaluated by two methods of a hot oil test and a short-circuit failure test. The results are shown in Table 2 and detailed. [Table 2] Occurrence rate of short-circuit failure in the hot oil test of soft-etched insulating layer materials Examples are ink-like good 1% or less Comparative Example 1 钲 prepreg 70 times 80% Comparative Example 2 No ink-like good 80% (A) Hot oil In the test hot oil test, a test sample was immersed in an oil at 260 ° C. for 10 seconds, and then left to stand in air at room temperature for 20 seconds as one treatment, which was performed 1,000 times. Those who remained connected after 1,000 implementations were evaluated as good. As a result, Examples and Comparative Examples 2 obtained good results, but Comparative Example 1 was unable to maintain the connection after 70 times and became defective. This is because in the lamination of the prepreg 11, the prepreg 11 cannot be fully charged in a space between the first wiring pattern 40A in a thickness direction of about 70 μm and a width direction of about 30 μm. As a result, the gap 13 was generated, and in this state, the temperature load was increased, and cracks occurred from the gap 13 to cause interstellar peeling. Therefore, the method for forming an interlayer insulating layer during multi-layering can ensure that I dH -20- (16) 200403962 is sufficient as the material of the insulating layer between the wiring patterns narrowed due to the narrow pitch, rather than using prepreg. It is more effective to use ink-like insulating material or insulating sheet without glass cloth layer, which can make the laminated thickness thinner and higher density. (B) Short circuit bad evaluation

The short-circuit failure evaluation is to measure the inductance of the test product. If there is a difference of 10% or more in the specifications, the evaluation is bad. In addition, an example in which the occurrence rate of the short-circuit failure was 1% or less was evaluated as good. As a result, Examples and Comparative Examples 2 obtained good results, but Comparative Example 1 was 80 ° /. Incidence of adverse effects. This is because, as described above, in the formation of a wiring pattern by etching, an etching residue is generated at the boundary between the pattern and the substrate, and the predetermined space of the adjacent pattern is about 3 0 // m, which is an unsecured portion or connected. The part is produced.

It can be seen that by removing the soft etching remaining from this etching, short-circuit defects can be effectively prevented from occurring in a space of 30m. In short, the embodiment of the present invention is not limited to the above-mentioned structure, and can be changed as follows without departing from the essence of the present invention. The substrate may be a double-sided substrate or a single-sided substrate. Moreover, it may be a single layer or multiple layers, and TH or LBH may be set freely. The photosensitive protective layer, the etchant, and the soft etchant are also not limited, and the etching conditions are set to the optimum conditions according to the use liquid. -21-(17) (17) 200403962 (Effect of the invention) As detailed above, according to the present invention, the cross-sectional shape of the wiring pattern is formed to have a width wider than that of a contact portion where the wiring pattern contacts the substrate or the insulating layer. The width of the end portion on the opposite side of the contact portion is larger, so short circuit defects caused by the etching residues do not occur, and a wiring substrate with a narrower pitch of the wiring pattern can be obtained. In addition, even if the space is the same as the adjacent pattern, the cross-sectional area becomes larger, so that a wiring board having a wiring pattern having a lower resistance can be obtained. On the one hand, after the conductor layer is processed into an electrode pattern having a slightly mountain-shaped cross-sectional shape by etching, the cross-sectional shape of the electrode pattern is wider than that of the contact portion in contact with the substrate or the insulating layer by soft etching. The width of the end portion on the opposite side of the contact portion is processed by digging the portion in contact with the substrate of the electrode pattern or the insulating layer toward the inside. Therefore, the shape of the wiring pattern is formed by the subsequent electrolytic plating. The portion in contact with the substrate or the insulating layer has a narrower cross-sectional shape toward the inside. Therefore, short-circuit defects due to etching residues do not occur, and a wiring substrate with a narrower wiring pattern can be obtained. At the same time, even if the space is the same as that of the adjacent pattern, a lower cross-sectional area can be obtained to obtain a lower resistance. Wiring pattern of the wiring board. Furthermore, in the process of multilayering, a sheet-like insulating material that does not include an ink-like insulating material or a glass cloth layer is applied or vacuum-laminated to form an insulating layer on a wiring pattern, and then a plating film is laminated on the insulating layer by a conductor layer. Since it is formed, it has excellent reliability without generation of gaps, and a multilayer wiring board with a short interlayer distance and high density can be obtained. -22- (18) (18) 200403962 [Brief description of the drawings] [Figs. 1 (a) to (j)] A schematic cross-sectional view showing a manufacturing method of an embodiment of the wiring board of the present invention. [FIGS. 2 (a) to (c)] A schematic cross-sectional view of a main part illustrating an embodiment of a wiring board of the present invention. [Fig. 3] A perspective cross-sectional view of a main part illustrating an example of a wiring board according to the present invention. [Fig. 4] A schematic cross-sectional view illustrating the effect of the wiring board of the present invention. [FIG. 5] A cross-sectional view showing an example of a conventional wiring board. [FIG. 6 (a) (b)] A cross-sectional view showing another example of a conventional wiring board. [FIG. 7] A perspective cross-sectional view illustrating another example of a conventional wiring board. [Figs. 8 (a) to (f)] A schematic cross-sectional view illustrating the manufacturing process of Comparative Example 1. [Fig. [FIGS. 9 (a) to (f)] A schematic cross-sectional view illustrating the manufacturing process of Comparative Example 2. [FIG. [Illustration of drawing number] 1 Copper post laminated board (substrate) 1 A Copper layer (conductor layer) 1B Substrate 2 Photosensitive protective layer-23- (19) 200403962 3, 1 4 Basic wiring pattern (electrode pattern) 3 A Reverse tilted face 3B top 4 (first) wiring pattern 5 solder resist photoresistive protective layer (PSR) 6 insulating layer 7 perforation (TH) 8 laser drilling (LVH) 9 second copper layer (second conductor layer) 10 second wiring Pattern 11 prepreg 12 copper foil 13 clearance -24-

Claims (1)

(1) (1) 200403962 Scope of patent application 1 A wiring substrate is formed by electrode patterns patterned by etching a conductor layer formed on a substrate or an insulating layer of the aforementioned substrate, and covered with an electrolytic plating film. A wiring board having a conductor having a predetermined vertical cross-sectional shape and having a predetermined longitudinal cross-sectional shape is characterized in that the predetermined vertical cross-sectional shape of the wiring pattern is such that the wiring pattern is formed so as to have a contact with the substrate or the insulating layer. The width of the contact portion is larger than the width of the opposite end portion of the contact portion. 2. The wiring board according to item 1 of the application, wherein an insulating layer is formed on the aforementioned wiring pattern, and a conductive layer is laminated on the insulating layer to form a multilayer structure. 3. A method for manufacturing a wiring substrate, in which a conductor layer formed on a substrate or an insulating layer of the aforementioned substrate is patterned by etching on an electrode pattern, and the conductor is coated with an electrolytic plating film to have a predetermined longitudinal section A method for manufacturing a wiring board having a wiring pattern formed in a shape, comprising: a process of processing the conductive layer into an electrode pattern having a slightly mountain-shaped longitudinal cross-sectional shape by etching; and thereafter, performing soft etching A process of processing the electrode pattern in such a manner that a longitudinal cross-sectional shape of the electrode pattern is wider than a width of a contact portion in contact with the substrate or the insulating layer and an opposite end portion of the contact portion . 4. The method for manufacturing a wiring board according to item 3 of the scope of patent application, which comprises: using a non-ink-like insulating material or -25- (2) 200403962 sheet-like insulation on the aforementioned wiring pattern The process of forming an insulating layer using a metal material, and layering a conductive layer on the insulating layer by plating. -26-