201106824 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種C0F(Chip On Fi lm，薄膜覆晶封裳） 薄膜載帶（film carrier tape)等之印刷配線基板及其製造 方法。 【先前技術】 在形成有由絕緣薄膜、黏接劑層及導電性金屬箔所形 成之配線圖案之3層構造式TAB(Tape Automated Bonding、捲帶式自動接合）捲帶或絕緣薄膜上直接形成有 由導電性金屬箔所構成之配線圖案之2層構造式C0F捲帶 等之印刷配線板之輸出側外引腳（outer lead)及輸入侧外 引腳’係例如以異方性導電薄膜（ACF，Anis〇toropicBACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board such as a COF (Chip On Film) film carrier tape, and a method of manufacturing the same. [Prior Art] Directly formed on a three-layer TAB (Tape Automated Bonding) tape or an insulating film formed with a wiring pattern formed of an insulating film, an adhesive layer, and a conductive metal foil An output side outer lead and an input side outer lead of a printed wiring board having a two-layer structure type COF tape or the like having a wiring pattern made of a conductive metal foil are, for example, an anisotropic conductive film ( ACF, Anis〇toropic
Conductive Film)與液晶面板或硬質（rigid)印刷配線板 之電路部電性連接。 近年來，驅動器1C晶片之金凸塊（bump)之微細間距 (fine pitch)化已隨液晶晝面之高精細化發展，而在C0F 等1C安裝用印刷配線板中，亦隨之需形成將内引腳（inner 1 ead)間距細線化為2〇 # ^以下之電路，而15 // m間距亦已 問世。 近年來’藉由半加成（semi_additive)法形成超微細間 距配線圖案之技術已見進步，而可藉由此技術形成Cu等導 體厚度為8 /z m以上，最厚亦只有2〇 v m間距以下的配線圖 案。 此種半加成法係於絕緣體層上形成基底層，接著在基 3 322083 201106824 底層上形成與配線圖案相反之阻劑（resist)圖案之後進行 電鍍，之後，將阻劑剝離再將基底層去除以形成配線圖案 者。 此外，為了解決藉由半加成法之配線在鍍覆層上部未 能形成緻密的結晶構造卻產生微小龜裂（crack)之問題，乃 提出一種在銅鍍覆之間加入濺鍍層而設計成多層以提升緻 密性之方法（參照專利文獻1)。 然而，亦有配線寬度隨著微細間距化而變窄，而使印 刷配線基板上之配線圖案之耐折性有降低傾向之問題。另 外，在專利文獻1之技術中雖未針對此點探討，惟無論如 何都是加入滅鐘層而做成為多層，因此在製造效率方面會 有問題。 [先前技術文獻] [專利文獻] [專利文獻1]日本特開2006-278950號公報 【發明内容】 [發明所欲解決之課題] 本發明係有鑑於上述問題而研創者，其目的在提供一 種具有耐折性優異之配線之印刷配線基板及其製造方法。 [解決課題之手段] 本發明之第1態樣係一種印刷配線基板，係在絕緣基 材表面具有包含基底層、及藉由半加成法在該基底層上形 成之銅鍍覆層的配線圖案者，其特徵為：前述銅鍍覆層係 具有多層構造，且雙晶粒徑未達5 // m。 4 322083 201106824 在此第1態樣中，由於藉由半加成法之銅鍍覆層具有 多層構造’且雙晶粒徑未達5# m，因此配線圖案之耐折性 優異。 本發明之第2態樣係在第1態樣之印刷配線基板中， •前述多層構造之各層厚度為m以下。 在此第2態樣中，多層構造之各層厚度為4ym以下， 而使耐折性更為有效地提升。 本發明之第3態樣係在第丨或第2態樣之印刷配線基 板中，前述鋼鍍覆層之雙晶粒縱橫比係未達〇 45。 在此第3態樣中，銅鍍覆層之雙晶粒縱橫比未達 0.45，而使耐折性更為有效地提升。 本發明之第4態樣係在第丨至第3態樣中任一態樣之 印刷配線基板中’前述多層構造在各層疊層方向下面係設 有以較形成各層時之鍍覆電流密度為低之電流密度所形成 之邊界層。 在此第4態樣中，係藉由隔介邊界層而使鋼鑛覆層更 確實地具有多層構造’而且雙晶粒徑未達。 本發明之第5態樣係在第！至第4態樣中任一態樣之 印刷配線基板中，前述多層構造之各層，其疊層料上側 之層係較下側之層薄。 在此第5態樣中，係藉由將疊層方向上側之層設為較 下侧之層溥，而使耐折性更為有效地提升。 本發明之第6態樣係在第1至第5態樣中任一萍樣之 印刷配線基板中，前述多層構造之疊層方向最上面:㈣ 322083 5 201106824 最薄。 在此第6態樣中，係藉由將多層構造之疊層方向最上 面之層設為最薄，而使财折性更為有效地提升。 本發明之第7態樣係一種印刷配線基板之製造方法， 係在絕緣基材表面形成導電性基底層，且於該基底層表面 形成光阻劑層，並將預定的圖案曝光顯影於該光阻劑層以 進行圖案化，藉以形成使前述基底層露出之凹部，且於該 凹部之基底層上形成銅鍍覆層，之後，將圖案化後之光阻 劑層剝離，接著，將藉由光阻劑層之剝離而露出之基底層 去除而形成配線圖案者，其特徵為：將前述銅鍍覆層之鍍 覆分割為多段進行，前述銅鍍覆層具有多層構造，且雙晶 粒徑係未達5 // m。 在此第7態樣中，係將藉由半加成法之銅鍍覆層作成 多層構造，且使雙晶粒徑未達5//m，藉此即可製造配線圖 案之财折性優異之印刷配線基板。 本發明之第8態樣係如第7態樣之印刷配線基板之製 造方法，其中，在分割為前述多段之鍍覆之間，係以較各 層之鍍覆電流密度為低之電流密度形成邊界層。 在此第8態樣中，係隔介邊界層而作成多層構造，藉 此即可製造銅鍍覆層更確實地具有多層構造，而且雙晶粒 徑未達5//m之印刷配線基板。 【實施方式】 以下說明本發明一實施形態之印刷配線基板及其製造 方法。 322083 201106824 第1圖係顯示作為一實施形態之印刷配線基板之COF 薄膜載帶。 第1圖所示本實施形態之C0F薄膜載帶1，係在由聚 酿亞胺（polyimide)層所構成之絕緣基材上，形成由導 體層所構成之具有所希望圖案之配線圖案20者，而配線圖 案20所具備之配線一般而言係具有作為端子之内引腳 21A、22A及外引腳21B、22B。在C0F薄膜載帶1之絕緣基 材10之寬度方向兩側，一般而言，係形成有鏈齒孔 (sprocket hole)2 ’而在除了配線圖案20之内弓丨腳21A、 22A及外引腳21B、22B以外之區域，係設有阻焊（s〇ider resist)層3，藉以覆蓋配線圖案20。 在此’成為端子部之配線，例如内引腳21A、22A，配 線之間距為30/im以下，較佳為2〇yni以下，線寬為6/zm 以上’較佳為7 # m至15 /z m，線寬間之間隔為15 y m以下， 較佳為13//m以下’配線厚度為6至15//m，較佳為6至 12 // m。 在此，參照圖式具體說明第丨圖之印刷配線基板之製 造方法。 第2圖係為顯示本實施形態之印刷配線基板之製造方 法之各步驟之基板剖面例圖。 如第2圖（a)及⑹所示，在本實施形態之印刷配線基 板之製造方法中’係於絕緣基材1〇之至少一表面形成由導 電性金屬薄層所構成之晶種（咖）層21。在此，絕緣基材 ίο只要是由絕緣性基板所構成之板、薄膜、薄片（sheet)、 322083 7 201106824 預浸材（prepreg)等，可作為通常之絕緣基材使用者均可使 用’並未特別限定。_，為了以捲盤至捲盤（㈣…⑻ 方式連續製造本發明之㈣彳崎隸，舰緣歸1〇係以 具有可撓性為較理想。此外，在製造印刷配線基板之步驟 中由於該絕緣基材10有與酸性溶液或驗性溶液接觸之情 形，故以具有優異耐藥品性者為較理想。再者，由於會有 曝露於高溫下之情形’故以具有優異耐熱性為較理想。此 外’從使用該絕緣基材10並藉由鍍覆步驟來製造配線圖案 而言’係以不會因為與水接觸而變質或變形者為較理想。 從此種觀點而言’以在本發明中所使用之絕緣基材10而 。’係以使用耐熱性之合成樹脂薄膜為佳，尤以使用聚醯 亞胺薄膜、聚醯胺醯亞胺（polyamideimide)薄膜、聚酯 (polyester)樹脂薄膜、氟樹脂薄膜、液晶樹脂薄膜等通常 用於製造印刷配線基板之樹脂薄膜為佳，此等薄膜之中， 又以具有優異耐熱性、耐藥品性、耐水性等特性之聚醯亞 胺薄膜為尤佳。 此外，在本發明中，絕緣基材1〇不需如上所述之薄膜 狀亦可為例如由纖維狀物與環氧（epoxy)樹脂等之複合體 所構成之板狀絕緣基材。 ，在本發明中，於上述絕緣基材10，除鏈齒孔2以外， 尚可晛需要形成折彎用細縫等必要的貫通孔。此等貫通孔 係可藉由衝孔（punching)法、雷射穿設法等來形成。 在本實施形態中，如上所述，係在絕緣基材1〇之至少 一面形成由導電性金屬薄層所構成之晶種層2卜此晶種層 322083 8 201106824 21係為在前述表面藉由電鍍疊層金屬層時形成電極之層， 通常，可藉由鎳、絡、銅、銘、鎳絡合金、Ni-Zn、Ni -Cr-Zn 等金屬或包含此等金屬之合金所形成。此種晶種層21，只 要是在絕緣基材10表面析出如上述之導電性金屬之方 法，則其形成法並無特別限制，惟以藉由濺鍍法形成較為 有利。藉由濺鍍法形成晶種層21，可使被濺鍍之金屬或合 金緊密附著於絕緣基材10表面，而牢固地黏合絕緣基材 10與被濺鍍之晶種層21。因此，在製造本發明之印刷配線 基板之際，不需在絕緣基材10與晶種層21之間設置黏接 劑層。 此外，晶種層2.1之平均厚度通常為10至1000A、較 佳為50至300A之範圍内。 以此方式形成晶種層21之後，係以如第2圖（c)所示 地在此晶種層21表面形成銅薄膜層22，且與晶種層21 — 併組成基底層23為佳。在本發明中，該銅薄膜層22係以 藉由例如藏鍵形成為佳。然而，此銅薄膜層2 2並不限定於 濺鍍，亦可以真空蒸鍍法、無電解鍍覆法等各種方法來形 成，惟作成藉由濺鑛所形成之銅薄膜層時，係可形成黏合 力良好且強度高的銅金屬電路。此銅薄膜層22雖係為以銅 為主成分之層，惟在不損及該層特性之範圍内，亦可含有 銅以外的金屬。此銅薄膜層之平均厚度，通常係為0. 01至 l#m、較佳為0.1至之範圍内。藉由以此種平均厚 度形成銅薄膜層22，即可提升與形成於該銅薄膜層22表 面之藉由半加成法所形成之銅層之親和性。 9 322083 201106824 雖以上述方式在晶種層21上形成銅薄膜層22而作成 基底層23’惟未必需要設置銅薄膜層22,此時，晶種層 21即成為基底層23。 形成基底層23後，雖可直接移至下一個步驟，惟由於 在銅薄膜層22表面會形成有氧化膜等，因此係以藉由硫 酸、鹽酸等強酸將銅薄臈層22表面作短時間酸洗之後，移 至下一個步驟為佳。 在本實施形態中，係於形成基底層23之後，如第2 0 W所示，在該銅薄膜層22表面整面，形成由感光性樹月 所構成之光阻劑層3卜形成該光阻騎3ι之樹脂，雖； 經照射光之部分會硬化㈣溶解於顯影液之負型、及經日 射光之部分會溶解於顯旦彡 ' 感光性樹脂均可使之正型，惟本發明中任何❸ 膜等薄膜狀阻劑作為最層Γ ’不限疋於液狀’亦可使用^ 係疊層負型之乾薄隐劑作為光阻劑層貫施㈣中， 在此，光阻劑層 案20之高度為域佳7度仙作成較欲形成之配線e 至25#m、較佳為13如光阻劑層31之厚度係為 王 W a m。 接著，如第2圖- 形成有所希在絲綱31表面，配】 使光阻劑層31感光 ^並從光罩32上方照射光t 之部分的感光性樹進仃顯影，藉此將形成配線電足 ⑴）。在以此方式所成阻劑圖案33(第2撞 係露出有在上述第案33之凹部咖底部 中所形成之基底層23。 322〇83 201106824 接下來，在本實施形態中，在使基底層23露出之狀態 下，將該基板移至銅電鍍槽，且以基底層23作為一方電 極，並對於與設於鍍覆槽之另一電極之間施加鍍覆電壓以 進行電解鍍覆，而於基底層23表面形成銅鍍覆層24(第2 圖（g))。 在此，電解鍍覆之施加電壓係可為直流電壓，亦可為 脈衝（pulse)電壓，而銅鍍覆層24之厚度，係以設計為較 阻劑圖案33之厚度薄為佳，且以將銅鍍覆層24厚度作成 為阻劑圖案33之一半厚度以下為佳。此係為了順暢進行後 續之阻劑圖案33之剝離的緣故。 在此，以進行電解鍍覆之銅鍍覆液而言，係以使用包 含選自 3-酼基-1-丙確酸（3-Mercapto-l-propanesulfonic acid)(簡稱「MPS」）或雙（3-磺丙基）二硫化物（Bis(3-sulfopropyl)disulfide)(簡稱 SPS)之至少一種、具有環 狀構造之4級氨鹽聚合體、及氣；而銅濃度為23至55g/ L，較佳為25至40g/L，硫酸濃度為50至250g/L，較佳 為80至220g/L為佳。 此係由於藉由使用此種組成之鑛覆液，即可藉由半加 成法尚效率地進行形成配線，而所形成之配線不會有氧化 或形狀異常情形，而使表面成為平坦之故。The conductive film is electrically connected to a circuit portion of a liquid crystal panel or a rigid printed wiring board. In recent years, the fine pitch of the gold bumps of the driver 1C wafer has progressed with the high definition of the liquid crystal surface, and in the printed wiring board for 1C mounting such as C0F, it is necessary to form The inner pin (inner 1 ead) pitch is thinned to a circuit of 2 〇 # ^ and the 15 // m pitch is also available. In recent years, the technology for forming ultra-fine pitch wiring patterns by the semi-additive method has progressed, and the thickness of conductors such as Cu can be formed by this technique to be 8 / zm or more, and the thickest is only 2 〇 vm or less. Wiring pattern. The semi-additive method forms a base layer on the insulator layer, and then forms a resist pattern opposite to the wiring pattern on the underlayer of the base 3 322083 201106824, and then performs electroplating, after which the resist is stripped and the base layer is removed. To form a wiring pattern. In addition, in order to solve the problem that a dense crystal structure is not formed in the upper portion of the plating layer by the wiring of the semi-additive method, a micro crack is generated, and a sputtering layer is added between the copper plating to design A method of improving the compactness by a plurality of layers (refer to Patent Document 1). However, the wiring width is narrowed with the fine pitch, and the folding resistance of the wiring pattern on the printed wiring board tends to be lowered. Further, although the technique of Patent Document 1 is not discussed in this regard, it is problematic in terms of manufacturing efficiency, regardless of the fact that the clock layer is added to be multi-layered. [Prior Art] [Patent Document 1] [Patent Document 1] JP-A-2006-278950 SUMMARY OF THE INVENTION [Problems to be Solved by the Invention] The present invention has been made in view of the above problems, and an object thereof is to provide a A printed wiring board having wiring excellent in folding resistance and a method of manufacturing the same. [Means for Solving the Problem] A first aspect of the present invention is a printed wiring board having wiring including a base layer and a copper plating layer formed on the base layer by a semi-additive method on the surface of the insulating base material. The pattern is characterized in that the copper plating layer has a multilayer structure and the twin crystal grain size is less than 5 // m. 4 322083 201106824 In the first aspect, since the copper plating layer by the semi-additive method has a multilayer structure 'and the twin crystal grain size is less than 5 # m, the wiring pattern is excellent in folding resistance. According to a second aspect of the present invention, in the printed wiring board of the first aspect, the thickness of each layer of the multilayer structure is m or less. In this second aspect, the thickness of each layer of the multilayer structure is 4 μm or less, and the folding endurance is more effectively improved. According to a third aspect of the present invention, in the printed wiring board of the second or second aspect, the double-grain aspect ratio of the steel plating layer is less than 45. In the third aspect, the double-grain aspect ratio of the copper plating layer is less than 0.45, and the folding endurance is more effectively improved. According to a fourth aspect of the present invention, in the printed wiring board according to any one of the second aspect to the third aspect, the multilayer structure is provided in a layered layer direction in a direction in which each layer is formed to have a plating current density. A boundary layer formed by a low current density. In this fourth aspect, the steel ore coating is more surely provided with a multilayer structure by interposing the boundary layer and the twin crystal grain size is not reached. The fifth aspect of the present invention is in the first! In the printed wiring board according to any one of the fourth aspects, each layer of the multilayer structure has a layer on the upper side of the laminate which is thinner than a layer on the lower side. In the fifth aspect, the folding resistance is more effectively improved by setting the layer on the upper side in the lamination direction to the lower layer. According to a sixth aspect of the invention, in the printed wiring board of any one of the first to fifth aspects, the multilayer structure has a stacking direction at the top: (4) 322083 5 201106824 is the thinnest. In the sixth aspect, the layer having the uppermost lamination direction of the multilayer structure is made thinner, and the fiscal property is more effectively improved. A seventh aspect of the present invention provides a method of manufacturing a printed wiring board, wherein a conductive underlayer is formed on a surface of an insulating substrate, and a photoresist layer is formed on a surface of the underlying layer, and a predetermined pattern is exposed and developed on the light. The resist layer is patterned to form a recess for exposing the base layer, and a copper plating layer is formed on the base layer of the recess, and then the patterned photoresist layer is peeled off, and then, by When the photoresist layer is peeled off and the exposed underlying layer is removed to form a wiring pattern, the plating of the copper plating layer is divided into a plurality of stages, and the copper plating layer has a multilayer structure and a twin crystal grain size. The system is less than 5 // m. In the seventh aspect, the copper plating layer by the semi-additive method is formed into a multilayer structure, and the twin crystal grain size is less than 5/m, whereby the wiring pattern can be manufactured with excellent financial properties. Printed wiring board. According to a eighth aspect of the invention, there is provided a method of manufacturing a printed wiring board according to the seventh aspect, wherein a boundary between the plurality of stages of plating is formed by a current density lower than a plating current density of each layer Floor. In the eighth aspect, the boundary layer is formed as a multilayer structure, whereby a copper wiring layer can be manufactured with a multilayer structure and a printed wiring board having a double grain diameter of less than 5/m. [Embodiment] Hereinafter, a printed wiring board and a method of manufacturing the same according to an embodiment of the present invention will be described. 322083 201106824 Fig. 1 shows a COF film carrier tape as a printed wiring board of one embodiment. The COF film carrier tape 1 of the present embodiment shown in Fig. 1 is formed by forming a wiring pattern 20 having a desired pattern composed of a conductor layer on an insulating base material made of a polyimide layer. The wiring included in the wiring pattern 20 generally has the inner leads 21A and 22A and the outer leads 21B and 22B as terminals. On both sides in the width direction of the insulating substrate 10 of the C0F film carrier tape 1, in general, a sprocket hole 2' is formed and the ribs 21A, 22A and the outside are drawn in addition to the wiring pattern 20. A region other than the legs 21B and 22B is provided with a solder resist layer 3 to cover the wiring pattern 20. Here, the wiring to be the terminal portion, for example, the inner leads 21A and 22A, the wiring pitch is 30/im or less, preferably 2 〇 yni or less, and the line width is 6/zm or more, preferably 7 # m to 15 /zm, the interval between the line widths is 15 ym or less, preferably 13//m or less 'the wiring thickness is 6 to 15//m, preferably 6 to 12 // m. Here, a method of manufacturing the printed wiring board of the second drawing will be specifically described with reference to the drawings. Fig. 2 is a view showing an example of a substrate cross section showing each step of the method of manufacturing the printed wiring board of the embodiment. As shown in Fig. 2 (a) and (6), in the method of manufacturing a printed wiring board of the present embodiment, a seed crystal composed of a thin layer of a conductive metal is formed on at least one surface of the insulating substrate 1A. ) Layer 21. Here, the insulating substrate ίο can be used as a general insulating substrate as long as it is a plate, a film, a sheet, a 322083 7 201106824 prepreg made of an insulating substrate. It is not particularly limited. _, in order to continuously manufacture the (4) Miyazaki of the present invention in a reel-to-reel ((4)...(8) manner, it is preferable to have flexibility in the case of the ship. In addition, in the step of manufacturing a printed wiring board, Since the insulating base material 10 is in contact with an acidic solution or an assay solution, it is preferable to have excellent chemical resistance. Further, since it is exposed to a high temperature, it is excellent in heat resistance. Further, it is preferable that 'the use of the insulating substrate 10 and the wiring pattern by the plating step is not deteriorated or deformed by contact with water. From this point of view, 'in this view' The insulating substrate 10 used in the invention is preferably a synthetic resin film using heat resistance, particularly a polyimide film, a polyimideimide film, or a polyester resin. A resin film which is generally used for producing a printed wiring board, such as a film, a fluororesin film, or a liquid crystal resin film, is preferable, and among these films, polyimine which has excellent heat resistance, chemical resistance, water resistance and the like Further, in the present invention, the insulating base material 1 is not required to have a film shape as described above, and may be, for example, a plate-like insulation composed of a composite of a fibrous material and an epoxy resin. In the present invention, in addition to the sprocket hole 2, it is necessary to form a necessary through hole such as a slit for bending, and the through hole may be punched. In the present embodiment, as described above, a seed layer 2 composed of a thin layer of a conductive metal is formed on at least one surface of the insulating substrate 1A. Layer 322083 8 201106824 21 is a layer forming an electrode when a metal layer is laminated by plating on the aforementioned surface, and generally, it can be made of nickel, complex, copper, indium, nickel alloy, Ni-Zn, Ni-Cr-Zn, etc. A metal or an alloy containing the same is formed. The seed layer 21 is not particularly limited as long as it is a method of depositing a conductive metal as described above on the surface of the insulating substrate 10. The plating method is more favorable. The seed layer 21 is formed by sputtering to make it splashed. The metal or alloy is closely adhered to the surface of the insulating substrate 10, and the insulating substrate 10 and the sputtered seed layer 21 are firmly bonded. Therefore, in the manufacture of the printed wiring substrate of the present invention, the insulating substrate is not required. An adhesive layer is provided between 10 and the seed layer 21. Further, the average thickness of the seed layer 2.1 is usually in the range of 10 to 1000 A, preferably 50 to 300 A. After the seed layer 21 is formed in this manner, It is preferable to form the copper thin film layer 22 on the surface of the seed layer 21 as shown in Fig. 2(c), and to form the base layer 23 together with the seed layer 21. In the present invention, the copper thin film layer 22 is Preferably, the copper thin film layer 22 is formed by sputtering, and may be formed by various methods such as vacuum deposition or electroless plating, but by sputtering. When the copper thin film layer is formed, a copper metal circuit having good adhesion and high strength can be formed. The copper thin film layer 22 is a layer mainly composed of copper, and may contain a metal other than copper within a range not impairing the characteristics of the layer. The average thickness of the copper film layer is usually in the range of 0.01 to 1 #m, preferably 0.1 to 0.1. By forming the copper thin film layer 22 at such an average thickness, the affinity with the copper layer formed by the semi-additive method formed on the surface of the copper thin film layer 22 can be improved. 9 322083 201106824 Although the copper thin film layer 22 is formed on the seed layer 21 in the above manner to form the base layer 23', it is not necessary to provide the copper thin film layer 22. In this case, the seed layer 21 serves as the underlayer 23. After the underlayer 23 is formed, it can be directly moved to the next step. However, since an oxide film or the like is formed on the surface of the copper thin film layer 22, the surface of the copper thin layer 22 is made short by a strong acid such as sulfuric acid or hydrochloric acid. After pickling, it is better to move to the next step. In the present embodiment, after the underlayer 23 is formed, as shown by the 20th W, a photoresist layer 3 composed of a photosensitive tree is formed on the entire surface of the copper thin film layer 22 to form the light. Blocking the resin of 3ι, although; the part that is irradiated with light will harden (4) the negative type dissolved in the developing solution, and the part which is exposed to the daylight will dissolve in the visible light. The photosensitive resin can make it positive, but the invention Any film-like resist such as ruthenium film is used as the most layer Γ 'not limited to liquid'. It can also be used as a photoresist layer (4). Here, the photoresist is used. The height of the layer 20 is preferably 7 degrees Celsius to form a wiring e to 25#m, preferably 13 such that the thickness of the photoresist layer 31 is Wang W am. Next, as shown in Fig. 2, a photosensitive tree is formed on the surface of the wire 31, and the photoresist layer 31 is exposed to light and irradiated from the upper portion of the mask 32, thereby forming Wiring electric foot (1)). In the resist pattern 33 formed in this manner (the second collision layer is exposed with the base layer 23 formed in the bottom portion of the recess 33 of the above-mentioned third case. 322 〇 83 201106824 Next, in the present embodiment, the substrate is made When the layer 23 is exposed, the substrate is moved to the copper plating bath, and the base layer 23 is used as one electrode, and a plating voltage is applied between the other electrode provided in the plating tank to perform electrolytic plating. A copper plating layer 24 is formed on the surface of the base layer 23 (Fig. 2(g)). Here, the applied voltage of the electrolytic plating may be a direct current voltage or a pulse voltage, and the copper plating layer 24 may be used. The thickness is preferably designed to be thinner than the resist pattern 33, and it is preferable to make the thickness of the copper plating layer 24 one half or less of the resist pattern 33. This is for smoothly performing the subsequent resist pattern. Here, for the reason of the peeling of the copper plating solution for electroplating, the use of 3-mercapto-l-propanesulfonic acid (hereinafter referred to as 3-mercapto-l-propanesulfonic acid) is used. "MPS") or Bis (3-sulfopropyl) disulfide (abbreviation) At least one of SPS), a 4-stage ammonia salt polymer having a cyclic structure, and gas; and a copper concentration of 23 to 55 g/L, preferably 25 to 40 g/L, and a sulfuric acid concentration of 50 to 250 g/L. Preferably, it is 80 to 220 g/L. This is because the use of the mineral coating of this composition allows the wiring to be formed efficiently by the semi-additive method, and the formed wiring does not have oxidation or shape. An abnormal situation causes the surface to be flat.
此外，半加成用硫酸系銅鍍覆液，必須存在有選自MPS 或SPS之至少一種、具有環狀構造之4級氨鹽聚合體、氣 等3種成分，藉由使用3種成分，即可充分發揮上述的致 果。再者’ MPS及/或SPS之濃度係以設為8至12mg/L 11 322083 201106824 為理想。將MPS及/或SPS之濃度設為上述範圍時，電流 效率不會降低，而配線之橫剖面表面會很平坦，故較佳。 此外，具有前述硫酸系銅電解液中之環狀構造之4級氨鹽 聚合體之濃度係為35至85mg/L，較佳為40至80mg/L。 將 DDAC(Diallyl dimethyl ammonium chloride，4 級氨鹽） 聚合體之硫酸系銅電解液中之濃度設為上述範圍時，電流 效率不會降低，而配線之橫剖面表面會很平坦，故較佳。 在此，以具有環狀構造之4級氨鹽聚合體而言，雖可使用 各種聚合體，惟若考慮上述效果，則以使用DDAC聚合體為 最佳。 此外，半加成用硫酸系銅鍍覆液中之氣濃度係為30至 55mg/L，較佳為35至50mg/L。將該氯濃度設為上述範 圍時，電流效率不會降低，故較佳。另外，在此，氯濃度 亦包含由DDAC而來的氯。 以上所說明之半加成用硫酸系銅鍍覆液，係以液中之 MPS或SPS與DDAC聚合體與氯之成分均衡最重要，此等量 的均衡設為上述範圍時，即可有效率地製造表面平坦之配 線。 再者，使用該半加成用硫酸系銅鍍覆液且以半加成法 形成配線時，液溫係室溫，例如設為15 °C至3 0 °C，較佳為 15至25°C，電流密度係設為ΙΟΑ/dm2以下，較佳為2至 6A/dm2以下並進行電解形成配線為佳。另外，當然亦可視 需要將電解步驟設為複數個步驟，及採用脈衝電解或PR電 解。 12 322083 201106824 使用此種半加成用硫酸系銅鐘覆液形成配線時，可達 成可尚效率地形成配線，而且，不會有配線之氧化或形狀 異常，而使配線橫剖面表面平坦之效果。此外，尤其使用 預疋組成之半加成用硫酸系銅鐘覆液時，可進一步達成獲 得耐折性優異之配線之效果。 接著，如第2圖（h)所示，將阻劑圖案33去除。該阻 劑圖案33之去除，雖可使用鹼洗淨液、有機溶媒等，惟以 使用鹼洗淨液來去除阻劑圖案33為佳。此係由於鹼洗淨液 不會對構成本發明之印刷配線基板之素材造成不良影響， 而且亦不會因為有機溶媒之蒸散等而產生環境污染之故。 =接著，如第2圖（i)所示，將藉由去除阻劑圖案犯所 露出之區域之基底層23去除。 另外，可在以此方式形成配線圖案2〇之印刷配線基板 表面，形成上述阻焊劑層3而作成印刷配線基板i。 ,在此，本實施形態之銅鍍覆層24,如第3圖所詳示， 係具有多層構造。舉其一例而言，如第3圖⑷所示，銅鑛 覆層24係具有：第丄銅鐘覆層24a、第2銅鑛覆層撕、 第3銅鑛覆層24卜第4銅鍍覆層2如之4層構造。此外， 鋼鍍覆層24之雙晶粒徑係未達，車交佳為_以上、 一以下。另外’在第3圖⑷之例中，第4贿覆層_ 雖係鍍覆成與第i至第3顺覆層24a至W相同的厚度， ㈣於以基底層23之去除步驟中_表面，因此膜厚較第 1至第3銅鍍覆層24a至24c稍薄。 在此，所謂多層構造係指各層結晶獨立所形成之多 322083 13 201106824 層，可藉由獨立鑛覆而形成第1至第4銅鑛覆層24a至24d 所構成。例如，在進行第！至第4銅鑛覆層池至⑽之 各鑛覆之後，可將被鍍覆體從鍍覆槽取出而獨立進行下一 個鑛覆’亦可在進行各缝之後，以與第1至第4銅鍵覆 層24a至24d之鍍覆條件不同之條件將可成為邊界之邊界 層形成極薄之後’形成下—個鑛覆層。另外，亦可在各鑛 覆層之間藉由濺鍍法形成薄膜而作成邊界層，但在製造步 驟上雖不是很理想。 如此，藉由設成各鍍覆層獨立的多層構造，即易於形 成雙晶粒徑未達5/zm之銅鍍覆層24，而配線之耐折性亦 與雙晶粒徑未達5#m之設計相互配合而顯著提升。另外， 所謂多層雖指2層以上，惟以3層以上為佳，4層以上尤 佳，即使設計為4層以上的多層，效果提升亦不顯著，因 此以2至8層為佳，且以4層左右尤佳。 此外’銅鍍覆層24之雙晶粒縱橫比（縱/橫）未達 0. 45，尤其為〇· 3至0. 4時，可得知对折性更為顯著地提 升，其詳細内容將於後陳述。 第3圖（b)係在第1至第4銅鑛覆層24a至24d之鍵覆 之前’就先以電流密度較其鍍覆條件低的電流密度，例如 1/5至1/15左右之電流密度進行鍍覆而形成邊界層24e 至24h者。例如’以電流密度5A/dm2形成第1至第4銅鍍 覆層24a至24d時，邊界層24e至24h之電流密度係設為 0. 5A/dm2左右。藉由設置此種邊界層24e至24h，即可更 確實地形成第1至第4銅鍍覆層24a至24d為獨立的多層 14 322083 201106824 構造。 邊界層可設置於所有層間之邊界，亦可僅設於一部分 的層間。另外，在形成與各層之邊界的涵義上，雖非必須 形成邊界層24e，惟在本實施形態中，係以提升下層與第1 銅鍍覆層24之密接性之目的等而形成。設置邊界層時，其 厚度為0.05/zm以下，觀察剖面時亦有無法發現的情形。 此外，此種邊界層24e至24h並不相當於多層構造之各層， 而係設為與第1至第4銅鍍覆層24a至24d合併形成各層 者。 此外，在此，所謂雙晶結晶係定義為：相鄰之結晶粒 處於以<111>為共通旋轉軸旋轉約60°之位置關係時，以 該結晶粒界為雙晶粒界時之結晶者，而雙晶結晶之雙晶粒 之粒徑係定義為雙晶粒徑。 此種雙晶粒徑係依是否將銅鍍覆層24設為多層構造 而大幅變化，而且係依銅鍍覆之條件或各層厚度等而變化 者。 另外，雙晶粒徑係與結晶粒徑無關，而為與結晶粒徑 獨立者。此外，結晶粒徑只要是相同鍍覆條件，是否設為 多層，均無極大變化。 在此，雙晶粒徑係藉由EBSD(Electron Back Scatter DiffractionPatterns)解析所求出者，且藉由剖面觀察而 特別指定雙晶粒，並求得相當於雙晶粒剖面積的近似圓， 且以該圓的直徑為該雙晶粒之雙晶粒徑，而算出此粒徑之 平均值者，只要未特別記載，所謂銅鍍覆層24之雙晶粒 15 322083 201106824 徑，係表示多層構造整體之雙晶粒徑之平均值。 此外，雙晶粒縱橫比係為如上所述特別指定之雙晶粒 之長徑與短徑之比（短徑/長徑），只要未特別記載，所謂 銅鍍覆層24之雙晶粒徑縱橫比，係表示多層構造整體之雙 晶粒徑縱橫比之平均值。另外，雙晶粒之長徑，係由於本 實施形態中銅鍍覆層24為多層構造所引起，通常係與各層 之面方向一致，而短徑則與厚度方向一致。 此外，雙晶粒徑或雙晶粒縱橫比雖亦可依各層來算 出，惟作為提升耐折性之參數使用時，係可使用整體的雙 晶粒徑或雙晶粒縱棱比。 另外，對照各層之雙晶粒徑或雙晶粒縱橫比與耐折性 可得知，最上層之雙晶粒徑或雙晶粒縱橫比與耐折性關聯 性較大，最上層之雙晶粒徑在4 # m以下，最上層之雙晶粒 縱橫比在0. 32以下，尤以0. 20至0. 32為佳。如此，若最 上層之雙晶粒徑及雙晶粒縱橫比為上述範圍，破裂時從印 刷配線基板表面所產生之龜裂就會在最上層及其正下方的 邊界停止，而具有難以成長為較大龜裂的效果。另外，在 本發明之印刷配線基板所獲得之雙晶粒徑之下限值，依經 驗係為0. 3# m左右。 此外，各層之厚度係以4//in以下為佳，整體厚度為 16//m以下，尤其12//m以下，甚至lOym以下為佳。此 係由於藉由將各層厚度及整體厚度設於範圍内，使作成多 層構造之效果變得顯著，而且雙晶粒徑易於成為未達5/im 之故。另外，從製造穩定性的觀點來看，各層厚度係以設 16 322083 201106824 為1 y m為佳。 再者，多層構造之各層厚度係可相同，亦可不同，惟 以將基底層相反侧，亦即愈上側之層設為愈薄為佳。例如， 將上半側之層數設為較整體下半侧之層數多為佳。例如， 將下半側設為1層或2層，及將上半側設為3層或4層者。 [實施例] 接著揭示本發明之實施例以進一步詳細說明本發明。 惟本發明並不限定於此等實施例。 [實施例1] 在厚度為35//m之聚醯亞胺薄膜之前處理側表面，以 250A厚度將Ni-Cr(20at%)進行濺鍍以形成晶種層。再者， 在該晶種層表面以0.3//m厚度將銅進行濺鍍以形成銅薄 膜層。接下來，在銅薄膜層側表面以疊層方式黏合厚度為 15 // m之負型乾薄膜阻劑（旭化成公司製）。 接著使用配置有玻璃光罩之曝光裝置OJSHI0電機股份 有限公司製），以約180mJ/cm2進行紫外線曝光，該玻璃光 罩描繪有由30 μ m間距且寬度為15//m之配線所構成之配 線圖案。 曝光後，藉由10%碳酸鈉溶液顯影，將未曝光部分溶 解，而形成各間距之光阻劑圖案。 在以此方式藉由感光性樹脂形成阻劑圖案之基材捲帶 上，使用SPS濃度為10mg/L、DDAC聚合體濃度為40mg/ L、氯濃度為30mg/L、銅濃度為38.2g/L、硫酸濃度為 100g/L之銅鍍覆液，在溫度25°C下，以電流密度0. 5A/ 17 322083 201106824 dm2形成極薄的邊界層24e。接著，以電流密度5A/dm2形 成厚度為2//m之第1銅鍍覆層24a，而在邊界層24e及第 1銅鍍覆層24a形成厚度2//in。同樣地，依序形成邊界層 24f、第2銅鍍覆層24b、邊界層24g、第3銅鍍覆層24c、 邊界層24h、第4銅鍍覆層24d，整體形成8#m之銅鍍覆 層24。 接著，在以2-乙醇胺（2-aminoethanol)為主成分之50 °C之剝離液中，進行30秒鐘浸潰（dipping)而將阻劑圖案 剝離。接下來，以硫酸及過氧化氫系蝕刻液處理，而藉由 全面蝕刻將基材上之銅薄膜層去除。接著，使用MEC公司 製CH1935將Ni-Cr層溶解以形成各間距之配線圖案。 [實施例2] 除了以與實施例1相同鍍覆條件，以相同厚度形成邊 界層及銅鍍覆層成對的2層，而將整體厚度作成為8# m之 2層構造以外，其餘均與實施例1相同。 [實施例3] 除了以與實施例1相同鍍覆條件，以相同厚度形成邊 界層及銅鍍覆層成對的6層之3層構造以外，其餘均與實 施例1相同。 [實施例4] 除了以與實施例1相同鍍覆條件，以相同厚度形成邊 界層及銅鍍覆層成對的8層之3層構造以外，其餘均與實 施例1相同。 [實施例5] 18 322083 201106824 除了以與實施例1相同鍍覆條件，以相同厚度形成邊 界層及銅鍍覆層成對的10層之3層構造以外，其餘均與實 施例1相同。 [實施例6] 除了以與實施例1相同鍍覆條件，以相同厚度形成邊 界層及銅鍍覆層成對的12層之3層構造以外，其餘均與實 施例1相同。 [實施例7] 除了以與實施例1相同鍍覆條件，以4 # m厚度形成邊 界層及銅鍍覆層成對的1層之後，再同樣地以相同厚度合 計以4am形成5層，而作成整體為8//m厚度的6層構造 以外，其餘均與實施例1相同。 [比較例1 ] 除了將銅鍍覆以電流密度5A/dm2形成8/zm之銅鍍覆 層以外，其餘均與實施例i相同方式製作配線圖案。 (試驗例1) 以與實施例1至7及比較例相同鍍覆條件形成MIT測 量用樣本，且針對此樣本，以彎曲角度：±135(>、彎曲速度： 175rpm(312r/min)、夾盤（chuck)之 r: 〇 8mm、荷重·· 1〇〇gf 來實施ΜIT試驗。 ΜΙΤ試驗之結果，係藉由導通檢驗之斷線檢測方式來 綠§忍’而採用斷線檢測時點之彎曲次數。 將該結果顯示於第1表。 由此結果可得知，在2層以上之多層構造情形下，相 322083 201106824 車乂於比車乂例l ’藉由MIT試驗所得之耐折性較優異。此外， 可知知夕層層數與耐折性並無多大_，即使超過8層， 财折性亦不會顯著提升。因此，可得知以2層至8層為佳， 尤以4層左右為佳。 此外，可得知將相對較薄之層所構成之疊層構造形成 於上半側之實施例7，相較於實施例3(整體為6層構造） 或實鉍例5(將與實施例7上半側之層厚度相同層設為10 層），耐折性顯著較優異。由此可得知，係以作成為上側之 疊層較下側薄的構造為佳，僅將上側作成為薄膜之多層構 造’耐折性更為優異。 第1表 多層構造之層數 MIT實驗結果 實施例1 4 131 實施例2 2 129 實施例3 6 126 實施例4 8 134 實施例5 10 127 實施例6 12 127 實施例7 6 135 比較例1 1 120 (試驗例2) 將針對實施例1、2、7及比較例1進行EBSD解析之結 果顯示於第 2 表。EBSD(Electron Back Scatter 20 322083 201106824In addition, the sulfuric acid-based copper plating solution for semi-addition must have three components selected from the group consisting of at least one of MPS and SPS, a 4-stage ammonia salt polymer having a cyclic structure, and gas, and by using three components. You can make the most of the above results. Furthermore, the concentration of 'MPS and/or SPS is ideally set to 8 to 12 mg/L 11 322083 201106824. When the concentration of MPS and/or SPS is in the above range, the current efficiency is not lowered, and the surface of the cross section of the wiring is flat, which is preferable. Further, the concentration of the 4-stage ammonia salt polymer having a cyclic structure in the sulfuric acid-based copper electrolytic solution is 35 to 85 mg/L, preferably 40 to 80 mg/L. When the concentration in the sulfuric acid-based copper electrolytic solution of the DDAC (Diallyl dimethyl ammonium chloride) polymer is in the above range, the current efficiency is not lowered, and the cross-sectional surface of the wiring is flat, which is preferable. Here, in the case of the 4-stage ammonia salt polymer having a ring structure, various polymers can be used, but in view of the above effects, it is preferred to use a DDAC polymer. Further, the gas concentration in the sulfuric acid-based copper plating solution for semi-addition is 30 to 55 mg/L, preferably 35 to 50 mg/L. When the chlorine concentration is in the above range, the current efficiency is not lowered, which is preferable. In addition, here, the chlorine concentration also includes chlorine derived from DDAC. The above-described semi-addition sulfuric acid-based copper plating solution is most important in that the balance between the MPS or SPS in the liquid and the DDAC polymer and the chlorine component is the most important, and when the equalization is equal to the above range, the efficiency can be obtained. Wiring the surface with a flat surface. Further, when the semi-additive sulfuric acid-based copper plating solution is used and the wiring is formed by a semi-additive method, the liquid temperature is room temperature, for example, 15 ° C to 30 ° C, preferably 15 to 25 °. C, the current density is preferably ΙΟΑ/dm2 or less, preferably 2 to 6 A/dm2 or less, and it is preferable to form wiring by electrolysis. In addition, it is of course also possible to set the electrolysis step to a plurality of steps, and to employ pulse electrolysis or PR electrolysis. 12 322083 201106824 When the wiring is formed by using the sulfuric acid-based copper bell solution of the semi-additive, the wiring can be efficiently formed, and the wiring is not oxidized or the shape is abnormal, and the surface of the wiring cross-section is flat. . Further, in particular, when a semi-addition sulfuric acid-based copper bell coating for a pre-twisting composition is used, the effect of obtaining a wiring excellent in folding endurance can be further achieved. Next, as shown in FIG. 2(h), the resist pattern 33 is removed. For the removal of the resist pattern 33, an alkali cleaning solution, an organic solvent or the like may be used, but it is preferable to use the alkali cleaning solution to remove the resist pattern 33. This is because the alkali cleaning solution does not adversely affect the material constituting the printed wiring board of the present invention, and environmental pollution does not occur due to evapotranspiration of the organic solvent. Then, as shown in Fig. 2(i), the underlayer 23 which is exposed by the removal of the resist pattern is removed. Further, the surface of the printed wiring board on which the wiring pattern 2 is formed in this manner can be formed by forming the solder resist layer 3 to form the printed wiring board i. Here, the copper plating layer 24 of the present embodiment has a multilayer structure as shown in detail in Fig. 3. As an example, as shown in Fig. 3 (4), the copper ore coating 24 has a second copper bell coating 24a, a second copper ore coating, a third copper coating 24, and a fourth copper plating. The coating 2 is constructed in a 4-layer structure. Further, the twin-crystal grain size of the steel plating layer 24 is not reached, and the vehicle cross-linking is preferably _ or more and one or less. Further, in the example of Fig. 3 (4), the fourth bribing layer _ is plated to have the same thickness as the i-th to third compliant layers 24a to W, and (d) in the step of removing the basal layer 23 - surface Therefore, the film thickness is slightly thinner than the first to third copper plating layers 24a to 24c. Here, the term "multilayer structure" means a layer of 322083 13 201106824 formed independently of the crystallization of each layer, and can be formed by forming the first to fourth copper ore layers 24a to 24d by independent mineral coating. For example, in the first! After the 4th copper ore coating pool to the respective mineral deposits of (10), the coated body may be taken out from the plating tank and the next mineral deposit may be carried out independently, or after the respective slits, and the first to fourth The conditions under which the plating conditions of the copper bond layers 24a to 24d are different may be such that the boundary layer of the boundary is extremely thin and then the lower layer is formed. Further, a boundary layer may be formed by forming a thin film between the respective cladding layers by sputtering, but this is not preferable in the production steps. Thus, by providing a multilayer structure in which each plating layer is independent, it is easy to form a copper plating layer 24 having a twin crystal grain size of less than 5/zm, and the folding resistance of the wiring is also different from that of the twin crystal grain size of 5#. The design of m complements each other significantly. Further, the term "multilayer" means two or more layers, preferably three or more layers, more preferably four or more layers, and even if it is designed as a multilayer of four or more layers, the effect is not significantly improved, so that it is preferably 2 to 8 layers, and 4 or so is especially good. In addition, the double-grain aspect ratio (vertical/horizontal) of the copper-plated layer 24 is less than 0.55, especially when 〇·3 to 0.4, the foldability is more significantly improved, and the details thereof will be Described later. Fig. 3(b) is a current density lower than the plating condition before the bonding of the first to fourth copper ore coatings 24a to 24d, for example, about 1/5 to 1/15. The current density is plated to form the boundary layer 24e to 24h. For example, when the first to fourth copper plating layers 24a to 24d are formed at a current density of 5 A/dm2, the current density of the boundary layers 24e to 24h is set to about 0.5 A/dm2. By providing such boundary layers 24e to 24h, it is possible to more reliably form the first to fourth copper plating layers 24a to 24d as independent multilayers 14 322083 201106824. The boundary layer may be disposed at the boundary between all the layers, or may be provided only between a part of the layers. Further, in the meaning of forming the boundary with each layer, the boundary layer 24e is not necessarily formed, but in the present embodiment, it is formed for the purpose of improving the adhesion between the lower layer and the first copper plating layer 24. When the boundary layer is set, the thickness is 0.05/zm or less, and there are cases where the cross section is not found. Further, such boundary layers 24e to 24h do not correspond to the respective layers of the multilayer structure, but are formed by combining the first to fourth copper plating layers 24a to 24d to form respective layers. Here, the term "double crystal" is defined as a crystal in which the adjacent crystal grains are in a positional relationship in which the crystal grain boundary is a double grain boundary when the position of rotation of the adjacent crystal grain is about 60°. The particle size of the twin crystals of the twin crystal is defined as the twin grain size. Such a twin crystal grain size varies greatly depending on whether or not the copper plating layer 24 has a multilayer structure, and varies depending on conditions of copper plating, thickness of each layer, and the like. Further, the twin crystal grain size is independent of the crystal grain size and is independent of the crystal grain size. Further, the crystal grain size is not changed as much as long as it is the same plating condition and is set to a plurality of layers. Here, the twin crystal grain size is determined by EBSD (Electron Back Scatter Diffraction Pattern) analysis, and the double crystal grains are specifically designated by cross-sectional observation, and an approximate circle corresponding to the cross-sectional area of the double crystal grain is obtained, and The diameter of the circle is the twin crystal grain size of the double crystal grain, and the average value of the particle diameter is calculated. Unless otherwise specified, the double crystal grain of the copper plating layer 24 is 322083, 201106824, which means a multilayer structure. The average of the overall twin grain size. Further, the double-grain aspect ratio is a ratio of a long diameter to a short diameter (short diameter/long diameter) of the double crystal grains specified as described above, and the twin crystal grain size of the copper plating layer 24 is not particularly described unless otherwise specified. The aspect ratio is an average value of the aspect ratio of the twin crystal grain size of the entire multilayer structure. Further, the long diameter of the double crystal grains is caused by the multilayer structure of the copper plating layer 24 in the present embodiment, and generally corresponds to the surface direction of each layer, and the short diameter coincides with the thickness direction. In addition, the twin crystal grain size or the twin grain aspect ratio can be calculated according to each layer, but when used as a parameter for improving the folding endurance, the overall twin grain size or the twin grain longitudinal ratio can be used. In addition, by comparing the double crystal grain size or the double grain aspect ratio and the folding endurance of each layer, it can be known that the double crystal grain size or the double grain aspect ratio of the uppermost layer is highly correlated with the folding endurance, and the uppermost double crystal The particle size is less than 4 # m, and the uppermost layer has an aspect ratio of 0.32 or less. When the bilayer grain size and the twin grain aspect ratio of the uppermost layer are in the above range, the crack generated from the surface of the printed wiring board at the time of the fracture stops at the boundary between the uppermost layer and the immediately below, and it is difficult to grow into Larger cracking effect. Further, the lower limit of the twin crystal grain size obtained by the printed wiring board of the present invention is about 0.30 m. Further, the thickness of each layer is preferably 4//in or less, and the overall thickness is 16//m or less, particularly 12//m or less, or even 10 μm or less. Since the thickness and the overall thickness of each layer are set in the range, the effect of forming a multi-layer structure becomes remarkable, and the twin crystal grain size tends to be less than 5/im. Further, from the viewpoint of manufacturing stability, the thickness of each layer is preferably set to be 16 322083 201106824 for 1 y m. Further, the thickness of each layer of the multilayer structure may be the same or different, but it is preferable to make the layer on the opposite side of the base layer, that is, the upper side, thinner. For example, it is preferable to set the number of layers on the upper half side to be larger than the number of layers on the lower half of the whole. For example, the lower half side is set to one or two layers, and the upper half side is set to three or four layers. [Examples] Next, examples of the invention will be disclosed to explain the invention in further detail. However, the invention is not limited to the embodiments. [Example 1] A side surface was treated before a polyimide film having a thickness of 35 / / m, and Ni-Cr (20 at%) was sputtered at a thickness of 250 A to form a seed layer. Further, copper was sputtered on the surface of the seed layer at a thickness of 0.3 / / m to form a copper thin film layer. Next, a negative dry film resist (manufactured by Asahi Kasei Corporation) having a thickness of 15 // m was bonded to the side surface of the copper thin film layer by lamination. Next, ultraviolet exposure was performed at about 180 mJ/cm 2 using an exposure apparatus (manufactured by OJSHI0 Motor Co., Ltd.) equipped with a glass mask, and the glass mask was formed by wiring having a pitch of 30 μm and a width of 15/m. Wiring pattern. After the exposure, the unexposed portions were dissolved by developing with a 10% sodium carbonate solution to form photoresist patterns at respective pitches. In the substrate tape in which the resist pattern was formed by the photosensitive resin in this manner, the SPS concentration was 10 mg/L, the DDAC polymer concentration was 40 mg/L, the chlorine concentration was 30 mg/L, and the copper concentration was 38.2 g/ L, a copper plating solution having a sulfuric acid concentration of 100 g/L, at a temperature of 25 ° C, a very thin boundary layer 24e is formed at a current density of 0.5 A / 17 322083 201106824 dm2. Next, a first copper plating layer 24a having a thickness of 2/m was formed at a current density of 5 A/dm2, and a thickness of 2//in was formed in the boundary layer 24e and the first copper plating layer 24a. Similarly, the boundary layer 24f, the second copper plating layer 24b, the boundary layer 24g, the third copper plating layer 24c, the boundary layer 24h, and the fourth copper plating layer 24d are sequentially formed, and the overall plating of 8#m is performed. Coating 24. Next, the resist pattern was peeled off by dipping for 30 seconds in a peeling solution of 50 °C containing 2-aminoethanol as a main component. Next, it is treated with sulfuric acid and a hydrogen peroxide-based etching solution, and the copper thin film layer on the substrate is removed by overall etching. Next, the Ni-Cr layer was dissolved using CH1935 manufactured by MEC Corporation to form wiring patterns of respective pitches. [Example 2] Except that the plating conditions were the same as in Example 1, two layers of the boundary layer and the copper plating layer were formed in the same thickness, and the entire thickness was made into a two-layer structure of 8 #m. The same as in the first embodiment. [Example 3] The same procedure as in Example 1 was carried out except that the boundary layer was formed in the same thickness as in Example 1, and a three-layer structure in which a boundary layer and a copper plating layer were paired in the same thickness was formed. [Example 4] The same procedure as in Example 1 was carried out, except that the boundary layer was formed in the same thickness as in Example 1, and the boundary layer and the copper plating layer were formed in a three-layer structure of eight layers in the same thickness. [Example 5] 18 322083 201106824 The same as Example 1 except that the boundary layer was formed in the same thickness as in Example 1, and a three-layer structure in which a boundary layer and a copper plating layer were paired in 10 layers was formed. [Example 6] The same procedure as in Example 1 was carried out, except that the boundary layer was formed in the same thickness as in Example 1, and the boundary layer and the copper plating layer were formed in a pair of 12 layers. [Example 7] A layer in which a boundary layer and a copper plating layer were formed in a thickness of 4 # m was formed in the same plating conditions as in Example 1, and then a total of 5 layers were formed in 4 mm in the same thickness. The same as in the first embodiment except that a six-layer structure having a thickness of 8/m was formed as a whole. [Comparative Example 1] A wiring pattern was produced in the same manner as in Example i except that copper plating was performed to form a copper plating layer of 8/zm at a current density of 5 A/dm2. (Test Example 1) Samples for MIT measurement were formed under the same plating conditions as those of Examples 1 to 7 and Comparative Examples, and for this sample, a bending angle: ±135 (>, bending speed: 175 rpm (312 r/min), The chuck test (r): 〇8mm, load··1〇〇gf to carry out the ΜIT test. The result of the ΜΙΤ test is based on the disconnection detection method of the continuity test, and the green § ' ” The number of times of bending is shown in Table 1. From this result, it can be seen that in the case of a multilayer structure of two or more layers, the phase 322083 201106824 is ruined by the MIT test. In addition, it is known that the number of layers and the folding endurance are not much _, even if it exceeds 8 layers, the financial property will not be significantly improved. Therefore, it is better to use 2 to 8 layers, especially Preferably, about four layers are obtained. Further, it is known that the laminated structure formed of the relatively thin layer is formed on the upper half side, compared to the third embodiment (the overall six-layer structure) or the actual example. 5 (10 layers of the same layer thickness as the upper half of Example 7), the folding endurance is remarkably excellent. It is understood that the structure in which the upper side is thinner than the lower side is preferable, and the multilayer structure in which the upper side is made into a film is more excellent in folding resistance. The number of layers of the first table multilayer structure is MIT experimental results. Example 1 4 131 Example 2 2 129 Example 3 6 126 Example 4 8 134 Example 5 10 127 Example 6 12 127 Example 7 6 135 Comparative Example 1 1 120 (Test Example 2) For Example 1, The results of EBSD analysis in 2, 7 and Comparative Example 1 are shown in Table 2. EBSD (Electron Back Scatter 20 322083 201106824
Diffraction Patterns，電子背向散射繞射）解析係於沪μ 配線之長度方向以切片機（microtome)進行剖面加工之 後，以FIB(Focused Ion Beam，聚焦離子束）進行钱刻加 工作為觀察用試料。 詳細解析條件如下。此外，實施例1及比較例丨之剖 面相片顯示於第4圖。 EBSD解析 •裝置：掃描型電子顯微鏡部（Zeiss公司SUPRATM 55VP) EBSD 部（EDAX 公司之 Pegasus system) •觀察用試料：在設置於試料台之狀態下傾斜7 〇度 •觀察倍率：5000倍 •觀察視野：10x30mm • WD(Working Distance，工作距離）約 15mm •具有2°以上方位差時即辨識為晶粒界 •測量軟體：TSL 0ΙΜ Data Collection 5 •解析軟體：TSL 0ΙΜ Analysis 5. 1 結果’從剖面相片可明顯得知實施例1的試料具有多 層構造。 此外，EBSD解析之結果，可得知在多層構造之實施例 1、2及7中，銅鍍覆層（整體）之雙晶粒徑未達5μιη、雙晶 粒縱橫比未達0· 45，惟在單層之比較例1中，雙晶粒徑為 5"m以上、雙晶粒縱橫比為0.45以上。此外，可得知雙 晶粒縱橫比在實施例2中係為〇. 43，惟在耐折性更優異之 21 322083 201106824 實施例1及7中’係落在0.32及〇 4〇、與〇 3至〇·4之 範圍。 ’ 此外，可得知在實施例i、2及7中，最上層之雙晶粒 徑4/zm以下、最上層之雙晶粒縱橫比為〇 32以下、落在 0. 20至0· 32之範圍。 第2表 整體 r—-——_ - 第1層 第2層 第3層 第4層 第5層 第6層 實施例 雙晶粒徑 (^ m) 4. 20 2. 72 4. 72 4.86 ----- 2. 65 1 雙晶粒 縱橫比 0.32 0.43 0. 30 0. 28 T" · ·* — 0. 24 實施例 雙晶粒徑 (β m) 4. 16 3. 59 3.96 — _ 2 雙晶粒 縱橫比 0.43 0. 47 0. 30 ---- 實施例 雙晶粒徑 (// m) 3. 44 3. 10 1. 59 1.12 1. 82 1. 38 1. 17 7 雙晶粒 縱橫比 0. 40 0. 43 0. 46 0. 39 0.34 0. 39 0. 31 比較例 雙晶粒徑 (β m) 5.31 1 ^---- 雙晶粒 縱橫比 "-- 0. 45 ____ 【圖式簡單說明】 ，第1圖係為顯示以本發明—實施㈣之印刷配線基板 之製造方法所製造之印刷配線基板之—例之概略平面圖。 第2圖（a)至（i)係為說明本發明一 實施形態之印刷配 22 322083 201106824 線基板之製造方法之各步驟之剖面圖。 第3圖（a)及（b)係為銅鍍覆層之放大剖面圖。 第4圖（a)及（b)係為實施例1及比較例1之配線之剖 面相片。 【主要元件符號說明】 1 印刷配線基板 2 鏈齒孔 3 阻焊層 10 絕緣基材 20 配線圖案 21 晶種層 21A 内引腳 21B 外引腳 22 銅薄膜層 23 基底層 24 銅鍍覆層 24a 第1銅鑛覆層 24b 第2銅鑛覆層 24c 第3銅鍍覆層 24d 第4銅鍍覆層 24e至24h邊界層 31 光阻劑層 32 光罩 33 阻劑圖案 33a 凹部 23 322083The Diffraction Patterns (Electrical Backscattering Diffraction) analysis is performed by a microtome in the length direction of the Shanghai μ wiring, and then the FIB (Focused Ion Beam) is used for observation. The detailed analysis conditions are as follows. Further, cross-sectional photographs of Example 1 and Comparative Example are shown in Fig. 4. EBSD analysis and installation: Scanning Electron Microscopy Department (Zeiss SUPRATM 55VP) EBSD Department (Pegasus system of EDAX Company) • Observation sample: Tilting 7 degrees in the state set on the sample stage • Observation magnification: 5000 times • Observation Field of view: 10x30mm • WD (Working Distance) is about 15mm • It is recognized as grain boundary when there is a difference of 2° or more. • Measurement software: TSL 0ΙΜ Data Collection 5 • Analytical software: TSL 0ΙΜ Analysis 5. 1 Result 'From The cross-sectional photograph clearly shows that the sample of Example 1 has a multilayer structure. In addition, as a result of EBSD analysis, it can be seen that in Examples 1, 2, and 7 of the multilayer structure, the double-crystal grain size of the copper plating layer (whole) is less than 5 μm, and the double-crystal aspect ratio is less than 0.55. In Comparative Example 1 of the single layer, the twin crystal grain size was 5 " m or more, and the double crystal grain aspect ratio was 0.45 or more. In addition, it can be known that the aspect ratio of the twin crystal grains is 〇. in Example 2, but it is more excellent in folding endurance. 21 322083 201106824 In Examples 1 and 7, 'the system falls within 0.32 and 〇4〇, and 〇 3 to 〇·4 range. In addition, it can be seen that in the examples i, 2, and 7, the uppermost layer has a twin crystal grain size of 4/zm or less, and the uppermost layer has a double crystal grain aspect ratio of 〇32 or less and falls at 0. 20 to 0·32. The scope. Table 2 overall r——————— 1st layer 2nd layer 3rd layer 4th layer 5th layer 6th layer embodiment Twin crystal grain size (^ m) 4. 20 2. 72 4. 72 4.86 - ---- 2. 65 1 double grain aspect ratio 0.32 0.43 0. 30 0. 28 T" · ·* — 0. 24 Example twin crystal grain size (β m) 4. 16 3. 59 3.96 — _ 2 Double grain aspect ratio 0.43 0. 47 0. 30 ---- Example twin grain size (// m) 3. 44 3. 10 1. 59 1.12 1. 82 1. 38 1. 17 7 Double grain Aspect ratio 0. 40 0. 43 0. 46 0. 39 0.34 0. 39 0. 31 Comparative example twin grain size (β m) 5.31 1 ^---- double grain aspect ratio "-- 0. 45 ____ [Brief Description of the Drawings] FIG. 1 is a schematic plan view showing an example of a printed wiring board manufactured by the method for manufacturing a printed wiring board of the present invention (4). Fig. 2 (a) to (i) are cross-sectional views showing respective steps of a method of manufacturing a printed wiring 22 322083 201106824 line substrate according to an embodiment of the present invention. Fig. 3 (a) and (b) are enlarged cross-sectional views of the copper plating layer. Fig. 4 (a) and (b) are cross-sectional photographs of the wirings of Example 1 and Comparative Example 1. [Main component symbol description] 1 Printed wiring board 2 Spiral hole 3 Solder mask 10 Insulating substrate 20 Wiring pattern 21 Seed layer 21A Inner lead 21B Outer lead 22 Copper film layer 23 Base layer 24 Copper plating layer 24a First copper ore coating 24b second copper ore coating 24c third copper plating layer 24d fourth copper plating layer 24e to 24h boundary layer 31 photoresist layer 32 light mask 33 resist pattern 33a concave portion 23 322083