KR101057878B1 - Printed wiring board and its manufacturing method - Google Patents

Abstract

Provided are a printed wiring board having wiring excellent in corrosion resistance and a method of manufacturing the same. A printed wiring board having a wiring pattern including a base layer 23 on a surface of an insulating substrate 10 and a copper plating layer 24 formed by a semiadditive process thereon, wherein the copper plating layer 24 has a multilayer structure. It has a twin particle diameter of less than 5 micrometers.

Description

Printed wiring board and its manufacturing method {PRINTED CIRCUIT BOARD AND ITS MANUFACTURING METHOD}

TECHNICAL FIELD This invention relates to printed circuit boards, such as a COF film carrier tape, and its manufacturing method.

Output side external lead and input side of printed wiring board, such as TAB tape of 3-layer structure with wiring pattern made of insulation film, adhesive layer and conductive metal foil or COF tape of 2-layer structure with wiring pattern made of conductive metal foil directly on insulation film The external lead is electrically connected to, for example, a circuit portion of a liquid crystal panel or a rigid printed wiring board by an anisotropic conductive film (ACF).

As the fine pitch of the bumps of the driver IC chip is increased with the recent high precision of the LCD screen, there is a need to form a circuit having a thinner internal lead pitch of 20 μm or less even in printed circuit boards for IC mounting such as COF. Soybean has been raised, and the 15 μm pitch has also entered the field of view.

In recent years, the technology of forming an ultra-fine pitch wiring pattern by a semi-additive method has been advanced, so that even if the conductor thickness such as Cu is thicker than 8 µm, the wiring pattern having a pitch of 20 µm or less is formed. It became possible to do that.

In this semi-additive process, a base layer is formed on an insulator layer, and then a resist pattern that is opposite to the wiring pattern is formed thereon, followed by electroplating. Then, the resist is peeled off and the base layer is removed to form a wiring. To form a pattern.

In addition, in order to solve the problem that the wiring by the semi-additive method does not form a dense crystal structure at the upper part of the plating layer and microcracks occur, a sputtering layer is interposed between copper plating to improve the compactness. This is proposed (refer patent document 1).

However, there is a problem that the cut resistance of the wiring pattern on the printed wiring board is lowered by narrowing the wiring width with fine pitch. On the other hand, although the technique of patent document 1 did not consider this point, since a sputtering layer is put in a multilayer anyway, there exists a problem in terms of manufacturing efficiency.

Patent Document 1: Japanese Patent Application Laid-Open No. 2006-278950

In view of the above circumstances, an object of the present invention is to provide a printed wiring board having a wiring excellent in cutting resistance and a manufacturing method thereof.

1st aspect of this invention is a printed wiring board which has a wiring pattern containing the base layer on the surface of an insulating base material, and the copper plating layer formed by the semiadditive process on it, The said copper plating layer has a multilayered structure, and a twin A particle size is less than 5 micrometers, It is a printed wiring board characterized by the above-mentioned.

In such a 1st aspect, since the copper plating layer by a semiadditive process has a multilayered structure, and a twin grain size is less than 5 micrometers, it is excellent in the corrosion resistance of a wiring pattern.

The 2nd aspect of this invention is the printed wiring board of 1st aspect characterized by the thickness of each layer of the said multilayer structure being 4 micrometers or less.

In such a 2nd aspect, the thickness of each layer of a multilayered structure is 4 micrometers or less, and more effectively, corrosion resistance improves.

The 3rd aspect of this invention is a printed wiring board as described in the 1st or 2nd aspect characterized by the bisizing aspect ratio of the said copper plating layer being less than 0.45.

In such a 3rd aspect, bisorption aspect ratio of a copper plating layer is less than 0.45, and cutting resistance improves more effectively.

According to a fourth aspect of the present invention, a boundary layer formed at a lower current density than the plating current density at the time of forming each layer is provided on the lower surface of each layer in the multilayer structure in the stacking direction. It is a printed wiring board in any one of them.

In such a 4th aspect, a copper plating layer will have a multilayered structure more reliably through a boundary layer, and a twin grain diameter will be less than 5 micrometers.

A fifth aspect of the present invention is the printed wiring board according to any one of the first to fourth aspects, wherein each layer of the multilayer structure is thinner than the layer below the stacking direction.

In such a fifth aspect, by lowering the upper layer than the lower layer in the stacking direction, the fracture resistance is effectively improved.

6th aspect of this invention is the manufacturing method of the printed wiring board in any one of the 1st-5th aspect characterized by the thinnest layer of the uppermost surface of the lamination direction of the said multilayer structure.

In such a sixth aspect, cutting resistance is effectively improved by making the layer on the uppermost surface in the stacking direction of the multilayer structure the thinnest.

According to a seventh aspect of the present invention, a conductive underlayer is formed on the surface of an insulating substrate, a photoresist layer is formed on the surface of the underlayer, and a predetermined pattern is exposed and developed on the photoresist layer to pattern the substrate. A recess is formed to expose the layer, and a copper plating layer is formed on the underlying layer of the recess. Thereafter, the patterned photoresist layer is peeled off, and then the underlying layer exposed by peeling off the photoresist layer is removed to form a wiring pattern, wherein the plating of the copper plating layer is divided into multiple stages. It is a manufacturing method of the printed wiring board characterized by the above-mentioned, and the said copper plating layer having a multilayered structure, and having a twin grain diameter of less than 5 micrometers.

In such a seventh aspect, the copper plating layer by the semiadditive process is made into a multilayer structure, and the wiring pattern excellent in abrasion resistance can be manufactured by making a twin grain size less than 5 micrometers.

An eighth aspect of the present invention is a method for manufacturing a printed wiring board according to the seventh aspect, wherein a boundary layer is formed at a current density lower than the current density of the plating of each layer between the platings divided into the multi-stage. .

In such an eighth aspect, by forming the multilayer structure via the boundary layer, the copper plated layer can be produced more reliably with a multilayer structure and a twin grain size of less than 5 m.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic top view which shows an example of the printed wiring board manufactured by the manufacturing method of the printed wiring board which concerns on one Embodiment of this invention.
It is sectional drawing explaining each process of the manufacturing method of the printed wiring board which concerns on one Embodiment of this invention.
3 is an enlarged cross-sectional view of the copper plating layer.
4 is a cross-sectional photograph of wirings of the first embodiment and the first comparative example.

EMBODIMENT OF THE INVENTION Hereinafter, the printed wiring board which concerns on one Embodiment of this invention, and its manufacturing method are demonstrated.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the COF film carrier tape which is a printed wiring board which concerns on one Embodiment.

The COF film carrier tape 1 of this embodiment shown in FIG. 1 forms the wiring pattern 20 which has the desired pattern which consists of a conductor layer on the insulating base material 10 which consists of a polyimide layer, and a wiring pattern 20 generally includes wirings having internal leads 21A and 22A serving as terminals and external leads 21B and 22B. Sprocket holes 2 are generally formed at both sides in the width direction of the insulating base 10 of the COF film carrier tape 1, and the inner leads 21A and 22A and the outer leads 21B and 22B of the wiring pattern 20 are formed. ), A solder resist layer 3 is formed to cover the wiring pattern 20.

Here, the wiring to be the terminal portion, for example, the internal leads 21A and 22A, has a pitch of the wiring of 30 µm or less, preferably 20 µm or less, line width of 6 µm or more, preferably 7 µm to 15 µm, line width The interval between them is 15 µm or less, preferably 13 µm or less, and the thickness of the wiring is 6 to 15 µm, preferably 6 to 12 µm.

Here, the manufacturing method of the printed wiring board of FIG. 1 is demonstrated concretely, referring drawings.

2 is a diagram illustrating an example of a substrate cross section in each step of the method of manufacturing a printed wiring board according to the present embodiment.

As shown to Fig.2 (a), (b), in the manufacturing method of the printed wiring board of this embodiment, the seed layer 21 which consists of an electroconductive metal foil layer is formed in at least one surface of the insulating base material 10. As shown to FIG. . Here, the insulating base material 10 can be used without particular limitation, if it is used as a normal insulating base material, such as a board, a film, a sheet, and a prepreg which consists of insulating resin. However, in order to manufacture continuously the printed wiring board of this invention by the reel-to-reel system, it is preferable that this insulating base material 10 has flexibility. Moreover, in the process of manufacturing a printed wiring board, since this insulating base material 10 may contact an acidic solution or an alkaline solution, it is preferable that it is excellent in chemical-resistance. Moreover, since it may be exposed to high temperature, it is preferable that it is excellent in heat resistance. In addition, since the wiring pattern is manufactured by the plating process using this insulating base material 10, it is preferable not to modify or deform by contact with water. From this viewpoint, it is preferable to use a heat resistant synthetic resin film as the insulating base material 10 used in the present invention, and in particular, a polyimide film, a polyamideimide film, a polyester resin film, a fluororesin film, a liquid crystal resin film, or the like. It is preferable to use the resin film normally used for manufacture of a printed wiring board, and among these, the polyimide film which is excellent in characteristics, such as heat resistance, chemical resistance, and water resistance, is especially preferable.

In addition, in this invention, the insulating base material 10 does not need to be a film form as mentioned above, For example, the plate-shaped insulating base material which consists of composites, such as a fibrous substance and an epoxy resin, may be sufficient.

In the present invention, the insulating substrate 10 as described above, in addition to the sprocket hole (2) can be provided with necessary through-holes, such as bending slits as necessary. These through holes can be formed by punching, laser drilling, or the like.

In the present embodiment, as described above, the seed layer 21 made of the conductive metal foil layer is formed on at least one surface of the insulating base 10. This seed layer 21 is a layer which becomes an electrode when laminating a metal layer on the surface by electroplating, and is usually nickel, chromium, copper, cobalt, nickel-chromium alloy, Ni-Zn, Ni-Cr- It can be formed from a metal such as Zn or an alloy containing these metals. The seed layer 21 is not particularly limited as long as it is a method of depositing the above-mentioned conductive metal on the surface of the insulating base 10, but is preferably formed by sputtering. By forming the seed layer 21 by sputtering, the metal or alloy to be sputtered adheres to the surface of the insulating base 10, and the insulating base 10 and the sputtered seed layer 21 are firmly bonded. Therefore, when manufacturing the printed wiring board of this invention, it is not necessary to provide an adhesive bond layer between the insulating base material 10 and the seed layer 21.

The average thickness of the seed layer 21 is usually in the range of 10 to 1000 mm 3, preferably 50 to 300 mm 3.

After forming the seed layer 21 in this manner, as shown in FIG. 2C, the copper thin film layer 22 is formed on the surface of the seed layer 21 to form the base layer 23 together with the seed layer 21. It is preferable to make it). In the present invention, the copper thin film layer 22 is preferably formed by sputtering, for example. However, the copper thin film layer 22 is not limited to sputtering but can be formed by various methods such as vacuum evaporation and electroless plating. However, when the copper thin film layer formed by sputtering is formed, the bonding strength is high and the strength is high. A copper metal circuit can be formed. Although the copper thin film layer 22 is a layer containing copper as a main component, metals other than copper may be contained in the range which the characteristic of this layer is not impaired. The average thickness of the copper thin film layer is usually in the range of 0.01 to 1 m, preferably 0.1 to 0.5 m. By forming the copper thin film layer 22 in such an average thickness, affinity with the copper layer formed by the semiadditive process formed in the surface of the copper thin film layer 22 improves.

As described above, the copper thin film layer 22 is formed on the seed layer 21 to form the base layer 23. The copper thin film layer 22 is not necessarily provided, and in this case, the seed layer 21 Layer 23.

After the base layer 23 is formed, the process may proceed to the next step as it is. However, since an oxide film or the like may be formed on the surface of the copper thin film layer 22, the copper thin film layer 22 may be formed of a strong acid such as sulfuric acid or hydrochloric acid. After pickling the surface for a short time, it is preferable to transfer to the next process.

In this embodiment, after forming the base layer 23, as shown in FIG.2 (d), the photoresist layer 31 which consists of photosensitive resin is formed in the whole surface of the copper thin film layer 22 surface. The resin for forming the photoresist layer 31 has a negative type in which a portion irradiated with light hardens and is not dissolved by a developer, and a positive type in which a portion irradiated with light is dissolved by a developer. Photosensitive resin can be used. Moreover, you may laminate and use film-like resists, such as a film, without restrict | limiting to a liquid phase. In the present embodiment, a negative dry film resist is laminated to form a photoresist layer 31.

Here, the photoresist layer 31 is preferably thicker than the height of the wiring pattern 20 to be formed. For example, the thickness of the photoresist layer 31 is 5 to 25 µm, preferably 13 to 20. [Mu] m.

Next, as shown in FIG. 2E, a photomask 32 having a desired pattern is disposed on the surface of the photoresist layer 31, and light is irradiated on the photomask 32 to form a photoresist layer ( The photosensitive resin of the part which forms a wiring circuit is removed by photosensitive and continuing development, and the resist pattern 33 is formed (FIG.2 (f)). The base layer 23 formed in FIG. 2C is exposed at the bottom of the recess 33a of the resist pattern 33 thus formed.

Subsequently, in this embodiment, the substrate is moved to an electroplating bath with the underlying layer 23 exposed, and the plating voltage is formed between the other electrode provided in the plating bath with the underlying layer 23 as one electrode. Is applied to electrolytic plating to form a copper plating layer 24 on the surface of the underlying layer 23 (Fig. 2 (g)).

Here, the applied voltage of the electroplating may be a direct current voltage or a pulse voltage, and the thickness of the copper plating layer 24 is preferably made thinner than the thickness of the resist pattern 33, and the thickness of the copper plating layer 24 is made the resist pattern. (33) It is more preferable to set it as half or less of thickness. This is for smooth peeling of the resist pattern 33 thereafter.

Here, as the copper plating solution to be electroplated, at least one selected from 3-mercapto-1-propanesulfonic acid (called "MPS") or bis (3-sulfopropyl) disulfide (called "SPS") and annular A quaternary ammonium salt polymer having a structure and chlorine, having a copper concentration of 23 to 55 g / L, preferably 25 to 40 g / L, and a sulfuric acid concentration of 50 to 250 g / L, preferably 80 to 220 It is preferable to use what is g / L.

By using the plating liquid of such a composition, wiring formation by a semiadditive process can be performed with high efficiency, and the formed wiring becomes a flat surface without burning or a shape abnormality.

In addition, the sulfuric acid copper plating solution for semiadditives requires at least one selected from MPS or SPS, the quaternary ammonium salt polymer having a cyclic structure, and the presence of three components of chlorine. It is enough. In addition, it is preferable that the density | concentration of MPS and / or SPS shall be 8-12 mg / L. If the concentration of MPS and / or SPS is in the above-described range, there is no decrease in current efficiency and the surface of the wiring cross section is flat, which is preferable. In addition, the concentration of the quaternary ammonium salt polymer having a cyclic structure in the sulfuric acid-based coin dissolving solution is 35 to 85 mg / L, preferably 40 to 80 mg / L. When the concentration of the quaternary ammonium salt polymer having a cyclic structure in the sulfate-based coin solution is in the above range, the surface of the wiring cross section is flat and there is no decrease in current efficiency, which is preferable. Here, various kinds of quaternary ammonium salt polymers having a cyclic structure can be used. In view of the above-mentioned effects, it is most preferable to use a diallyldimethylammonium chloride ("DDAC") polymer.

The chlorine concentration in the sulfuric acid copper plating solution for semi-additives is 30 to 55 mg / L, preferably 35 to 50 mg / L. When the chlorine concentration is in the above range, there is no decrease in current efficiency, which is preferable. On the other hand, the chlorine concentration here also includes chlorine derived from DDAC.

In the sulfuric acid-based copper plating solution for semi-additive described above, the balance of components of MPS or SPS, DDAC polymer and chlorine in the liquid is most important, and when these quantitative balances are within the above ranges, wiring having a flat surface can be efficiently produced. have.

And when wiring is formed by the semiadditive process using the sulfuric acid type copper plating solution for semiadditives, liquid temperature is room temperature, for example, 15 degreeC-30 degreeC, Preferably it is 15-25 degreeC, and current density is 10 It is preferable to form a wiring by electrolysis at A / dm 2 or less, preferably 2 to 6 A / dm 2 or less. In addition, of course, you may make an electrolysis process into several steps as needed, or may employ | adopt pulse electrolysis or PR electrolysis.

When the wiring is formed using such a semi-additive sulfuric acid copper plating solution, the wiring can be formed with high efficiency, there is no burning of the wiring or abnormality in shape, and the surface of the wiring cross section is flat. Moreover, especially when the sulfuric acid type copper plating liquid for semiadditives of a predetermined composition is used, there exists an effect which can further obtain the wiring excellent in corrosion resistance.

Next, as shown in FIG. 2H, the resist pattern 33 is removed. Alkali cleaning liquid, an organic solvent, etc. can be used for removal of this resist pattern 33, but it is preferable to remove the resist pattern 33 using alkaline cleaning liquid. This is because the alkaline cleaning liquid does not adversely affect the material constituting the printed wiring board of the present invention and also does not cause environmental pollution due to evaporation and diffusion of the organic solvent.

Subsequently, as shown in FIG. 2 (i), the underlayer 23 of the exposed region is removed by removing the resist pattern 33.

In addition, the soldering resist layer 3 mentioned above can be formed in the surface of the printed wiring board in which the wiring pattern 20 was formed, and it can be set as the printed wiring board 1 here.

Here, the copper plating layer 24 of this embodiment has a multilayered structure, as shown in detail in FIG. As an example, as shown to Fig.3 (a), the copper plating layer 24 is the 1st copper plating layer 24a, the 2nd copper plating layer 24b, the 3rd copper plating layer 24c, and the 4th copper plating layer ( It has a four-layer structure of 24d). In addition, the twin grain size of the copper plating layer 24 is less than 5 micrometers, Preferably they are 1 micrometer or more and less than 5 micrometers. On the other hand, in the example of FIG. 3A, the fourth copper plating layer 24d is plated with the same thickness as the first to third copper plating layers 24a to 24c, but the surface of the underlying layer 23 is removed. Since this is etched, the film thickness becomes somewhat thinner than the first to third copper plating layers 24a to 24c.

Here, the multilayer structure means that the crystals of the respective layers are formed independently to become a multilayer, and can be formed by forming the first to fourth copper plating layers 24a to 24d by independent plating. For example, after performing each plating of the 1st-4th copper plating layers 24a-24d, the to-be-plated body may be taken out of a plating bath and next plating may be performed independently, and after each plating, 1st-4th After forming the boundary layer which can become a boundary on the conditions different from the plating conditions of copper plating layers 24a-24d very thinly, you may form the next plating layer. On the other hand, although it is not preferable in a manufacturing process, a thin film by sputtering method can also be provided between each plating layer, and it can also be set as a boundary layer.

Thus, by making each plating layer into an independent multilayer structure, it is easy to form the copper plating layer 24 with a twin grain diameter of less than 5 micrometers, and it improves not only the twin grain size of less than 5 micrometers, but also the wiring-resistance significantly. On the other hand, although a multilayer means two or more layers, three or more layers are preferable, and four or more layers are more preferable, but even if it is more than four layers, since the improvement of an effect is not remarkable, 2-8 layers are preferable and four layers are preferable. Front and back are particularly preferred.

In addition, although it mentions later in detail, it turns out that abrasion resistance improves more remarkably when the bi-grain aspect ratio (length / width) of the copper plating layer 24 is less than 0.45, especially 0.3-0.4.

3 (b) shows a current density having a lower current density than the plating conditions, for example, a current density of about 1/5 to 1/15 prior to the plating of the first to fourth copper plating layers 24a to 24d. The plating was performed at to form the boundary layers 24e to 24h. For example, when the first to fourth copper plating layers 24a to 24d are formed at a current density of 5 A / dm 2, the current density of the boundary layers 24e to 24h is about 0.5 A / dm 2. By providing such boundary layers 24e to 24h, an independent multilayer structure of the copper plating layers 24a to 24d can be formed more reliably.

The boundary layer may be provided at the boundary between all the layers, or may be provided only in part of the layers. On the other hand, the boundary layer 24e is not necessarily formed in the sense of forming a boundary with each layer. However, in the present embodiment, the boundary layer 24e is formed for the purpose of improving adhesion between the lower layer and the first copper plating layer 24. When providing a boundary layer, the thickness is 0.05 micrometers or less, and it may not be seen even if a cross section is observed. In addition, such boundary layers 24e to 24h do not correspond to the respective layers of the multilayer structure, and form each layer together with the first to fourth copper plating layers 24a to 24d.

Here, twin crystals are defined as crystals when the crystal grains are adjacent to each other when the crystal grains adjacent to each other are in a positional relationship rotated about 60 ° with <111> as a common rotation axis. The particle size of the twin grains of is defined as twin grain size.

Such twin grain size varies greatly depending on whether the copper plating layer 24 has a multilayer structure, and also changes depending on the conditions of copper plating, the thickness of each layer, and the like.

On the other hand, twin grains have no correlation with grain size and are independent of grain size. For reference, if the crystal grain size is the same plating condition, there is no big change depending on whether or not it is a multilayer.

Here, the twin grain size is obtained by EBSD analysis. The twin grain is identified by cross-sectional observation, approximated to a circle corresponding to the cross-sectional area of the twin grain, and the diameter of the circle is used as the twin grain size of the twin grain. It is computed as an average average value, and unless otherwise indicated, the twin crystal grain size of the copper plating layer 24 shows the average value of the twin crystal grain diameter of the whole multilayer structure.

In addition, as mentioned above, the bilateral aspect ratio is the ratio between the long diameter and the short diameter (short diameter / long diameter) of a specific pair of grains, and unless otherwise specified, the pair grain aspect ratio of the copper plating layer 24 is a pair of whole grains of the multilayer structure. It shows the average value of aspect ratio. On the other hand, the long diameter of the paired grains coincides with the plane direction of each layer, and the short diameter coincides with the thickness direction due to the copper plating layer 24 in the present embodiment having a multilayer structure.

In addition, although a twin grain size and a twin grain aspect ratio can be computed for every layer, when using as a parameter which improves cut resistance, it is good to use the whole twin grain diameter and a twin grain aspect ratio.

On the other hand, in contrast to the twin grain size, the pair grain aspect ratio and the cut resistance of each layer, the twin grain size and the pair grain aspect ratio of the top layer have a high correlation with the cut resistance, the twin grain size of the top layer is 4 μm or less, and the top grain pair aspect ratio is 0.32 or less. In particular, 0.20 to 0.32 are preferable. Thus, if the twin grain size and twin grain aspect ratio of the uppermost layer are in the above-mentioned range, the crack which arises from the surface of a printed wiring board at the time of breakage will stop at the boundary of the uppermost layer and the layer immediately under it, and it will have an effect that it is difficult to grow by a large crack. . On the other hand, the lower limit of the twin crystal grain size obtained by the printed wiring board of this invention is about 0.3 micrometer empirically.

Moreover, 4 micrometers or less are preferable, and the thickness of each layer is 16 micrometers or less, especially 12 micrometers or less, Furthermore, it is more preferable to set it as 10 micrometers or less. This is because the effect of forming a multilayer structure becomes remarkable by keeping the thickness and total thickness of each layer within this range, and the twin grain size tends to be less than 5 µm. On the other hand, it is preferable that the thickness of each layer shall be 1 micrometer or more from a viewpoint of manufacture stability.

In addition, although the thickness of each layer of a multilayered structure may be the same or different, it is preferable to make it thinner so that the layer on the opposite side, ie, the upper layer, is opposite to the underlying layer. For example, it is desirable to increase the number of layers in the upper half than the number of layers in the lower half of the whole. For example, the lower half made into one layer or two layers, and the upper half made into three layers or four layers is mentioned.

[Example]

Next, although an Example of this invention is given and this invention is demonstrated in detail, this invention is not limited by these.

[First Embodiment]

A seed layer was formed by sputtering Ni-Cr (20 at%) to a thickness of 250 GPa on the surface of the pretreatment side of the polyimide film having a thickness of 35 μm. Further, copper was sputtered on the surface of the seed layer to a thickness of 0.3 µm to form a copper thin film layer. Subsequently, a negative dry film resist (manufactured by Asahi Kasei Co., Ltd.) having a thickness of 15 µm was bonded to the copper thin film layer side surface with a laminator.

Subsequently, UV exposure was performed at about 180 mJ / cm <2> using the exposure apparatus (product of Ushio Denki Co., Ltd.) which arrange | positioned the glass photomask which drawn the wiring pattern which consists of wiring of 15 micrometers width by 30 micrometer pitch.

After exposure, development was carried out with a 10% sodium carbonate solution to dissolve the unexposed portions to form photoresist patterns of each pitch.

Thus, the concentration of bis (3-sulfopropyl) disulfide (SPS) was 10 mg / L, and the concentration of diallyldimethylammonium chloride (DDAC) polymer was 40 mg / L on the base tape on which the resist pattern by the photosensitive resin was formed. The ultrathin boundary layer 24e was formed at a temperature of 25 ° C. and a current density of 0.5 A / dm 2 using a copper plating solution having a chlorine concentration of 30 mg / L, a copper concentration of 38.2 g / L, and a sulfuric acid concentration of 100 g / L. Then, the 1st copper plating layer 24a of 2 micrometers thick was formed at the current density of 5 A / dm <2>, and the thickness of the boundary layer 24e and the 1st copper plating layer 24a was 2 micrometers. Similarly, the boundary layer 24f, the second copper plating layer 24b, the boundary layer 24g, the third copper plating layer 24c, the boundary layer 24h, and the fourth copper plating layer 24d are sequentially formed, and have a total thickness of 8 µm. The copper plating layer 24 was formed.

Subsequently, it immersed for 30 second in 50 degreeC peeling liquid which has 2-aminoethanol as a main component, and the resist pattern was peeled off. Subsequently, the copper thin film layer on the substrate was removed by etching with sulfuric acid and hydrogen peroxide-based etching solution. Next, the Ni-Cr layer was melt | dissolved using CH1935 by a MEC company, and the wiring pattern of each pitch was formed.

Second Embodiment

Under the same plating conditions as those of the first embodiment, two layers of the boundary layer and the copper plating layer were formed with the same thickness, and the same procedure as in the first embodiment was carried out except that the two-layer structure had a total thickness of 8 µm.

Third Embodiment

The same process as in the first embodiment was carried out except that six pairs of boundary layers and copper plating layers were formed with the same thickness under the same plating conditions as the first embodiment, and the six-layer structure was made with an overall thickness of 8 占 퐉.

[Example 4]

The same process as in the first embodiment was carried out except that eight pairs of the boundary layer and the copper plating layer were formed with the same thickness under the same plating conditions as the first embodiment, and the eight-layer structure was made with an overall thickness of 8 µm.

[Fifth Embodiment]

The same procedure as in the first embodiment was carried out except that ten layers of the boundary layer and the copper plating layer were formed with the same thickness under the same plating conditions as the first embodiment to form a ten-layer structure having an overall thickness of 8 µm.

[Sixth Embodiment]

12 layers of the boundary layer and the copper plating layer of the same thickness were formed under the same plating conditions as in the first embodiment, and the same procedure as in the first embodiment was carried out except that a 12-layer structure having an overall thickness of 8 µm was formed.

[Example 7]

Under the same plating conditions as in the first embodiment, a pair of boundary layers and a copper plating layer was formed in one layer with a thickness of 4 µm, and then, similarly, five layers were formed in a total of 4 µm with the same thickness. The same procedure as in the first embodiment was carried out except for the above description.

[First Comparative Example]

A wiring pattern was produced in the same manner as in the first embodiment except that copper plating was formed with a copper plating layer of 8 µm at a current density of 5 A / dm 2.

(Test Example 1)

Samples for MIT measurement were formed under the same plating conditions as those of the first to seventh examples and the first comparative example, and the bending angle was ± 135 ° and the bending speed was 175 rpm (312 r / min) for the sample. The MIT test was carried out at R: 0.8 mm and load: 100 gf.

The result of the MIT test was confirmed by disconnection detection by conduction detection, and the number of bendings at the time of disconnection detection was adopted.

The results are shown in Table 1.

From this result, it turned out that the multilayer structure of two or more layers is excellent in the corrosion resistance by the MIT test compared with the 1st comparative example. In addition, it was found that there is no significant correlation between the number of layers and the corrosion resistance of the multilayer, and the resistance to corrosion is not remarkably improved even beyond eight layers. Therefore, it can be seen that two to eight layers, preferably four layers, are good.

Further, the seventh embodiment in which the laminated structure formed of a relatively thin layer is formed on the upper half is the same layer as the layer thickness of the third embodiment (the whole six-layer structure) or the fifth embodiment (the upper half of the seventh embodiment). Compared to the 10th floor), it was found to be remarkably excellent in corrosion resistance. From this, it is preferable to set it as the structure which laminated | stacked the thin layer on the upper side rather than lower side, and it turned out that having only the upper side as the multilayered structure of a thin film, it is more excellent in abrasion resistance.

Number of layers MIT test results First embodiment 4 131 Second embodiment 2 129 Third embodiment 6 126 Fourth embodiment 8 134 Fifth Embodiment 10 127 Sixth embodiment 12 127 Seventh Embodiment 6 135 Comparative Example 1 One 120

(Test Example 2)

Table 2 shows the results of the EBSD analysis for the first, second, seventh examples, and the first comparative example. EBSD (Electron Back Scatter Diffraction Patterns) analysis was performed by cross-sectional processing with a microtome along the length of the wiring, and then etched with FIB to produce a sample for observation.

Detailed analysis conditions are as follows. In addition, the cross-sectional photograph of a 1st Example and a 1st comparative example is shown in FIG.

EBSD interpretation

Device: Scanning electron microscope (Zeiss SUPRA ^TM 55VP)

        EBSD Department (EDAX Corporation Pegasus System)

Observation sample: 70 degree inclination in the sample table

Observation magnification: 5000 times

Observation field of view: 10 x 30 mm

WD (Working Distance) about 15mm

Recognition as grain boundary when there is an azimuth difference of 2 ° or more

Measurement software: TSL OIM Data Collection 5

Analysis software: TSL OIM Analysis 5.1

As a result, it was clear from the cross-sectional photograph that the first embodiment had a multilayer structure.

As a result of the EBSD analysis, in the first, second and seventh embodiments of the multilayer structure, the twin crystal grain size of the copper plating layer (whole) was less than 5 µm and the twin grain aspect ratio was less than 0.45. It was found that the twin grain size is 5 µm or more and the twin grain aspect ratio is 0.45 or more. In addition, although the bieraxial aspect ratio is 0.43 in the 2nd Example, it turned out that it is 0.32 and 0.40 in the range of 0.3-0.4 in the 1st and 7th Example which was more excellent in abrasion resistance.

Further, in the first, second and seventh examples, it was found that the twin grain size of the uppermost layer was 4 µm or less, and the twin grain aspect ratio of the uppermost layer was 0.32 or less and in the range of 0.20 to 0.32.

all The first floor 2nd floor 3rd floor 4th floor 5th floor 6th floor
First
Example Twin grain size
(Μm) 4.20 2.72 4.72 4.86 2.65 Twin
Aspect ratio 0.32 0.43 0.30 0.28 0.24
2nd
Example Twin grain size
(Μm) 4.16 3.59 3.96 Twin
Aspect ratio 0.43 0.47 0.30
7th
Example Twin grain size
(Μm) 3.44 3.10 1.59 1.12 1.82 1.38 1.17 Twin
Aspect ratio 0.40 0.43 0.46 0.39 0.34 0.39 0.31
First
Comparative example Twin grain size
(Μm) 5.31 Twin
Aspect ratio 0.45

1 printed wiring board
2 sprocket holes
3 solder resist layer
10 insulation materials
20 wiring patterns
21 seed layer
22 Copper Thin Film Layer
23 basement layers
24 Copper Plating Layer
31 Photoresist Layer
32 photomask
33 resist pattern

Claims (8)

As a printed wiring board which has a wiring pattern which consists of a base layer and the copper plating layer formed by the semiadditive method on the surface of an insulating base material,
The said copper plating layer has a multilayered structure, and the twin wiring diameter is less than 5 micrometers, The printed wiring board characterized by the above-mentioned. The method of claim 1,
The thickness of each layer of the said multilayer structure is 4 micrometers or less, The printed wiring board characterized by the above-mentioned. The method of claim 1,
The bidirectional aspect ratio of the copper plating layer is less than 0.45. The method of claim 1,
A printed wiring board, characterized in that a boundary layer formed at a lower current density than the current density of plating at the time of forming each layer is provided on the lower surface of each layer in the multilayer structure in the stacking direction. The method of claim 1,
Each layer of the said multilayer structure is thinner on the upper side than the layer of the lower side of a lamination | stacking direction. The printed wiring board characterized by the above-mentioned. The method according to any one of claims 1 to 5,
A printed wiring board, characterized in that the layer on the uppermost surface in the stacking direction of the multilayer structure is the thinnest. A concave portion for exposing the underlying layer is formed by forming a conductive underlayer on the surface of the insulating substrate, and forming a photoresist layer on the surface of the underlayer and exposing and developing a predetermined pattern on the photoresist layer. And forming a copper plating layer on the underlayer of the concave portion, then peeling the patterned photoresist layer, and subsequently removing the underlayer exposed by the exfoliation of the photoresist layer to form a wiring pattern. In
The plating of the copper plating layer is carried out in multiple stages, so that the copper plating layer has a multi-layered structure, and a twin grain size is less than 5 µm. The method of claim 7, wherein
A method for manufacturing a printed wiring board, wherein a boundary layer is formed at a current density lower than the current density of the plating of each layer between the plating divided into the multi-stage.

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