JP2001332855A - Method for manufacturing multi-layered wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a multi-layered wiring board which is superior in the formation precision of a conductor pattern and superior in control over the insulating layer thickness of a built-up layer without decreasing connection reliability. SOLUTION: This method has a stage for stacking and integrating resin layers on the top and reverse surfaces of plural conductor pattern layers, a stage for forming through holes penetrating the conductor pattern layers, a stage for forming a circuit board by depositing a conductor on the internal wall of the through hole, a stage for forming a stack plate which has nonwoven fabric prepreg laminated integrally on at least one of the top and reverse surfaces of the circuit board, the through holes charged with nonwoven fabric prepreg, and a build-up layer formed on at least one surface of the circuit board, a stage for forming a hole where an internal-layer circuit is exposed selectively in the built-up layer, a stage for depositing a conductor on the internal wall of the hole, and a stage for forming a conductor pattern connected to the internal layer circuit on the built-up layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a multilayer wiring board, and more particularly to a method for manufacturing a multilayer wiring board using a nonwoven fabric prepreg for forming a through hole and a build-up layer.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and high performance of electronic devices, surface mount components (hereinafter, referred to as "SM") on multilayer wiring boards have been developed.
D "), the mounting density of the conductive patterns of the mounting terminals has been increasing.

In a method of manufacturing a multilayer wiring board, as a method of forming a conductor pattern such as a connection terminal or a circuit, an etching resist is formed in a required shape on a surface of a copper foil.
There is a so-called subtract method in which an unnecessary portion of the copper foil is removed by etching by spraying a chemical etching solution.
When this subtraction method is used, the lower area of the conductor pattern is larger than the upper area. In other words, the cross-sectional shape of the conductor pattern becomes trapezoidal, and the greater the thickness of the conductor pattern, the greater the difference between the upper and lower areas. Therefore, when the precision of the conductor pattern is required to mount a high-density SMD, the thickness of the conductor pattern is reduced as much as possible.

Another method for forming a conductor pattern is an additive method. The additive method is a method of forming a conductive pattern by forming a plating resist image at a place where a conductive pattern is not formed on an insulating substrate, and depositing electrolessly plated copper just before that. Unlike the subtractive method, according to the additive method, it is possible to form a conductor pattern having a rectangular cross-sectional shape such that the upper area and the lower area are substantially equal. In this additive method, when the accuracy of the conductor pattern is required, since the accuracy of forming the plating resist image is inversely proportional to its thickness, it is necessary to reduce the thickness of the plating resist image, and accordingly, it is formed. The thickness of the conductor pattern is also limited.

[0005]

Incidentally, a multilayer wiring board used in the fields of supercomputers, semiconductor device inspection, and the like has, for example, 20 or more layers and a plate thickness of 5 or more.
High-density and high-layer materials of mm or more are sometimes used. In such a high-density, high-layered multilayer wiring board, it is necessary to increase the thickness of the inner layer copper deposited on the inner wall of the through hole penetrating between the wiring layers as much as possible in order to ensure the connection reliability of the connection terminals. In addition, in the conventional methods such as the subtraction method and the additive method, it is difficult to increase the thickness of the conductor pattern, which is the thickness of the inner copper layer, and to increase the precision.

Generally, in a multilayer wiring board, it is necessary to uniformly control the thickness of an interlayer insulating film in order to make the characteristic impedance of a wiring path constant. However, the plate thickness is 5mm
If the above-mentioned high-density, high-layer multilayer wiring board is filled with through-holes and formed with a build-up layer by using an adhesive film with copper foil, etc. by batch pressing, the insulating film of the build-up layer It is difficult to control the thickness uniformly.

When the filling of the through-holes and the formation of the build-up layer are performed by a batch press using a glass woven fabric prepreg or the like, it is possible to control the insulating film thickness of the build-up layer uniformly. In addition, it is difficult to form a hole for electrically connecting the surface circuit and the inner layer circuit with a laser.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and it is an object of the present invention to improve the precision of forming a conductive pattern without lowering the connection reliability and to improve the build-up. An object of the present invention is to provide a method for manufacturing a multilayer wiring board excellent in controlling the thickness of an insulating layer.

[0009]

In order to achieve the above object, the features of the present invention are as follows. (1) A resin layer is superimposed on the front and back surfaces of one or more conductor pattern layers, and the resin layers are pressurized and heated. (2) a second step of forming an inner layer circuit on the laminated and integrated resin layer;
(3) a third step of forming a through hole penetrating through the conductor pattern layer and the resin layer; and (4) a conductor is deposited on the inner wall of the through hole, and the conductor pattern layer and the inner layer circuit are electrically connected to each other. A fourth step of forming the circuit board, and (5) the nonwoven fabric prepreg is stacked on at least one of the front and back surfaces of the circuit board, and is pressurized and heated to be laminated and integrated, and the through holes are filled with the nonwoven fabric prepreg; (5) a fifth step of forming a laminate having a build-up layer formed on at least one surface of the circuit board, (6) a sixth step of selectively forming holes in which the inner-layer circuits are exposed in the build-up layer, and (7) A) a seventh step of depositing a conductor on the inner wall of the hole and (8) an eighth step of forming a conductor pattern connected to the inner layer circuit on the build-up layer. is there. Here, the “conductor pattern layer” includes a flat insulating substrate and a predetermined conductive pattern disposed on the insulating substrate.

According to the feature of the present invention, the thickness of the build-up layer can be made uniform by filling the through holes with the non-woven prepreg and forming the build-up layer. Therefore, the characteristic impedance of the conductor pattern of the multilayer wiring board can be kept constant. At the same time, the thickness of the conductor deposited on the inner wall of the through hole can be made smaller than the thickness of the conductor deposited on the inner wall of the through hole, so that the connection reliability of the conductor deposited on the inner wall of the through hole is not reduced. A conductor pattern with high formation accuracy can be formed on the build-up layer.

[0011] In the features of the present invention, the nonwoven fabric prepreg is desirably a glass nonwoven prepreg. Alternatively, the nonwoven prepreg may be an organic fiber nonwoven prepreg. The number of conductor pattern layers is arbitrary. Furthermore, it is desirable that the nonwoven fabric prepreg be pressed and heated by overlapping the necessary number of places for filling the through holes and forming the build-up layer. In other words, if one nonwoven fabric prepreg is insufficient for filling the through holes and forming the build-up layer, it is desirable to stack two or more sheets. If only one of the front and back surfaces of the circuit board is insufficient, It is desirable to overlap the nonwoven fabric prepreg on both sides.

[0012]

(Embodiment 1) Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view illustrating the configuration of the multilayer wiring board according to the first embodiment. As shown in FIG. 1, the multilayer wiring board 12 according to the first embodiment is formed by laminating and integrating a plurality of conductor pattern layers 1 and a plurality of resin layers 2 respectively disposed on the front and back surfaces of the conductor pattern layer 1. A through hole 4 penetrating through the plurality of conductor pattern layers 1 and the resin layer 2; an inner layer circuit 10 formed on the front and back surfaces of the plurality of conductor pattern layers 1 and the resin layer 2 which are laminated and integrated; A conductor that is deposited on the inner wall and electrically connects between the different conductor pattern layers 1 and the inner layer circuit 10, a build-up layer 16 stacked on the inner layer circuit 10, and formed on the build-up layer 16 And a conductor pattern 11. The conductive pattern layer 1 includes a flat insulating substrate and conductive patterns arranged on the front and back surfaces of the insulating substrate.
The inside of the through hole 4 is filled with a nonwoven fabric prepreg, which is the same material as the buildup layer 16. Conductor pattern 1
1 and the inner layer circuit 10 are connected via a conductor deposited on the inner wall of the hole 9 formed in the build-up layer 16.

Next, a method of manufacturing the multilayer wiring board 12 shown in FIG. 1 will be described with reference to FIGS. 2A to 2E are process cross-sectional views illustrating main processes in the method for manufacturing the multilayer wiring board 12 according to the first embodiment of the present invention. The cut surfaces in FIGS. 2A to 2E are:
It corresponds to the cut surface in FIG.

(A) First, a glass cloth polyimide resin copper-clad laminate M in which copper foil is deposited on the front and back surfaces of a flat insulating plate.
A plurality of CL-I-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is prepared. On the surface of these glass cloth polyimide resin copper-clad laminates, an etching resist film HP-
250 (manufactured by Hitachi Chemical Co., Ltd., trade name). The etching resist film is irradiated with ultraviolet rays through a photomask and developed to form an etching resist having the same shape as a predetermined conductor pattern (inner circuit pattern). Using the etching resist as a mask, the copper foil is selectively etched away to form a plurality of conductor pattern layers 1 on which predetermined conductor patterns are arranged on the front and back surfaces of the insulating plate, as shown in FIG. . Note that FIG.
In the first embodiment as shown in (a) to (e), the case where the number of the conductor pattern layers 1 is three will be continued, but the present invention is not limited to this, and the number of layers is smaller or larger than this. It may be. After that, the etching resist is peeled off. Three conductor pattern layers 1
, Four resin layers 2 are respectively superposed on the front and back surfaces, and a copper foil 3 is further superimposed on the outer side of the outermost resin layer 2 at a pressure of 2.94M.
The layers are integrated under the conditions of pa, a temperature of 175 ° C. and 90 minutes.
The three conductor pattern layers 1, the four resin layers 2, and the copper foil 3 that are laminated and integrated are referred to as a circuit board 5. In addition, the resin layer 2
Is a glass cloth polyimide resin prepreg GIA-67
(Trade name, manufactured by Hitachi Chemical Co., Ltd.). FIG. 2A is a diagram showing an arrangement relationship of each layer (1, 2, 3) of the circuit board 5 before lamination and integration.

(B) Next, as shown in FIG. 2 (b), through holes 4 penetrating the front and back surfaces of the circuit board 5 are formed at predetermined positions using a numerically controlled drilling machine. 30 electroless plating
The required conductor (copper foil) is deposited on the inner wall of the through-hole 4 and the front and back surfaces of the circuit board 5 by performing electro-copper plating of 20 μm. Etching resist film HP-2 on copper foil 3
50 is laminated, irradiated with ultraviolet rays through a photomask, and developed to form an etching resist having the same shape as the inner layer circuit 10. Using this etching resist as a mask, the copper foil 3 is selectively removed by etching to form the inner layer circuit 1.
0 is formed. After that, the etching resist is peeled off. The copper foil deposited on the inner wall of the through hole 4 connects the inner layer circuit 10 and the plurality of inner layer circuit patterns (conductor pattern layers 1). Through the above steps, FIG.
As shown in (b), a circuit board 5 having a through-hole 4 penetrating the plurality of stacked conductor pattern layers 1 and having a thickness of about 5 mm can be formed.

(C) Next, as shown in FIG. 2 (c), a nonwoven fabric prepreg 6 is laminated on the front and back surfaces of the circuit board 5, and a copper foil 7 having a thickness of 12 μm is laminated on the outside of the prepreg. Laminate and integrate. As shown in FIG. 2D, the nonwoven fabric prepreg 6
Of the nonwoven fabric prepreg 6
Are build-up layers 1 remaining as spacers between the inner layer circuit 10 and the copper foil 7 and deposited on the front and back surfaces of the circuit board 5.
6 are formed. The circuit board 5, the nonwoven fabric prepreg 6, and the copper foil 7 which are laminated and integrated are referred to as a laminate 8. Through the above steps, the nonwoven fabric prepreg 6 and the copper foil 7 are superimposed on the front and back surfaces of the circuit board 5 and pressurized and heated to laminate and integrate,
Filling of the through holes 4 and formation of the build-up layer 16 can be performed by a batch press. In addition, the nonwoven fabric prepreg 6
Uses glass nonwoven epoxy prepreg GEA-679P (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a kind of glass nonwoven prepreg. FIG. 2 (c)
It is a figure which shows the arrangement | positioning relationship of each layer (5, 6, 7) of the laminated board 8 before lamination and integration.

(D) Next, an etching resist film HP-250 is laminated on the front and back surfaces of the laminate 8. Using a photolithography method, ultraviolet rays are irradiated through a photomask and developed, and the holes 9 shown in FIG.
An etching resist having a window in a region where it is desired to form is formed. Using this etching resist as a mask, copper foil 7
Is selectively removed by etching. Using LCO-1B21 (trade name, manufactured by Hitachi Via Mechanics Co., Ltd.) which is a carbon dioxide laser drilling machine, a frequency of 500
Hz, pulse width of 12 μs, beam diameter φ of 0.2 mm, and irradiation with a laser beam under the conditions of eight shots, to selectively remove the hardened epoxy resin at the position of the hole 9 and the build-up layer 16 which is a glass nonwoven fabric base material. Then, as shown in FIG. 2 (e), a hole 9 where the inner layer circuit 10 is exposed is formed. After that, the etching resist is peeled off.

(E) Next, an electroless copper plating solution having the following composition is used to perform electroless copper plating under the following conditions, and a 12 μm-thick conductor ( (Copper foil).

<Composition of electroless copper plating solution and conditions of use> CuSO ₄ .5H ₂ O 10 g / liter EDTA 4Na 40 g / liter 37% CH ₂ O 3 mg / liter ・ pH: 12.4 ・ Liquid temperature: 70 ° C. (F) Next, an etching resist film HP-250 is laminated on the front and back surfaces of the laminated plate 8, and the same as the conductive pattern 11 by photolithography. An etching resist having a shape is formed. Using this etching resist as a mask, the copper foil is selectively etched away to form a conductor pattern 11. The conductor pattern 11 has holes 9
Is connected to the inner layer circuit 10 via a copper foil deposited on the inner wall of the internal circuit. After that, the etching resist is peeled off. Finally, the outer shape is processed by the numerical control router,
Can be manufactured.

According to the multilayer wiring board 12 according to the first embodiment, the nonwoven fabric prepreg 6 is attached to the circuit board 5 having the through holes 4.
Are laminated and integrated by pressurizing and heating, a part of the nonwoven fabric prepreg 6 is filled in the through hole 4, and the remaining nonwoven fabric prepreg 6 is built up layer 16 deposited on the front and back surfaces of the circuit board 5. To form The thickness of the build-up layer 16 can be made uniform, and the holes 9 for interlayer connection can be formed by laser. Since the build-up layer 16 serving as a spacer between the inner layer circuit 10 and the conductor pattern 11 (outermost layer copper foil) can be formed uniformly, the characteristic impedance of the wiring path of the multilayer wiring board 12 can be kept constant. it can.

The multilayer wiring board 12 has two kinds of holes, a hole 9 for connecting the outermost conductor pattern 11 and the inner layer circuit 10 adjacent thereto and a through hole 4 for connecting between the inner layer conductor patterns. Have. The thickness (12 μm) of the conductor deposited on the inner wall of the hole 9 is formed smaller than the thickness (50 μm) of the conductor deposited on the inner wall of the through hole 4 connecting the conductor patterns of the inner layer. Of the conductor pattern 11 without lowering the connection reliability of the conductor deposited on the inner wall of the conductor pattern 11.
Can be formed more accurately.

The number of conductor pattern layers 1 and the type of insulating material in the multilayer wiring board 12 according to the first embodiment are as follows.
The present invention is not limited to the present invention, and may be a multilayer wiring board having an arbitrary number and types of layers. When the circuit board 5, the nonwoven fabric prepreg 6, and the copper foil 7 shown in FIG. 2 (c) are laminated and integrated by pressurizing and heating, a single nonwoven fabric prepreg can be inserted into the through hole 4 for interlayer connection. When resin filling cannot be performed sufficiently, a plurality of nonwoven fabric prepregs 6 may be stacked and pressurized and heated by the number required for resin filling. Conversely, when the resin can be sufficiently filled in the through-holes 4 without overlapping the nonwoven fabric prepreg 6 on the front and back surfaces of the circuit board 5, the nonwoven fabric prepreg 6 may be arranged on only one surface of the circuit board 5. In this case, the build-up layer 16 is formed only on one side of the multilayer wiring board 12. Further, as the nonwoven fabric prepreg 6, a glass nonwoven epoxy prepreg GEA-
Although a glass nonwoven fabric prepreg such as 679A was used, an organic fiber nonwoven fabric prepreg may be used instead.

(Comparative Example 1) The inventors have studied a multilayer wiring board according to Example 1 shown in FIG. 1 and a multilayer wiring board according to the following two comparative examples (Comparative Example 1 and Comparative Example 2). , A connection reliability test was performed to verify the superiority of the connection reliability of the multilayer wiring board according to the first embodiment. First, 2
A method for manufacturing a multilayer wiring board and the like according to two comparative examples will be described. In the description of the comparative example, the same portions as those in the method for manufacturing the multilayer wiring board according to the first embodiment are described, and the description is omitted. 3 (a) to 3 (f)
FIG. 9 is a process cross-sectional view showing main processes in the method for manufacturing the multilayer wiring board according to Comparative Example 1. 3A to 3F, the same parts in FIG. 1 are denoted by the same reference numerals.

(A) First, using three glass cloth polyimide resin copper-clad laminates MCL-I-67, FIG.
As shown in (3), three conductor pattern layers 1 on which predetermined conductor patterns are arranged are formed on the front and back surfaces of the insulating plate. Then, four resin layers 2 are formed on the front and back surfaces of the three conductor pattern layers 1.
And further, a copper foil 3 is layered on the outer side of the outermost resin layer 2, the pressure is 2.94 Mpa, the temperature is 175 ° C., 90
The circuit board 5 is formed by laminating and integrating under the conditions of minutes. The resin layer 2 is made of glass cloth polyimide resin prepreg G
Use IA-67. FIG. 3A is a diagram showing an arrangement relationship of each layer (1, 2, 3) of the circuit board 5 before lamination and integration.

(B) Next, as shown in FIG. 3B, a through hole 4 penetrating the front and back surfaces of the circuit board 5 is formed. Then, electroless plating is 30 μm and electrolytic copper plating is 20 μm.
Then, copper foil is deposited on the inner wall of the through hole 4 and the front and back surfaces of the circuit board 5. Etching resist film H on copper foil 3
Using P-250, an etching resist having the same shape as the inner layer circuit 10 is formed. The inner layer circuit 10 is formed using this etching resist. The above steps (a) and (b) are the same as those in the first embodiment. The circuit board 5 having a thickness of about 5 mm shown in FIG. 3B is the same as the circuit board 5 shown in FIG. Things.

(C) Next, in place of the nonwoven fabric prepreg 6 and the copper foil 7 in Example 1, as shown in FIG.
F-6000E (trade name, manufactured by Hitachi Chemical Co., Ltd.) 1
3 are stacked, pressurized and heated, and laminated and integrated. FIG. 3 (d)
As shown in (1), a part of the adhesive film 13 is filled in the through hole 4, and the remaining adhesive film 13 forms a build-up layer 16 deposited on the front and back surfaces of the circuit board 5. The laminated circuit board 5 and the adhesive film 13 are laminated on a laminate 14.
That. FIG. 3C is a diagram showing the arrangement relationship of each layer (5, 13) of the laminated plate 14 before lamination and integration.

(D) Next, by the same method as in the first embodiment, a hole 9 exposing the inner layer circuit 10 shown in FIG. 3E is formed. Then, a copper foil having a thickness of 12 μm is deposited on the front and back surfaces of the laminate 14 and the inner wall of the hole 9 under the same conditions as in the first embodiment.

(E) Next, in the same manner as in Example 1, the copper foil of the adhesive film 13 is selectively removed by etching to form the conductor pattern 11. Finally, the outer shape is processed by the numerical control router, and the multilayer wiring board 15 as shown in FIG. 3F can be manufactured.

(Comparative Example 2) A multilayer wiring board according to Comparative Example 2 is the circuit board 5 shown in FIG. That is, the circuit board 5 manufactured by the method described below.

First, using three glass cloth polyimide resin copper-clad laminates MCL-I-67, as shown in FIG. The conductor pattern layer 1 is formed. Then, the four resin layers 2 are respectively superposed on the front and back surfaces of the three conductor pattern layers 1, and the copper foil 3 is further superimposed on the outside of the outermost resin layer 2, and are laminated and integrated to form the circuit board 5. In addition,
The resin layer 2 is made of glass cloth polyimide resin prepreg GIA.
Use -67. FIG. 4A is a diagram showing an arrangement relationship of each layer (1, 2, 3) of the circuit board 5 before lamination and integration.

Next, as shown in FIG. 4B, a through hole 4 penetrating the front and back surfaces of the circuit board 5 is formed. Electroless plating is performed by 30 μm and electrolytic copper plating is performed by 20 μm, and copper foil is deposited on the inner wall of the through hole 4 and the front and back surfaces of the circuit board 5. An etching resist having the same shape as that of the inner layer circuit 10 is formed on the copper foil 3 using an etching resist film HP-250. Inner layer circuit 1 using this etching resist
0 is formed. Through the above steps, a circuit board 5 having a thickness of about 5 mm as shown in FIG. 4B can be formed.

(Test Results) Next, the results of a connection reliability test performed by the inventor on the multilayer wiring boards and the like according to Example 1 and Comparative Examples 1 and 2 will be described. Table 1 shows the specifications of the multilayer wiring board and the like according to Example 1 and Comparative Examples 1 and 2, and test results of connection reliability.

[0033]

[Table 1] As shown in Table 1, the thicknesses of the multilayer wiring boards and the like according to Example 1 and Comparative Examples 1 and 2 are all 5 mm. The conductor pattern (front surface circuit) exposed on the front and back surfaces of the multilayer wiring board and the like is the conductor pattern 11 formed from the copper foil 7 in Example 1, and the copper pattern of the adhesive film 13 in Comparative Example 1. This is the conductor pattern 11 formed from a foil. The conductor thickness of each of these conductor patterns 11 is 24 μm.
m. On the other hand, the surface circuit of Comparative Example 2 is the internal circuit 10 formed from the copper foil 3. The conductor thickness of the internal circuit 10 is 68 μm. The line / space of the conductor pattern 11 is 60 μm / 60 μm, and the line / space of the internal circuit 10 is 120 μm / 130 μm. The diameters of the through holes 4 are all 0.4 mm, and the number of the through holes 4 is all 1,000. In Example 1 and Comparative Example 1, the holes (non-through holes) 9 connecting the conductor pattern 11 and the internal circuit 10 each had a diameter of 0.15 mm, and the number of holes was 50 each.

The connection reliability test method and test conditions are MIL
-According to STD-202 Method 107B. That is, 30 minutes at −65 ° C./5 minutes at 25 ° C./30 minutes at 125 ° C.
The heat cycle was repeated for 5 minutes / 25 ° C./5 minutes, and the evaluation was performed by the number of cycles until 10% increase from the initial connection resistance value. The number of cycles indicating the connection reliability is 150 cycles for the circuit board 5 according to Comparative Example 2, while
In Example 1 and Comparative Example 1, good results of 150 cycles or more were obtained. The thickness of the build-up layer 16 is
Comparative Example 1 has a thickness of 30 to 110 μm, whereas Example 1
Was 90 to 110 μm. Example 1 compared to Comparative Example 1
It was verified that a more uniform buildup layer 16 was formed. That is, in the method for manufacturing the multilayer wiring board according to the first embodiment, the line / space = 60 μm / 60 μm
It has been verified that a multi-layer wiring board having good fine wiring formation and connection reliability, and having a small variation in the thickness of the insulating layer can be formed.

As described above, according to the present invention, it is possible to provide a multilayer wiring board which has good fine wiring formation and connection reliability, and has a small thickness variation of the insulating layer.

[0036]

As described above, according to the present invention, there is provided a multilayer wiring board having excellent conductor pattern formation accuracy and excellent control of the build-up layer insulating layer thickness without reducing connection reliability. A manufacturing method can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a multilayer wiring board according to Embodiment 1 of the present invention.

FIGS. 2A to 2E are process cross-sectional views illustrating main processes in a method for manufacturing a multilayer wiring board according to Embodiment 1 of the present invention.

FIGS. 3A to 3F are process cross-sectional views illustrating main processes in a method for manufacturing a multilayer wiring board according to Comparative Example 1. FIGS.

FIGS. 4A and 4B are process cross-sectional views illustrating main processes in a method for manufacturing a circuit board according to Comparative Example 2. FIGS.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 conductor pattern layer 2 resin layer 3, 7 copper foil 4 through hole 5 circuit board 6 non-woven fabric prepreg 8, 14 laminate 9 hole 10 inner layer circuit 11 conductor pattern 12, 15 multilayer wiring board 13 adhesive film

Continued on the front page (72) Inventor Shigeharu Ariya 1500 Oji Ogawa, Shimodate-shi, Ibaraki F-term in Hitachi Chemical Industry Research Laboratory (reference) 5E346 AA42 CC04 CC10 CC32 DD23 DD44 DD48 EE09 EE13 EE38 GG09 GG15 GG18 GG28 HH03

Claims (3)

[Claims] A first step of laminating resin layers on the front and back surfaces of one or more conductor pattern layers, and pressing and heating to laminate and integrate the resin layers; and A second step of forming an inner layer circuit, a third step of forming a through-hole penetrating the conductor pattern layer and the resin layer, and depositing a conductor on an inner wall of the through-hole. A fourth step of forming a circuit board in which the inner layer circuits are electrically connected to each other, and a nonwoven prepreg is laminated on at least one of the front and back surfaces of the circuit board, and the laminate is integrated by pressing and heating, A fifth step of forming a laminated board in which the through-hole is filled with the nonwoven fabric prepreg and a build-up layer is formed on at least one surface of the circuit board, and selectively building up the hole in which the inner-layer circuit is exposed; Shape into layers A sixth step of depositing a conductor on the inner wall of the hole, and an eighth step of forming a conductor pattern connected to the inner layer circuit on the build-up layer. A method for manufacturing a multilayer wiring board. 2. The method according to claim 1, wherein the non-woven fabric prepreg is a glass non-woven fabric prepreg. 3. The method according to claim 1, wherein the non-woven fabric prepreg is an organic fiber non-woven fabric prepreg.