TW200301937A - Silicon on insulator device with improved heat removal and method of manufacture - Google Patents
Silicon on insulator device with improved heat removal and method of manufacture Download PDFInfo
- Publication number
- TW200301937A TW200301937A TW091132396A TW91132396A TW200301937A TW 200301937 A TW200301937 A TW 200301937A TW 091132396 A TW091132396 A TW 091132396A TW 91132396 A TW91132396 A TW 91132396A TW 200301937 A TW200301937 A TW 200301937A
- Authority
- TW
- Taiwan
- Prior art keywords
- silicon
- layer
- substrate
- silicon oxide
- metal
- Prior art date
Links
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 38
- 239000010703 silicon Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000012212 insulator Substances 0.000 title claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 title description 8
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 3
- 239000004575 stone Substances 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims 2
- 229910000831 Steel Inorganic materials 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 238000005121 nitriding Methods 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- CHWRSCGUEQEHOH-UHFFFAOYSA-N potassium oxide Chemical compound [O-2].[K+].[K+] CHWRSCGUEQEHOH-UHFFFAOYSA-N 0.000 claims 1
- 229910001950 potassium oxide Inorganic materials 0.000 claims 1
- 239000010959 steel Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 36
- 230000000873 masking effect Effects 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005299 abrasion Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- AHKZTVQIVOEVFO-UHFFFAOYSA-N oxide(2-) Chemical compound [O-2] AHKZTVQIVOEVFO-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
200301937 ⑴ 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 技術領域 本發明是有關於半導體裝置及其製造方法，尤其，本發 明是有關於在碎上絕緣體（SOI)結構中製造出這些的裝置。 先前技術 可以在半導體裝置中，藉製造出矽上絕緣體結構中的裝 置，而達成較低寄生組件，比如矽上藍寶石與矽上氧化物 絕緣體，包括能以商品方式取得的黏結矽上絕緣體以及離 子佈植氧化物（SIM0X)。這些結構中，支撐基底通常是黏結 到散熱座以去移除熱，對於功率電晶體結構尤其重要。此 外，可以在基底表面上進行金屬化，提供接地面。 本發明是一種製造矽上絕緣體結構的改良方法，改善熱 的移除以及電路接地組合，包括低電阻接地路徑。 發明内容 依據本發明，在矽上絕緣體（SOI)基底内製造出一種半導 體裝置，包括被支撐的矽基底，該基底所支撐的氧化矽層， 以及覆蓋在該氧化矽層的矽層。尤其，如電晶體或電容器 的電氣組件，例如，是在部分矽氧化物層上的矽層中製造 出來，然後對與該組件相反的基底進行光罩與蝕刻處理。 然後利用蝕刻，在已經被去除掉的部分基底内形成金屬 層，使用金屬層提供從組件上移除掉熱。在另一實施例中， 將覆蓋在-部分基底上的氧化矽層去除掉，而該金屬層是緊 鄰矽層。 製造該裝置時，可以利用優先触刻，以氧化碎當作触刻 200301937
法，以最後 (2) 阻止來去除掉基底内的矽。可以使用二步騾方 的蝕刻處理為最優先。然後，可以利用氧化矽的優先姓刻 劑，去除掉曝露出的氧化石夕，如同在另一實施例中的。 例如，可以在基底表面上形成硬質光罩的氮化矽，供碎 蝕刻用。紅外線光罩對齊或鏡面對齊都可以在對氮化碎進 行光罩以及蝕刻處理而形成硬質光罩中使用。金屬層最好 是包括用金所覆蓋住的高熔點金屬。可以使用晶圓磨擦讓 基底在進行光罩與蝕刻處理之前便先變薄。 本發明之目的及特徵，在以下的詳細說明、專利申請範 圍及圖式說明中將會更加的明顯。
圖式簡單說明 I 圖1A-1D是顯示出依據本發明實施例製造出半導體裝置 之步驟的剖示圖。 圖2 A-2C是顯示出依據本發明另一實施例製造出半導體 裝置之步驟的剖示圖。 圖3A-3C是顯示出可以依據本發明實施例在半導體裝置 内製造之已知電氣組件的剖示圖。 實施方式 圖1A-1D是顯示出依據本發明實施例製造出矽上絕緣體 裝置之步騾的剖示圖。在圖1 A中，提供可以是黏結矽或氧 化物離子佈植矽的SOI結構，其中矽基底1〇支撐住氧化矽層 12，而矽層14是在氧化矽層12上。這些s〇I結構是眾所周知 的，而且能以商品方式取得，於半導體裝置製造中使用。 如同圖1 B中所示的’電氣組件丨6是在矽層丨4内，使用傳 (3) (3)200301937
統的光阻光罩，蝕刻以及摻雜技術而製造出來。組件1 6可 以是任何半導體裝置，比如：如圖3A剖示圖的側向dm〇s 電晶體’如圖3 B剖示圖的雙載子電晶體，或如圖3 c叫示圖 的電容器與變容器。這些半導體裝置以及其它的半導體裝 置都是眾所周知的，而且製造這些裝置都使用傳統的半導 體處理技術。 如同圖1 B的進一步顯示，氮化矽或氧化物/氮化物夫心層 1 8是在與組件1 6相反侧的基底1 0表面上形成，在姓刻摔基 底1 0時當作硬質光罩用，進行選擇性的光罩與蝕刻處理， 如圖1 C所示。優點是，如氫氧化鉀的優先蝕刻劑或如cF4+〇2 的乾電漿蝕刻，可以用來蝕刻掉基底10内的矽，用氧化石夕 層1 2當作蝕刻阻止，進而避免過度蝕刻到矽層丨4内。 藉此，如圖1D所示，高熔點金屬層20是沉積在基底1〇表 面上，並沉積在緊鄰到氧化矽層1 2的蝕刻部分内。任何的 已知高溶點金屬都可以使用’比如鈥鎢與氮化鈦。然後高 熔點金屬層2 0被金屬層2 2覆蓋住，比如金，銅或鋁，可以 在後續中重疊而在基底10的表面上形成平面金屬表面。優 點是，藉去除掉組件16底下的基底材料，讓薄層2〇與22的 金屬散熱片更加靠近組件16，並方便移除掉熱。金屬層也 可以當作給該組件用的接地。基底電阻也會降低。 圖2A-2C是顯示出本發明另一實施例的剖示圖。如圖1 b所 示，在製造組件1 6之後，但在形成氮化矽層18之前，磨擦 基底1 〇而讓基底變薄，並降低曝露出氧化矽層1 2所需要的 後績蚀刻量，如圖2A所示。 200301937 (4) I舞織德萌讀貰 圖2 A的結構可以做進一步蝕刻，如圖2B所示，藉使用優 先蝕刻劑的氧化矽，比如濕式缓衝HF酸或乾式電漿蝕刻， 以便去除掉不只是一部分的基底1 0，還有在組件1 6底下的 曝露氧化矽層1 2。在該實施例中，金屬層20與22緊鄰到組 件1 6底下的矽層1 4，進而方便移除熱，並可以隨時當作該 組件的接地，也會降低基底的電阻。 依據本發明的裝置已經將金屬放到組件熱源的附近而降 低其熱阻，並降低因金屬很靠近主動電晶體所引起的基底 電阻。優點是，該方法使用在二層矽層之間的氧化矽層當 作蝕刻阻止，讓厚基底的蝕刻有良好的一致性，而不會過 度蝕刻i到主動矽内。高溫阻障金屬與金的厚度可以被調適 來提供足夠的散熱能力。如果氧化矽層留下來，阻障金屬 是可自由選擇的。所以金屬散熱座可以在實際熱源的數微 米内，而不需要讓整個晶圓都變薄。 雖然本發明已經參閱特定實施例來做說明，但是本說明 是解釋性的，而不被視為是要限定本發明。對於熟知該技 術領域的人士來說，在不偏離由所附申請專利範圍定義的 本發明精神與範圍下，不同的改變與應用都會發生。 圖式代表符號說明 10基底 12 氧化矽層 14 矽層 16 組件 18 氮化矽層 20 金屬層 22 金屬層
Claims (1)
- 200301937 拾、申請專利範園 2. 3. 4. 1.法，包括的步驟有： a) 提供半導體本骨董，勺 撐的氧化碎層，以及覆^ 體（SOI)基底内之半導體裝置 之 方 b) 在部分氧化矽屉 4 臂上的 C)在與該組件相反的基 d)加上優先蝕刻劑，1 廣底下基底内的石夕；及 e)在基底的名虫 作期間提供從級 如申請專利範gj 金屬。 刻部分内 件上的熱 罘IX員之 括石夕支撐基底’由該基底所支 在該氧化矽層上的碎層； 矽層内形成半導體組件； 底表面上，形成蚀刻光罩； 便選擇性的蚀刻掉部分氧化石夕 提供金屬層，以便在組件操 移除。 方法，其中該金屬層包括一高溫 如申請專利範gj 在遺南溫金屬 如申清專利乾_ 或氮化飲。 第2項> 、 /、 万法，其中該金屬層進一步包括 的令 Λ 至、鋼或鋁。 第3項乏、 " 万法，其中該高溫金屬包括鈦鎢 5. 如申請專利範圍第1 $、、 表面上形成氮价^ 万法’其中該步驟c)包括在基底 、iL»今層， 與蝕刻處理，^ Θ ;、、、後優先對該氮化矽層進行光罩 矽。 ·、路出部分氧化矽層底下之基底内的 、〈万法’其中該氮化矽層是優先用 且用風氧化鉀優先對該矽進行蝕 6. 如申凊專利範園第 乾式電漿進行蝕刻 刻處理。 200301937 7. 如申請專利範圍第6項之方法，其中該氮化矽是優先用電 漿進行蝕刻處理，而且用電漿優先對該矽進行蝕刻處理。 8. 如申請專利範圍第5項之方法，在步騾d)後進一步包括的 步騾是優先的蝕刻掉氧化矽層的曝露部分。 9. 如申請專利範圍第8項之方法，其中該氧化矽進層是用緩 衝氫氟酸進行姓刻。 10. 如申請專利範圍第8項之方法，其中該氧化矽層是用離子 電漿進行蚀刻。 11. 如申請專利範圍第1項之方法，在步騾d)後進一步包括的 步騾是優先的蝕刻掉氧化矽層的曝露部分。 12. 如申請專利範圍第1項之方法，在步騾c)之前進一步包括 的步騾是磨擦與該組件相反的基底表面，以降低支撐基 底的厚度。 13. 如申請專利範圍第1項之方法，其中該步騾a)進一步包括 提供黏結矽上絕緣體晶圓。 14. 如申請專利範圍第1項之方法，其中該步驟a)進一步包括 提供具離子佈植氧化矽層的矽晶圓。 15. —種半導體裝置，其包括： a) —半導體本體，包括矽支撐基底，由該基底所支撐 的氧化矽層，以及覆蓋在該氧化矽層上的矽層； b) —半導體組件，是在覆蓋到已經被蝕刻去除掉之部 分基底衲矽層内形成；及 c) 一金屬層，是在被I虫刻去除掉的部分基底内，該金 屬層提供從該組件的熱移除。 20030193716. 如申請專利範圍第1 5項之半導體裝置，其中覆蓋到部分 基底上的該氧化矽層被去除掉，該金屬層緊鄰到矽層。 17. 如申請專利範圍第1 6項之半導體裝置，其中該金屬層包 括一高溫金屬。 18. 如申請專利範圍第1 7項之丰導體裝置，其中該金屬層進 一步包括在該高溫金屬上的金、銘或銅。 19. 如申請專利範圍第1 7項之半導體裝置，其中該高溫金屬 包括鈦鎢或氮化鈦。 20. 如申請專利範圍第1 5項之半導體裝置，其中該金屬層緊 鄰到氧化矽層。 21. 如申請專利範圍第20項之半導體裝置，其中該金屬層包 括一鬲溫金屬。 22. 如申請專利範圍第2 1項之半導體裝置，其中該金屬層包 括在該高溫金屬上的金。 23. 如申請專利範圍第2 1項之半導體裝置，其中該高溫金屬 包括致嫣。
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/053,424 US6900501B2 (en) | 2001-11-02 | 2001-11-02 | Silicon on insulator device with improved heat removal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW200301937A true TW200301937A (en) | 2003-07-16 |
Family
ID=21984117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW091132396A TW200301937A (en) | 2001-11-02 | 2002-11-01 | Silicon on insulator device with improved heat removal and method of manufacture |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US6900501B2 (zh) |
| EP (1) | EP1446836A1 (zh) |
| JP (1) | JP2005509294A (zh) |
| KR (1) | KR20040068922A (zh) |
| CN (2) | CN101188216B (zh) |
| CA (1) | CA2465162A1 (zh) |
| TW (1) | TW200301937A (zh) |
| WO (1) | WO2003041168A1 (zh) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7119431B1 (en) * | 2003-09-18 | 2006-10-10 | National Semiconductor Corporation | Apparatus and method for forming heat sinks on silicon on insulator wafers |
| JP4629490B2 (ja) * | 2005-05-09 | 2011-02-09 | 三菱電機株式会社 | 誘電体分離型半導体装置 |
| US8421128B2 (en) * | 2007-12-19 | 2013-04-16 | International Business Machines Corporation | Semiconductor device heat dissipation structure |
| US20100117153A1 (en) * | 2008-11-07 | 2010-05-13 | Honeywell International Inc. | High voltage soi cmos device and method of manufacture |
| US8232597B2 (en) * | 2009-07-15 | 2012-07-31 | Io Semiconductor, Inc. | Semiconductor-on-insulator with back side connection |
| EP2937898A1 (en) * | 2009-07-15 | 2015-10-28 | Silanna Semiconductor U.S.A., Inc. | Semiconductor-on-insulator with backside heat dissipation |
| US9466719B2 (en) | 2009-07-15 | 2016-10-11 | Qualcomm Incorporated | Semiconductor-on-insulator with back side strain topology |
| CN102484097B (zh) * | 2009-07-15 | 2016-05-25 | 斯兰纳半导体美国股份有限公司 | 具有背侧支撑层的绝缘体上半导体 |
| US9390974B2 (en) | 2012-12-21 | 2016-07-12 | Qualcomm Incorporated | Back-to-back stacked integrated circuit assembly and method of making |
| US8921168B2 (en) | 2009-07-15 | 2014-12-30 | Silanna Semiconductor U.S.A., Inc. | Thin integrated circuit chip-on-board assembly and method of making |
| US9496227B2 (en) | 2009-07-15 | 2016-11-15 | Qualcomm Incorporated | Semiconductor-on-insulator with back side support layer |
| CN102339836B (zh) * | 2011-09-28 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | 绝缘体上硅器件 |
| TWI433615B (zh) * | 2012-04-12 | 2014-04-01 | Subtron Technology Co Ltd | 散熱基板及其製作方法 |
| US9412911B2 (en) | 2013-07-09 | 2016-08-09 | The Silanna Group Pty Ltd | Optical tuning of light emitting semiconductor junctions |
| CA2876267A1 (en) | 2013-12-31 | 2015-06-30 | Martin Tremblay | Electronic vaping device |
| US9515181B2 (en) | 2014-08-06 | 2016-12-06 | Qualcomm Incorporated | Semiconductor device with self-aligned back side features |
| JP6328852B2 (ja) * | 2014-11-13 | 2018-05-23 | クアルコム，インコーポレイテッド | 裏側ひずみトポロジーを有するセミコンダクタオンインシュレータ |
| CN111554750B (zh) * | 2020-05-20 | 2022-06-17 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制备方法、显示面板 |
| CN113421913B (zh) * | 2021-05-26 | 2023-07-18 | 美的集团(上海)有限公司 | 一种soi芯片、制备方法、智能功率模块、电器及空调 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4030943A (en) | 1976-05-21 | 1977-06-21 | Hughes Aircraft Company | Planar process for making high frequency ion implanted passivated semiconductor devices and microwave integrated circuits |
| JPH07115175A (ja) * | 1993-10-14 | 1995-05-02 | Nec Corp | 半導体装置 |
| KR100233286B1 (ko) * | 1996-06-29 | 1999-12-01 | 김영환 | 반도체 장치 및 그 제조방법 |
| US6259099B1 (en) | 1996-12-18 | 2001-07-10 | Commissariat A L'energie Atomique | Ultra-thin ionizing radiation detector and methods for making same |
| US5949104A (en) | 1998-02-07 | 1999-09-07 | Xemod, Inc. | Source connection structure for lateral RF MOS devices |
| JP3265569B2 (ja) * | 1998-04-15 | 2002-03-11 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| US6048772A (en) | 1998-05-04 | 2000-04-11 | Xemod, Inc. | Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection |
| US6063678A (en) | 1998-05-04 | 2000-05-16 | Xemod, Inc. | Fabrication of lateral RF MOS devices with enhanced RF properties |
| US6064088A (en) | 1998-06-15 | 2000-05-16 | Xemod, Inc. | RF power MOSFET device with extended linear region of transconductance characteristic at low drain current |
| JP3395661B2 (ja) * | 1998-07-07 | 2003-04-14 | 信越半導体株式会社 | Ｓｏｉウエーハの製造方法 |
| US6236103B1 (en) | 1999-03-31 | 2001-05-22 | International Business Machines Corp. | Integrated high-performance decoupling capacitor and heat sink |
| US6190985B1 (en) * | 1999-08-17 | 2001-02-20 | Advanced Micro Devices, Inc. | Practical way to remove heat from SOI devices |
| US6222233B1 (en) | 1999-10-04 | 2001-04-24 | Xemod, Inc. | Lateral RF MOS device with improved drain structure |
| US6483147B1 (en) * | 1999-10-25 | 2002-11-19 | Advanced Micro Devices, Inc. | Through wafer backside contact to improve SOI heat dissipation |
| US6303413B1 (en) * | 2000-05-03 | 2001-10-16 | Maxim Integrated Products, Inc. | Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates |
| US6512292B1 (en) * | 2000-09-12 | 2003-01-28 | International Business Machines Corporation | Semiconductor chip structures with embedded thermal conductors and a thermal sink disposed over opposing substrate surfaces |
| IL154945A0 (en) * | 2000-09-21 | 2003-10-31 | Cambridge Semiconductor Ltd | Semiconductor device and method of forming a semiconductor device |
| US6611002B2 (en) | 2001-02-23 | 2003-08-26 | Nitronex Corporation | Gallium nitride material devices and methods including backside vias |
-
2001
- 2001-11-02 US US10/053,424 patent/US6900501B2/en not_active Expired - Lifetime
-
2002
- 2002-10-30 CN CN2007101609553A patent/CN101188216B/zh not_active Expired - Lifetime
- 2002-10-30 JP JP2003543102A patent/JP2005509294A/ja active Pending
- 2002-10-30 CN CNB028217918A patent/CN100438031C/zh not_active Expired - Lifetime
- 2002-10-30 EP EP02778688A patent/EP1446836A1/en not_active Withdrawn
- 2002-10-30 CA CA002465162A patent/CA2465162A1/en not_active Abandoned
- 2002-10-30 KR KR10-2004-7006245A patent/KR20040068922A/ko not_active Application Discontinuation
- 2002-10-30 WO PCT/US2002/034860 patent/WO2003041168A1/en not_active Application Discontinuation
- 2002-11-01 TW TW091132396A patent/TW200301937A/zh unknown
- 2002-12-20 US US10/327,479 patent/US6740548B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005509294A (ja) | 2005-04-07 |
| US6740548B2 (en) | 2004-05-25 |
| EP1446836A1 (en) | 2004-08-18 |
| CN100438031C (zh) | 2008-11-26 |
| CN1579021A (zh) | 2005-02-09 |
| CN101188216A (zh) | 2008-05-28 |
| US6900501B2 (en) | 2005-05-31 |
| CN101188216B (zh) | 2010-06-09 |
| US20030107084A1 (en) | 2003-06-12 |
| US20030085425A1 (en) | 2003-05-08 |
| WO2003041168A1 (en) | 2003-05-15 |
| KR20040068922A (ko) | 2004-08-02 |
| CA2465162A1 (en) | 2003-05-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW200301937A (en) | Silicon on insulator device with improved heat removal and method of manufacture | |
| US6190985B1 (en) | Practical way to remove heat from SOI devices | |
| TWI253729B (en) | A system and method of heat dissipation in semiconductor devices | |
| TW200807653A (en) | Semiconductor device with under-filled heat extractor | |
| JP2018522397A (ja) | 接合型半導体構造のエッチストップ領域を用いた製作 | |
| TW200522268A (en) | Soi mosfet with multi-sided source/srain silicide | |
| JPH0574958A (ja) | 半導体装置およびその製造方法 | |
| TW200810084A (en) | Fuse with silicon nitride removed from fuse surface in cutting region | |
| CN112053936A (zh) | 晶圆背面粗糙化控制方法以及功率器件制造方法 | |
| EP1772898A1 (en) | Method for forming a silicide gate | |
| JP2007150249A (ja) | 半導体装置およびその製造方法 | |
| TW200403848A (en) | Method of manufacturing capacitor in semiconductor devices | |
| JPS61150216A (ja) | 半導体装置の製造方法 | |
| JPH11111843A (ja) | 半導体集積回路装置およびその製造方法 | |
| TW468227B (en) | High frequency metal oxide semiconductor field effect transistor structure | |
| TW432510B (en) | Method for producing device having wavy titanium silicide | |
| CN103378150B (zh) | 半导体器件及其制造方法 | |
| JP3688335B2 (ja) | 半導体集積回路装置およびその製造方法ならびに半導体ウエハ | |
| JP2000340566A (ja) | 半導体装置の製造方法 | |
| JP2709200B2 (ja) | 半導体装置の製造方法 | |
| TWI225284B (en) | Method of using self-aligned metal silicide bridging to form interconnects | |
| KR100598244B1 (ko) | 반도체 소자의 콘택홀 제조 방법 | |
| JPH1126767A (ja) | 半導体装置の製造方法 | |
| JP2002231941A (ja) | 半導体集積回路装置 | |
| TW200903642A (en) | Method of fabricating a semiconductor device |