TR201913677A2 - Sicaklik li̇mi̇ti̇ne göre uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi - Google Patents

Sicaklik li̇mi̇ti̇ne göre uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi

Info

Publication number
TR201913677A2
TR201913677A2 TR2019/13677A TR201913677A TR201913677A2 TR 201913677 A2 TR201913677 A2 TR 201913677A2 TR 2019/13677 A TR2019/13677 A TR 2019/13677A TR 201913677 A TR201913677 A TR 201913677A TR 201913677 A2 TR201913677 A2 TR 201913677A2
Authority
TR
Turkey
Prior art keywords
random access
access memory
dynamic random
dram
temperature limit
Prior art date
Application number
TR2019/13677A
Other languages
English (en)
Inventor
Ergi̇n Oğuz
Koç Fahretti̇n
Original Assignee
Tobb Ekonomi Ve Teknoloji Ueniversitesi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tobb Ekonomi Ve Teknoloji Ueniversitesi filed Critical Tobb Ekonomi Ve Teknoloji Ueniversitesi
Priority to TR2019/13677A priority Critical patent/TR201913677A2/tr
Priority to PCT/TR2020/050683 priority patent/WO2021050020A1/en
Publication of TR201913677A2 publication Critical patent/TR201913677A2/tr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0021—Modifications of threshold
    • H03K19/0027—Modifications of threshold in field effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

Bu buluş, sıcaklık limiti veya sıcaklığına bağlı olarak dinamik rastgele erişim belleği yapılarındaki hücrelerin (21) erişim transistörlerine (211) kutuplama gerilimlerinin uyarlamalı olarak uygulanması sağlayan bir dinamik rastgele erişim belleği yapısı (1) ile ilgilidir.
TR2019/13677A 2019-09-10 2019-09-10 Sicaklik li̇mi̇ti̇ne göre uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi TR201913677A2 (tr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TR2019/13677A TR201913677A2 (tr) 2019-09-10 2019-09-10 Sicaklik li̇mi̇ti̇ne göre uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi
PCT/TR2020/050683 WO2021050020A1 (en) 2019-09-10 2020-08-05 A dynamic random access memory (dram) structure with adaptive body bias voltage depending on temperature limit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TR2019/13677A TR201913677A2 (tr) 2019-09-10 2019-09-10 Sicaklik li̇mi̇ti̇ne göre uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi

Publications (1)

Publication Number Publication Date
TR201913677A2 true TR201913677A2 (tr) 2021-03-22

Family

ID=74866381

Family Applications (1)

Application Number Title Priority Date Filing Date
TR2019/13677A TR201913677A2 (tr) 2019-09-10 2019-09-10 Sicaklik li̇mi̇ti̇ne göre uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi

Country Status (2)

Country Link
TR (1) TR201913677A2 (tr)
WO (1) WO2021050020A1 (tr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8369172B2 (en) * 2010-07-27 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits for providing clock periods and operating methods thereof
JP2016500927A (ja) * 2012-10-31 2016-01-14 三重富士通セミコンダクター株式会社 低変動トランジスタ・ペリフェラル回路を備えるｄｒａｍ型デバイス、及び関連する方法
TR201910444A2 (tr) * 2019-07-12 2019-07-22 Tobb Ekonomi Ve Teknoloji Ueniversitesi Uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi

Also Published As

Publication number Publication date
WO2021050020A1 (en) 2021-03-18

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