TR201917243A2 - Hücreleri̇n eri̇şi̇m örüntüsüne göre uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi - Google Patents

Hücreleri̇n eri̇şi̇m örüntüsüne göre uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi Download PDF

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Publication number
TR201917243A2
TR201917243A2 TR2019/17243A TR201917243A TR201917243A2 TR 201917243 A2 TR201917243 A2 TR 201917243A2 TR 2019/17243 A TR2019/17243 A TR 2019/17243A TR 201917243 A TR201917243 A TR 201917243A TR 201917243 A2 TR201917243 A2 TR 201917243A2
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TR
Turkey
Prior art keywords
cells
dram
bias voltage
dynamic random
voltage according
Prior art date
Application number
TR2019/17243A
Other languages
English (en)
Inventor
Ergi̇n Oğuz
Koç Fahretti̇n
Original Assignee
Tobb Ekonomi Ve Teknoloji Ueniversitesi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tobb Ekonomi Ve Teknoloji Ueniversitesi filed Critical Tobb Ekonomi Ve Teknoloji Ueniversitesi
Priority to TR2019/17243A priority Critical patent/TR201917243A2/tr
Priority to US17/766,326 priority patent/US20240055040A1/en
Priority to PCT/TR2020/051058 priority patent/WO2021091518A2/en
Publication of TR201917243A2 publication Critical patent/TR201917243A2/tr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

Abstract

Bu buluş, DRAM yapılarında satırların erişim örüntüsüne göre bir başka ifade ile satırlara erişim olup olmadığı ve/veya satırlara hangi sıklıkta erişim olup olmadığına göre hücrelerdeki (21) erişim transistörlerine kutuplama (bias) gerilimlerinin (B) uyarlamalı olarak uygulanması ile ilgilidir.
TR2019/17243A 2019-11-07 2019-11-07 Hücreleri̇n eri̇şi̇m örüntüsüne göre uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi TR201917243A2 (tr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TR2019/17243A TR201917243A2 (tr) 2019-11-07 2019-11-07 Hücreleri̇n eri̇şi̇m örüntüsüne göre uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi
US17/766,326 US20240055040A1 (en) 2019-11-07 2020-11-06 A dynamic random access memory (dram) structure with body bias voltage that can be adapted to the access pattern of cells
PCT/TR2020/051058 WO2021091518A2 (en) 2019-11-07 2020-11-06 A dynamic random access memory (dram) structure with body bias voltage that can be adapted to the access pattern of cells

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TR2019/17243A TR201917243A2 (tr) 2019-11-07 2019-11-07 Hücreleri̇n eri̇şi̇m örüntüsüne göre uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi

Publications (1)

Publication Number Publication Date
TR201917243A2 true TR201917243A2 (tr) 2021-05-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
TR2019/17243A TR201917243A2 (tr) 2019-11-07 2019-11-07 Hücreleri̇n eri̇şi̇m örüntüsüne göre uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi

Country Status (3)

Country Link
US (1) US20240055040A1 (tr)
TR (1) TR201917243A2 (tr)
WO (1) WO2021091518A2 (tr)

Family Cites Families (17)

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US5909618A (en) * 1997-07-08 1999-06-01 Micron Technology, Inc. Method of making memory cell with vertical transistor and buried word and body lines
US6646942B2 (en) * 2001-10-09 2003-11-11 Micron Technology, Inc. Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages
KR100526889B1 (ko) * 2004-02-10 2005-11-09 삼성전자주식회사 핀 트랜지스터 구조
CN101221953B (zh) * 2007-11-22 2011-06-22 林殷茵 多端口、多沟道的嵌入式动态随机存储器及其操作方法
US8696522B2 (en) * 2010-08-13 2014-04-15 Robert Brady Tarpaulin surfing apparatus and method
US8582359B2 (en) * 2010-11-16 2013-11-12 Zeno Semiconductor, Inc. Dual-port semiconductor memory and first-in first-out (FIFO) memory having electrically floating body transistor
CN102683418B (zh) * 2012-05-22 2014-11-26 清华大学 一种finfet动态随机存储器单元及其制备方法
CN104854698A (zh) * 2012-10-31 2015-08-19 三重富士通半导体有限责任公司 具有低变化晶体管外围电路的dram型器件以及相关方法
US9112495B1 (en) * 2013-03-15 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
KR102095856B1 (ko) * 2013-04-15 2020-04-01 삼성전자주식회사 반도체 메모리 장치 및 그것의 바디 바이어스 방법
KR20150024685A (ko) * 2013-08-27 2015-03-09 삼성전자주식회사 특성이 서로 다른 칩으로 구성된 메모리 모듈
US20150199134A1 (en) * 2014-01-10 2015-07-16 Qualcomm Incorporated System and method for resolving dram page conflicts based on memory access patterns
US10002657B2 (en) * 2016-03-25 2018-06-19 The Regents Of The University Of Michigan Enhanced memory device
KR102426729B1 (ko) * 2017-08-11 2022-07-29 삼성전자주식회사 불휘발성 메모리 장치 및 불휘발성 메모리 장치의 동작 방법
US10685703B2 (en) * 2018-09-12 2020-06-16 Nxp B.V. Transistor body bias control circuit for SRAM cells
TR201910444A2 (tr) * 2019-07-12 2019-07-22 Tobb Ekonomi Ve Teknoloji Ueniversitesi Uyarlanabi̇li̇r alttaş kutuplama (body bias) geri̇li̇mli̇ bi̇r di̇nami̇k rastgele eri̇şi̇m belleği̇ (dram) yapisi
US11262780B1 (en) * 2020-11-12 2022-03-01 Micron Technology, Inc. Back-bias optimization

Also Published As

Publication number Publication date
WO2021091518A2 (en) 2021-05-14
WO2021091518A3 (en) 2022-01-13
US20240055040A1 (en) 2024-02-15

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