SU970375A1 - Device for checking two-cycle binary counter - Google Patents

Description

second, is connected to the first input of the first element I, the inputs of the correction unit are connected to the outputs of the information bits of the counter, the input of which through the additionally introduced delay element is connected to the second input of the first element I. In FIG. 1 shows a functional diagram of the proposed device in FIG. 2 — timing diagrams for its operation. The device for monitoring a push-pull binary counter contains a push-pull binary counter 1, delay element 2, trigger 3, correction block 4, modulo two convolution block 5, first 6 and second 7 And elements, modulo two 8, additional delay element 9, tires control of addition 10 and subtraction 1 The device input is connected directly to the input of the buffer bits to the counter and through element 2 behind, the cores to the information input of the counter, the first input of the second 7 And element, and the input of the additional delay element 9, the info outputs counter bits are connected to the inputs of the correction unit 4 and the inputs of the convolution unit 5 modulo two, the output of which is connected to the first input of the modulator two modulator two, the output of the correction unit 4 is connected to the second input of the second 7 element I, the output of which is connected to the counting input the trigger 3, the output of the trigger 3 is connected to the second by the input of the adder 8 modulo two, the output of which is connected to the second input of the first 6 And element, the first input of which is connected to the output of the additional delay element 9, addition control bus 10 and subtraction 11 sec. Uniform and the gate input of the counter unit and the correction device works as follows .. The correction unit in each clock cycle an lyses previous state COUNT ka and generates a correction signal condition trigger. By this signal, the trigger is set to a state equal to the value of the even-state attribute of the next state code. In the correction block, the values of two functions Ty23V2i5V2i67V 246., Lp-1) are formed if n is odd, (1 2.6 .. Lp-1), if n is even. F 1u2U2 5U25b7U. Lp) if n is odd, 25b,., (N-1), if n is even. where 1,2, ..., p are the values of the corresponding YUntsikh code bits. The buffer bits are designed to store the previous state of the counter, and data bits to store the next state of the counter. At the start of operation, the state of the trigger 3 is set to the value of the parity attribute of the state code of the counter 1 contained in the information bits. Let, for definiteness, after performing the operation of addition or subtraction, the counter is in the i-M state. Then the 1st state code is contained in the information bits of the counter and is fed to the inputs of the correction unit 4, and the trigger state 3 is equal to the value of the parity attribute of the 1st state code. Consider the operation of the device for monitoring a push-pull binary counter 1 in the next cycle (Fig. 2). An input pulse is fed to the counter input (Fig. 2a), and one of the buses 10 or 11 is the code of the addition or subtraction operation, Depending on the code operations from the output of the correction unit 4 to the second input of the second element And 7, a correction signal is output. It is formed by the value of the i-ro state code in accordance with the expression (1) during the addition operation, or in accordance with the expression (2) during the subtraction operation. The value of the correction signal is equal to one (resolving potential) if the parity of the code of the (i + 1) -th state changes compared to the parity of the code of the i-ro state, or zero (forbidding potential) if the parity does not change. Thus, a correction signal (CR, fig. 2d) of the trigger is formed immediately. same nocje input pulse. Under the influence of the input pulse, the i-ro state code is received from the information bits into the buffer bits (PB, Fig. 2 g) o In the proposed device, the magnitude of the signal delay by the delay element 2 is equal to the time the code is received in the buffer bits. Therefore, after receiving the code in the buffer bits, the delayed input pulse Bj arrives at the first input of the element AND 7. At the same time, if the second input of the element 7 does have a permissive (inhibitory) potential, then the pulse 8, in FIG. 25 (Fig. 2g) passes (does not pass (Fig. 2e) to the counting input of trigger 3 and changes (does not change) its opposite state. As a result, the trigger is corrected (CT) and the trigger 3 is set to tion equal to the parity of the (1 + 1) -th state.

Under the action of the same impulse, an operation is performed. (Cf specified by the operation code. The result of the operation (the next (I + 1) -th state) is received into information bits (pi). Then the code (f + l) -ro from the output of the information bits is fed to the inputs of the block 5 modulo two convolutions, where the value of the parity attribute of this code (CB) is fixed.

When the counter is working correctly, the value of the parity feature coincides with the state of trigger 3, the result of adding (SL) in the adder 8 modulo 2 is zero and on the second Bxog. element And 6 comes prohibitive potential. Therefore, the signal of the shading at the output of the element And 6 is missing. In the event of an error in the counter: a coincidence is absent, and the forbidding potential arrives at the second input of element b. At the first input of the element 6, the input pulse delayed by elements 2 and 9 of the input pulse enters, and an error signal is generated at the output of the element 6.

The signal delay by element 9ea, the holder is equal to the sum of the times of performing the operation in the counter, receiving the code of the (+) -th state into information bits, convolving the information in block 5 convolution modulo two and adding cyNwaTope 8 modulo two.

The introduction of an additional delay element 9 and the connection of the inputs of the block, 4 corrections to the outputs of the information bits of the counter, allowed

reduce the duration of the counter operation time by combining in time a part of the operations of the previous cycle with the operations of the next cycle.

Claims (2)

1. Author's certificate of the USSR 444186, cl. 6 06 F 11/00, 1975. 2. Authors certificate of USSR 607221 cl. G 06 F 11/08, 1978 (prototype). and