SU1615891A1 - Serial to parallel code converter - Google Patents

Abstract

The invention relates to computing and can be used to transmit binary information using signals of three levels of voltage between a computer and peripheral devices. The invention provides for the reception, processing and conversion of one bit of information in a time equal to the duration of this bit of information, which results in an increase in the speed of the converter. The Converter contains a matching unit 1, the elements 2, 3, 12, 13, and 14 delay, the element OR 4 shifting register 5, counters 6 and 7 pulses, elements And 8, 9, 10 and 22, the decoder 11, adders 15, 16 and 17, comparison units 18, 19, and 20, an inverter 21, a pulse shaper 23, and a pulse generator 24. 1 il.

Description

The invention relates to computing techniques and can be used to transmit binary information using signals of three levels of voltage between a computer and peripheral devices.

The aim of the invention is to improve the speed of the converter,. The drawing shows the functional diagram of the converter.

The Converter contains a matching unit 1, the first 2 and the second 3 delay elements, the element OR 4, the shift register 5., the first 6 and the second accountants and mycoJ, the first 8, the second 9 and the third 10 And the elements, the decoder 115 the third 12, the fourth 13 and five 14 delay elements, the first 115, the second 16 and the third 17 adders, the first 18, the second 19 and the third 20 blocks; comparison, the inverter 21, the fourth element And 225 pulses 23 and J eHepaTop 24 pulses. In addition, the first 25 and the second 26 inputs of the converter are indicated in the S circuit, the first .7 ”are the second 28 and the third 29 outputs (the converter.

The converter is working sshduyu- (dim way

To the initial state, counters 6 and 7 are cleared (initial setup circuits he are shown). The input word is information- (data is given to input 25 follower MO bits by bit. In this case, the input signals are determined by three levels of Voltage -iU., -U, 0 "Information bit 1 is encoded by levels ± 11, information bit O is encoded by levels О when the pulse duration and pause (well. The target bit) Td, the beginning of the word is encoded by a double pulse of 2Td duration by the level 4-Ь% Polar pulses of the bits of the word go to the inputs of the delay element 2, negative pulses - to the input of the delay element 3. , 3 and 13 delays: the maximum signal delay by The output T has a certain number of taps, the signals from which are fed to the inputs of the corresponding adders 15 17 "The latter determine the sum of the unit signals at the outputs of the corresponding elements 2, 3 and 13 delays, taking into account the input signals to these elements. The codes of the sums of the units from the outputs adders 15-17 are supplied to the first; the inputs of the respective equalization blocks 18-20, the second inputs of which are

0

five

0

five

0

0

five

five

Input 26 continuously receives a threshold number code. If the sum of the units at the output of the corresponding adder exceeds this threshold number, then an output signal is formed at the output of the corresponding comparator block.

For the pulses of the beginning of the word, the coincidence of the signals at the outputs of the blocks 18 and 20 of the comparison is detected by the element AND 22. The pulse from the output of the latter is given to the input of the imaging unit 23, which forms a narrow pulse. This pulse interrogates the element AND 10 and through the delay element 14 zeroes the counter 7 and-; from this moment synchronizes the operation of the generator 24, the latter generates an impulse sequence with the following period To, which flows through the element 9 to the input of the register 5 and the clock input of the counter 7. Pulse, corresponding to positive input signals, from the output of the comparison block 18 and negative - from the output of the comparison block 19 are fed to the inputs of the element 1-ШИ 4 and further to the information input of the shift register 5, in which you accumulate couple input-parallel code words. and to the input of counter 6 modulo two. After the number of pulses corresponding to the number of word bits, decoder G generates a signal that prohibits the counting of pulses in counter 7, closes elements 9 and 10 through inverter 21 and stops shifting information in register 5. In the latter, a parallel code of the word is formed.

In addition, the signal from the output of the decoder 11 through the delay element 12 drives the element 8, With the correct received code, the counter 6 enters the signal that is output through the element 8 to the converter output 28 as an Information signal. If the received code is incorrectly parity, the signal at the output of counter 6 is missing, the AND 8 element is closed and the Information signal is not ready. If a random double pulse is given to the input 25 of the converter as a result of interference in the word reception process - a sign of the word start, then an extraordinary pulse is formed at the output of the driver 23, Since the word reception process is not finished yet, then the signal at the output of the decoder 7 is absent and

five,

the element AND 10 is prepared for opening by the output signal of the inverter 21. The pulse from the output of the driver 23 is outputted via the element NU to the output 29 of the converter as an error signal.

Claims (1)

Invention Formula The serial to parallel converter contains a matching unit whose input is the first input of the converter, the first and second outputs are connected to the inputs of a single delay element, the OR element whose output is connected to the information input of the shift register, the outputs of which are the first output of the converter , pulse counters, the first, second and third elements And, the output of the first pulse counter is connected to the first input of the first element And, the output of which is the second output of the transducer The receiver, the outputs of the second pulse counter are connected to the corresponding inputs of the decoder, characterized in that, in order to increase the speed of the converter, the third, fourth and fifth delay elements, totalizers, blocks of comparison, the inverter, the fourth element, And, pulse generator and pulse generator, the output of which is connected to the clock input of the second pulse counter and with the first input of the second element And whose output is connected to the clock input of the shift register, the output of the decoder is connected with the control input BTOpqro of the pulse counter, through the inverter with the second input of the second element ten 15 20 15891 6 the first input of the third element And, and through the i-retium delay element with the second input of the first element  And, the first exits of the first element the delays are connected to the corresponding first inputs of the first adder, the output of which is connected to the first input of the first comparison unit, the output of KOTOpoi o is connected to the first input of UT11 and to the first input of the fourth element And, the outputs of the second delay element are connected to the corresponding input by their first inputs of the second adder, the output of which is connected to the first input of the second comparison unit, the output of which is connected to the second input of the OR element, the second output of the first delay element is connected to the first input of the third, "adder" and to the input h of the fourth delay element, the outputs of which are connected to the corresponding second inputs of the third adder, the output of which is connected to the first input of the third comparison unit, the output of which is connected to the second input of the fourth And element, the second inputs of the first and second adders are connected respectively to the first and second outputs of the matching block, the output of the fourth element And is connected to the input of the pulse former, the output of which is connected directly to the second input of the third element And and through the fifth delay element with set by the input of the second pulse counter and with the input of the pulse generator, the input of the first pulse counter is connected to the output of the OR element, the second inputs of the first, second and third adders are combined and VL; The second input of the converter, the output of the third element And is  third output converter. 25 thirty 35 40