SU964979A1 - Digital matched filter for pulsed echo signals - Google Patents

Description

The invention relates to computing and can be used in computing devices for the statistical processing of geoacoustic or radar signals.

A digital filter is known that implements a digital filtering algorithm based on solving linear differential equations with constant coefficients and containing a sampler, an analog-to-digital converter, multipliers, delay elements, and an adder G13.

The choice of a temporal (impulse) or frequency characteristic for building such a filter implies a priori information about the temporal or frequency parameters of the pulsed echo signals, and this, in turn, requires a preliminary statistical analysis of the filtered signals and noise acting on the filter input.

Closest to the proposed digital filter containing delay elements, multipliers, adder, and the delay elements are connected in series, in addition, the output of each delay element is connected to the input of the corresponding multiplier, on

the second inputs of which are weights, the outputs of the multipliers are connected to the corresponding inputs 11 of the adder. The output of the adder is the outputs of the digital filter 2.

The disadvantage of such a filter is that for each implementation of pulsed echoes, it is necessary to select the weighting coefficients of the filter time characteristic, which leads to an increase in the time ofStop echoes.

The purpose of the invention is to increase the filtration accuracy.

15

This goal is achieved by having a digital filter for pulsed echoes containing a multiplier,. the output of which is connected to the first input of the adder, the output of which is 20 with the output of the filter, the analog-digital converter whose input is the input of the filter, a control unit, a recording unit, a character analysis unit, the first and second memory units are entered,

Claims (2)

25 switches op and filtering control unit, the output of which is connected to the control inputs of the first and second memory blocks and the first control input of the adder, the output of which is 30 to the first input of the second memory block, the output of which is connected to the second input of the adder and the first input of the block analysis of signs, the output of which is connected to the second input of the second memory block, the second control / 1 to the input of the adder and the control input of the multiplier, the output of the first memory block is connected to the second input of the block for analyzing characters, the first input of the multiplier and the first input of the switch, the first output of which is connected to the input of the iBoro memory unit and the first input of the recording unit, the output of which is connected to the first input of the control unit, the output of which is connected to the second input of the recording unit, to the control input of the analog-digital converter, first the input of the filtering control unit and the control input of the switch, the second output of which is connected to the third input of the character analysis unit, the second input of the multiplier and the second input of the filtering control unit, while the output of the analog-digital the converter is connected to the second input of the switch, and the second input of the control unit is the control input of the filter.  The control unit contains a pulse generator, a single pulse generator, a frequency divider, an And trigger element and an RS flip-flop, the output of which is connected to the first input of the And element, the second input of which is connected to the output of a frequency divider, the input of which is connected to the output of the pulse generator, the output of which connected to the first input of a single pulse generator, the output of which is connected to the R input of the RS trigger and the trigger input, the input of the RS trigger, is the first input of the control unit, and the second input of the single pulse generator is The second input of the control unit, the output of the pulse generator, the output of the element I, the output of the trigger and the output of the generator of single pulses form the output of the control unit.  The recording unit contains the first and second elements And, RS-trigger, trigger counter, decoder, register and comparison node, the output of which is connected to the first input of the trigger, the output of which is connected to the first input of the second element And whose output is connected to the input of the counter, It is connected to the input of the decoder, the output of which is the output of the recording unit and connected to the second trigger input, the output of the RS flip-flop is connected to the first input of the first element H, the output of which is connected to the first input of the comparison node and the register output to torogo connected to the second input of the comparator, whose output is connected to the S-consist: RS-trigger, R-input of which is the first input of the recording unit, the second inputs of the first and second elements and are combined and the second input of the recording unit.  The filtering control unit contains the first and second RS-triggers, the first and second And elements, the first and second counters, the first second and third decoders, the output of the first RS-trigger connected to the first input of the first And element, the output of which is connected to the first input of the first counter and the input of the second counter, the output of which is connected to the inputs of the second and third decoders, the outputs of which are connected to the S-inputs of the first and second, respectively.  RS triggers, the R inputs of which are combined and are the second input of the filtering control unit,. the output of the first counter is connected to the input of the first decoder, the output of which is connected to the second input of the first counter, the second inputs of the first and second And elements are the first input of the filtering control unit, and the outputs of the first and second And elements and the decoder output by filtration.  FIG.  1 shows a block diagram of a digital matched filter for pulsed echoes; in fig.  2 is a block diagram of the control unit; in fig.  3 - block diagram of the recording unit; in fig.  4 is a block diagram of the filtering control unit.  Device (see  FIG.  1) contains control unit 1, analog-to-digital converter 2, probe 3 and echo signals switch 3, recording unit.  Si 4, first memory block 5 (probing signal, character analysis block b, multiplier 7, second memory block 8 intermediate results, adder 9 and filtering control unit.  she is 10.  Control unit 1 (see  FIG.  2) contains a generator (clock) pulses 11, a frequency divider 12, a generator of single pulses 13, the element And 14, RS-flip-flop 15 and the trigger 16.  Record box 4 (see  FIG.  3) contains the RS-flip-flop 17, the first element And 18, the register 19, the node compared to no 20, the trigger 21, the second element And 22, the counter 23 and the decoder 24.  Filter control block.  10 (see  FIG.  4) contains two RS-flip-flops 25 and 26, two elements And 27.  and 28, two counters 29 and 30 and three decoders 31, 32 and 33.  The device works as follows.  The first command pulse from an external device, which coincides in time with the creation of a probing signal in the medium, enters the control unit 1 through the control input of the system, where through its front terminal a single pulse generator 13 generates a pulse that sets the triggers 15 and sixteen.  The control command from the trigger 16 goes to the switch 3 and switches it in such a way that the output of the analog-digital converter 2 is connected to the inputs of the recording unit 4 and the memory block 5.  At the start command from the trigger 15, the clock pulses generated by the clock pulse generator 11, through the frequency divider 12 and the AND 14 element, are fed to the angular-digital converter 2.  A single pulse from the generator 13 is also fed to the recording unit 4.  An array signal from the device is fed to the input of analog-digital converter 2, in which for each starting pulse, the current amplitude value of the input signal is sampled and converted into a digital code.  From the output of the analog-digital converter 2 digital codes, accompanied by synchronous pulses, through the switch 3 are fed to the recording unit 4 and the memory block. In the latter, the digital codes of the samples are recorded sequentially. .  Block Ps1m ty 5 built according to the principles.  PU, shift registers and has a limited number of cells, determined by the duration of the filter time characteristic.  And since the proposed device uses a probing signal as the temporal characteristic of the filter, the number of cells in memory block 5 is determined by the number of probing signal samples and necessary for filtering echo signals, the condition of matched (optimal) filtering is that (temporal) filter characteristic should be a mirror image of the probe signal, t. e.  ) - c5es (Tc- t), where T is the duration of the probe signal; c is the scale factor.  The impulse response of the optimal digital filter can be written in the form h (ki;) cS3 (njjt-kt) cSjc Г (where k is the current sample number and the probing signal, t is the sampling interval; Tc.  The difference (pr-k) can be considered as the address of the cell in which the V -th sample is recorded. of the probing signal, therefore, the corresponding location of the samples in memory block 5 can be used to realize the time response of the digital matched filter, t. e.  provide a mirror image of the surround signal.  In the general case, the arrival time of the probing signal is unknown, therefore, the input signal is recorded in memory block 5 by a command pulse from an external device, but since the number of cells is limited, sample codes of the probing signal must be recorded in memory block 5.  so that, for example, the sampling code of the maximum amplitude of the probing signal is located in a specific cell of the memory block 5.  For this, the comparison node 20 in the recording unit 4 compares the sampling codes of the input signal currently arriving at Sjc (mT) from AND 18 and at the previous time S ts (t-1) T, which is stored in register 19.  When choosing the maximum code of the input signal t. e.  subject to S3cf (ni-Of 5cc (n t), the comparison node 20 forms a command that sets the trigger 17 to the zero state, stopping the flow of codes, and sets the trigger.  21 into one state, permitting the passage of clock pulses accompanying codes through AND 22 to counter 23.  Sync pulses are counted until their number reaches the pre-selected) GO number N samples of the sound signal, which are located after the maximum, for example, N.  The decoder 24 selects the required state of the counter 23 and produces a recording end pulse. a probing signal, which sets the trigger 17 to the zero state and goes to the control unit 1, where it sets the trigger 15 to the zero state, prohibiting the passage of pulses h. through element And 14 to analog-to-digital converter 2.  Thus, in the device, the digital codes of the probing signal are fixed, with the maximum of the zones; the one of the signals located in a specific cell of the memory block 5, thereby achieving uniformity of fixing the temporal characteristic at each sounding.  On the second command impulse from the external device, which anticipates the echo signal in time, the control unit L.  re-forms control and start commands.  By the control command, the switch 3 connects the output of the memory unit 5 to its input, forming a ring of memory cells for circulating the sampling signal samples through them, and the output of the analog-digital converter 2 to the inputs of the character analysis block b, multiplier 7 and control unit filtration 10.  The start command in the control unit 1 generates the start-up pulses of the analog-to-digital converter 2 with the same tracking frequency f 3.   The analog signal from the external device is switched to the analog-to-digital converter 2, in which, for each starting pulse, the current amplitude of the input signal is sampled and converted into a digital code.  G output of analog-to-digital converter 2 through switch 3 of digital code is fed to the first input of multiplier 7, the sign of the input-signal sample code goes to the character analysis block b, and the clock pulses accompanying the digital code go to the filter control unit 10.  For each clock pulse, the triggers 25 and 26 are set to one state, allowing the sequence of the (27) clock pulses to pass through the element 27 and the frequency of which fjdrlzhna be more (pd + 1) times the start pulse frequency f , city e, f t () f 3.  The sequence of (pd4-1) tact pulses from element 27 is fed to counter 29 and memory 5, where it is used to circulate the code of the probing signal.  But since the memory block 5 has PD cells, and, clock pulses (), it produces one additional shift of the sampling codes of the probing signal in each start-up cycle of the analog-digital converter 2.  Such a circulation mode is necessary for the implementation of the digital matched filtering algorithm. In the filter control unit 10, a sliding pulse is also generated, which is fed to the mat 9 to output the filtering result, which is formed in different clock cycles during each start cycle ), t. e.  in the first cycle, it is formed in pd-omtakte, in the second cycle - in (n0-1) th cycle, and so on. d. , in the first cycle - in the first cycle, and in (on + 1) -th cycle - again in pdtakTe, {П {1 + 2) -th cycle - in (n-1) -th cycle, etc. d.  The sliding pulse produces with the help of a counter 29, a decoder nj, -th pulse 31.  The entrance of the counter 29 is given a sequence of (by + 1) pulses through the element AND 27.  When the descrambler 31 is being targeted. By the second pulse, it is fed to the adder 9 of the output of the fnltration output, and the falling edge of this impulse resets the counter 29. After the reset, the counter receives another pulse from the And 27 element. .  In the next start-up cycle, the counter 29 starts counting from the first pulse, and is reset by the (1) -th pulse, after which two pulses are recorded in it, and so on. d. Sequences of (pr + 1) clock pulses are generated in the filtering control unit using counter 30 and decoders 32 and 33.  Decoder.  33 selects the state of the counter 30 after the arrival of the o-th pulse and produces a pulse, which sets the trigger 26 to the zero state and prohibits the passage of pulses through the AND 28 element.  Thus, from the element 28 and out of the sequence of "on clock pulses.  The decoder 32 selects the connection of the counter 30 after the arrival of the (+ 1) th pulse and produces a pulse, which sets the trigger 25 to the zero state and. prohibits the passage of clock pulses through the element 27 to the counter 30 and to the output of the filtering control unit.  From the filtering control unit 10, the clock pulses through the AND unit 28 are fed to the memory unit B, where they are used to record the digital codes received from the adder 9 and read the intermediate result codes to the adder 9 AND the sign of the indicated codes to the character analysis block B.  Depending on the 2 nakov codes of samples of the input (S i gn -Sjx) and probing (Sign 83) signals, as well as the sign of the intermediate result code (Sign Snp), the character analysis block 6 generates a command to read directly or from the multiplier 7 to the accumulator 9, the Q command to read the direct or reverse code from the adder 9 to the block 8 and the command + memory block 8 to the adder 9 according to the following logical expression: Cm Sign 5ts, F Sign Cm S i gn Spj, f Cm Sign Spp g (Cm Sign S p + C i Si S i gn Snp) P where C m is the product sign. ; P - adder transfer signal.  During each start-up cycle, the code for extracting the input signal Sgjj (iT) appears on one of the inputs of multiplier 7 and remains on it until the code arrives after the sensible cycle of the SBX (+ l) t radiation.  At the second input of the multiplier 7, during each start-up cycle, the samples of the probing signal are fed.  the multiplier 7 produces a sequential multiplication of the sampling code of the input signal Sg (IC) by all the first sampling codes of the probing signal es (o l) gJ Paired products from the output of the multiplier 7 are fed to one of the inputs of the adder 9, the second input of which receives the intermediate result codes from the block memory 8.  Intermediate (partial sums of paired products from the output of adder 9 are recorded in memory block 8.  In one of the cycles, corresponding to the sliding pulse, the code of the intermediate sum is output from the adder 9 to the output of the device, and at this moment the zero code is written to the memory block 8, t. e.  One of the memory cells 8 is reset.  During the operation of the device, the following algorithm of digital matched filtering f / i S, -t (no-k) t3sJ (n-k) t is realized where n is the current sample number of the input signal.  Moreover, with n k “O, Thus, overwriting the probing signal during each sounding and using its sample codes as a pulse (time) filter characteristic creates, in comparison with the prototype, an optimal filtering mode for each realization of pulsed echoes. .  The choice of the maximum value of the probing signal and recording it in a certain cell of the power supply unit, regardless of the time of arrival, ensures the stability of the digital pulse characteristic of the digital filter for each implementation of the echo signal.  The development of a sliding pulse makes it possible, directly in the filtering process, to output the results to an external device and not to waste time searching for the result of the filter after the end of the processing cycle.  Claim 1.  A digital matched filter for pulsed echoes containing a multiplier; the output of which is connected to the first input of the adder, the output of which is the output filter of the analog-to-digital converter, whose input is the input of the filter characterized in that, in order to improve the accuracy of filtering, a control unit, a recording unit, a character analysis unit, the first and a second memory block, a cohmmutator. and a filtering control unit, the output of which is connected to the control inputs of the first and second memory blocks and the first control input of the adder, the output of which is connected to the first input of the second memory block, the output of which is connected to the second input of the adder and the first input of the analysis unit characters whose output is the subkey to the second input of the second memory block, the second control input of the adder and the control input of the multiplier, the output of the first memory block is connected to the second input of the character analysis block, the first multiplier input and the first th input switch, the first shlhod coupled to an input of the first block memory and a first input of a recording block, whose output is connected to the first input of the control unit, Bb. the stroke of which is connected to the second input of the recording unit, controlling the cadre input of the analog-digital converter, the first input of the filtering control unit and the control input of the switch; the second output of which is connected to the third input of the character analysis unit, the second input of the multiplier and the second input of the filtering control unit Thus, the A / D converter output is connected to the second input of the switch, and the second input of the control unit is the control input of the filter.  .  2 The device according to claim.  1 that the control unit contains a pulse generator, a single pulse generator, a frequency divider, a trigger, an And element and an RS flip-flop, the output of which is connected to the first input of an And element, the second input of which is connected to the output of a frequency divider, connected to the output of the pulse generator, the output of which is also connected to the first input of the generator of single pulses, the output of which is connected to the R input of the short-circuit trigger and the trigger input, the S input of the RS trigger is the first input of the control unit, and the second input of the generator and the single pulses are the second input of the control unit, and the output of the pulse generator, the output of the element I, the output of the trigger and the output of the generator of single pulses form the output of the control unit.  .  3 The device according to claim.  1, it is clear that the recording unit contains the first and second elements AND, RS-trigger, trigger, counter, diopter, register and node, the comparison, the output of which is connected. with the first input of the trigger, the output of which is connected to the first input, of the second element I, the output of which is connected to the input of the counter, the output of which is connected to the input of the decoder, the output of which is the output of the recording unit and connected to the second input of the trigger.  vyhol R. “Trigger is connected to the first input of the first element I, whose exhaust is connected to the first input of the node by comparing with the register input, the output of which is connected to the second input.  the comparison node whose output is connected to the S-input of the K5 flip-flop, whose K-input is the first input of the recording unit, the second inputs of the first and second And elements are combined and are the second input of the recording unit.  four.  The device according to claim.  1, that is, that the filtering control unit contains the first and second RS-flip-flops, the first and second elements And, the first and second counters the first, second and third decoders, the output of the first RS-flip-flop is connected to the first input of the first element And The output of which is connected to the first input of the first counter and the input of the second counter, the output of which is connected to the inputs of the second and third decoders, the outputs of which are connected to the S inputs of the first and second RS triggers, respectively, the R inputs of which are combined and are the second input of the unit and the filtering control, the output of the first counter is connected to the input of the first decoder, the output of which is connected to the second input of the first counter, the second inputs of the first and second elements AND are combined and are the first input of the filtering control unit, and the outputs of the first and second elements AND and the output of the decoder are The output of the filter control block.  Sources of information taken into account in examination 1, Goldenberg L. M.  and etc.  Digital filters.  M. Holy bones  1974.   2. US patent 3521041, cl. G 06 F 15/34, 1970 (prototype). eleven Controllai Lead fMod 0On & yunP Na & y 1 one Vmrd -0 15 R ftafyoM ftadMft 4ke2