RU2020496C1 - Pulse repetition period meter - Google Patents

Abstract

FIELD: measurement technology. SUBSTANCE: meter uses delay line 1, amplifiers 2, adders 3 and 15, analog-to-digital converter 4, switches 5 and 8, registers 6, 9 and 14, comparison circuit 7, counter 10, pulse shaper 11, permanent storage 12, subtraction circuit 13, clock-pulse generator 16, filter 17, threshold device 18, time indicating unit 19 and arithmetic unit 20 with respective couplings. EFFECT: enhanced accuracy. 4 dwg

Description

 The invention relates to measuring equipment, in particular to measuring time intervals.

 Known devices for measuring the period T of the pulse repetition of a known (deterministic) shape, in particular close to rectangular [1].

The disadvantage of these devices is the low accuracy of measuring the period T of the pulse repetition, and especially in a situation where the duration of τ _and pulses is unknown.

 Closest to the proposed device is [2].

Its disadvantage is the low accuracy of measuring the pulse repetition period T, which also manifests itself in conditions of unknown duration τ _and pulses. At the same time, in cases where the maximum value of the pulse duration is limited and is an a priori known value, there is the possibility of increasing the measurement accuracy.

 The aim of the invention is to improve the accuracy of measuring the current values of period T.

 This goal is achieved by the fact that a filter, an analog-to-digital converter, a threshold device, a time recording unit and an arithmetic unit are additionally introduced into the pulse repetition period meter containing a clock pulse generator, the filter output being connected to the analog input of the analog-to-digital converter, the output of which connected to the input of the threshold device, the output of which is connected to the control input of the time recording unit, the first output of which is connected to the input of the arithmetic unit, and the second output is connected to the zero-setting inputs of the threshold device and the arithmetic unit, the output of which is connected to the meter output, the output of the clock generator is connected to the gating input of an analog-to-digital converter, the counting input of the time recording unit and the clock inputs of the threshold device and time recording unit, while the filter contains an N-tap delay line, an N-input adder and an amplifier, the outputs of the N-tap delay line from the first to (N-1) -th are connected to the corresponding inputs of the N-tap delay directly, and the Nth output of the N-branch delay line is connected to the corresponding input of the N-input adder through an amplifier, the output of the N-input adder is connected to the filter output, the threshold device contains a comparison circuit, a register, and a switch, the first inputs of the comparison circuit and the switch is combined and connected to the input of the threshold device, the output of the switch is connected to the input of the register, the output of which is connected to the second inputs of the comparison circuit and the switch, the clock input and the input of setting the register zero are connected to the corresponding inputs of the threshold device, the output of the comparison circuit is connected to the control input of the switch and the output of the threshold device, the time recording unit contains a pulse shaper, counter, register and switch, and the output of the counter is connected to the first input of the switch and the input of the pulse shaper, the output of which is connected to the second output the time registration unit and the zero-setting input of the register, the output of which is connected to the first output of the time registration unit and the second input of the switch, controlling One of which is connected to the input of the time recording unit of the same name, and the output is connected to the register input, the clock input of which is connected to the clock input of the time registration unit, the arithmetic unit contains read-only memory, a subtraction circuit, a register and an adder, the second adder input and the inverse input of the circuit subtractions are combined and connected to the input of the arithmetic unit, the zero-setting input of which is connected to the same input of the register, the output of which is connected to the first input of the adder, and the input is connected to the output a subtraction circuit, the input of which is connected to the output of the permanent storage device, the output of the adder is connected to the output of the arithmetic unit.

 The invention is illustrated in FIG. 1-4.

 In FIG. 1 shows a diagram of the proposed meter; in FIG. 2 - time diagrams explaining the measurement procedure in the proposed device; in FIG. 3 is a timing chart explaining the operation of a known meter; in FIG. 4 - time diagrams explaining the operation of the proposed meter.

 The device (Fig. 1) contains a delay line (LH) 1, amplifier 2, adder 3, analog-to-digital converter (ADC) 4, switch 5, register 6, comparison circuit (CC) 7, switch 8, register 9, counter 10 , pulse shaper (FI) 11, read-only memory (ROM) 12, subtraction circuit (CB) 13, register 14, adder 15, clock generator (GTI) 16, filter 17, threshold device (PU) 18, time recording unit (BRV) 19, arithmetic unit (AB) 20.

In FIG. 2 shows a sequence of reference pulses with a period T _o (see Fig. 2, a) and a sequence of input pulses (see Fig. 2, a). In this case, the device must carry out the procedure for calculating
T = T _o - T _i ^' + T _i $\genfrac{}{}{0ex}{}{\text{''}}{\text{+}}$ ₁ , where T is the measured repetition period of the input pulses in the i-th period;
T _about - the repetition period of the reference pulses;
T _i ^' - delay of the i-th input pulse relative to the nearest (previous) reference pulse;
T _{i + 1} ^' is the delay of the (i + 1) -th input pulse relative to the nearest (previous) reference pulse.

 The pulse repetition period meter (see Fig. 1) contains a series-connected filter 17, which includes LZ 1, amplifier 2 and switch 3, ADC 4, PU 18, which includes switch 5, register 6 and SS 7, BRV 19, which includes switch 8, register 9, counter 10 and FI 11, AB 20, which includes ROM 12, CB 13, register 14 and adder 15. In addition, the meter contains a GTI 16, the output of which is connected to the input the gating of the ADC 4, the counting input BRV 19 and the clock inputs PU 18 and BRV 19.

= NΔt , (3) где N - число отводов ЛЗ 1, число входов сумматора 3, кроме того,
Т_о = K Δt=2^lΔt, (4) где К - коэффициент пересчета счетчика 10;
l - разрядность счетчика 10, АЦП 4 и составляющих ПУ 18, БРВ 19, АБ 20.For a given step Δ t of the delay line and the known maximum value of the input pulse duration τ and _max , the remaining parameters can be determined:
GTI frequency 16
f = 1 / Δ t, (2)
total delay time LZ 1
T _ls =

= NΔt, (3) where N is the number of taps LZ 1, the number of inputs of the adder 3, in addition,
T _about = K Δt = 2 ^l Δt, (4) where K is the conversion factor of the counter 10;
l - bit counter 10, the ADC 4 and the components PU 18, BRV 19, AB 20.

 The proposed meter works as follows.

The result of the summation from the output of the adder 3, the end element of the filter 17 is supplied to the AUP 4, converted to digital form (l-bit code) and with a repetition period Δ t is supplied to the control unit 18 to the first input of the SS 7. The voltage comes to the second input of the SS 7, stored in register 6, which at the beginning of each period T _{o is} set to the zero position (determining the threshold voltage U _p = 0 at the beginning of each measurement cycle) by a pulse from the output of FI 11 of block 19. At the output of SS 7, the voltage "LOG 1" or " LOG 1 "depending on which of the two comp Vai is greater.

 If the output of the ADC 4 receives a voltage greater than that recorded in the register 6, then the output of the SS 7 produces a voltage supplied to the control input of the switch 5, under the influence of which the output of the ADC 4 connects to the output of the register 6. Under the action of the clock frequency f coming from the output of the GTI 16 to the clock input of register 6, the voltage coming back from the ADC 4 is recorded in register 6.

 In the next time interval equal to Δ t, the voltage newly received from the ADC 4 will be compared with the previous voltage previously recorded in register 6. If the newly received value turned out, for example, to be less than that previously recorded in register 6, then CC 7 is generated at the output the voltage supplied to the control input of the switch 5, under the action of which the output of the register 6 is connected to its input. Under the action of the clock frequency f, the value previously recorded in the register is again written to it (the old value is regenerated).

 Thus, if the value newly received from the ADC 4 exceeds the value previously recorded in register 6, then the new value will be written in register 6.

 If the new voltage value coming from the ADC 4 does not exceed the previously recorded value in register 6, then the old value is regenerated in the register.

 By the end of the cycle, the maximum voltage (allocated by filter 17 in this cycle) will be in register 6.

In the next cycle T _{about, a} similar procedure is repeated and the maximum value for this period is selected.

From the output of the CC 7 of the block 18, the control voltage is supplied to the switch 8 of the block 19. The BRV 19 fixes in each cycle T _the time of maximum voltage isolation and works synchronously with the block 18 and under its control.

 BRV 19 works as follows.

 The outputs of the register 9 and counter 10 are connected to the inputs of the switch 8, to the control input of which comes the control voltage from the CC 7 of block 18.

At the beginning of each period T _{about the} pulse generated in FI 11, connected to the output of the counter 10, the register 9 is set to "0".

With the arrival of a clock pulse f, the counter 10 changes its state, forming at its output a code corresponding to the time elapsed from the beginning of the cycle T _o .

 At those time points counted by the counter 10, when the voltage exceeding the value previously recorded in the register 6 is supplied from the output of the ADC 4 to the control unit 18, in the BRV 19 under the action of a control signal from CC 7, the output of the counter 10 through the switch 8 is connected to register 9. Under the action of the clock frequency, the code value of the counter 10 is recorded in register 9.

 At those times when the voltage not exceeding the previously recorded voltage is supplied to the control unit 18 from the output of the ADC 4, the previously recorded time value (code) is regenerated in register 9 in it.

By the end of each i-th cycle T _about in the register 9 there will be a time code T _i ', which is received in AB 20.

 The value of the period of incoming pulses is calculated by the formula (I).

This calculation procedure is implemented by AB 20. In it, the value of the time code T _i ^I arrives at the inverse input of CB 13, the positive input of which receives a code corresponding to the value of the period T _о from ROM 12. At the output of CB 13, a time code equal to T _about -T _i , which is recorded in the register 14 under the action of the pulse T _o arriving at its input.

From the output of the register, the value of the time code T _o -T _i ^I , delayed by the cycle, is supplied to the first input of the adder 15, the second input of which receives the calculated value T _{i + 1} ^I without delay from the output of the register 9 of the relay receiver 19. At the output of the adder, the value time code corresponding to the pulse repetition period (1).

 To prove the positive effect, we consider the response of the filters of the prototype meter and the proposed meter to rectangular input pulses of various durations.

Consider the cases when N = 6, T _lz = 6 Δ t, and the input pulses have the duration:
a) τ _and = Δt <T _lz ;
b) τ _and = 3Δ t <T _lz ;
c) τ _and = 6Δ t = T _lz ;
d) τ _u = 8Δ t> T _ls .

Moreover, in FIG. 3 and 4 are diagrams of output voltages, respectively, for the prototype filter, which is used as a filter, matched to receive a rectangular pulse of known duration (in particular, τ _and = = T _lz ) and filter 17 used in the proposed meter.

 From FIG. 3 shows that the filter of the prototype has a "plateau" in its output characteristic in all cases, except when the duration of the input pulse is consistent with the duration of the LP, i.e.

τ _and = T _lz .

From FIG. 4 shows that the filter 17 of the proposed meter has a similar "plateau" only for cases when
τ _and > T _ls .

≅ T_лз, выходное напряжение фильтра предлагаемого измерителя характеризуется следующими свойствами:
- существование и единственность локального максимума, что позволяет говорить о максимуме М выходного сигнала;
- независимость момента появления этого максимума t_м от длительности τ_и, причем сам момент t_м при моменте появления импульса на входе t = 0 определяется длительностью реакции фильтра, т.е. временем задержки в ЛЗ.It is this fact that allows us to say that in the case of input pulses with a known duration τ _and satisfying the condition

≅ T _ls , the output voltage of the filter of the proposed meter is characterized by the following properties:
- the existence and uniqueness of a local maximum, which allows us to talk about the maximum M of the output signal;
- the independence of the instant of occurrence of this maximum t _m from the duration τ _and , moreover, the moment t _{m itself} at the moment of appearance of a pulse at the input t = 0 is determined by the duration of the filter reaction, i.e. delay time in LZ.

The main advantage of the proposed meter is the unbiased estimate of T, i.e., in the absence of a systematic error (Δ = 0). Note that these properties do not possess the meters with matched filters at their input, which although providing a minimum fluctuation error δ meter, but have significant systematic error Δ, the value of which is directly proportional to the difference between the lengths of the input pulse and delay τ _and T LZ _LZ.

Claims (1)

 A PULSE REPEATER PER METER, comprising a clock pulse generator, characterized in that, in order to increase accuracy, a filter, an analog-to-digital converter, a threshold device, a time recording unit and an arithmetic unit are introduced, the filter output being connected to an analog-to-digital analog input a converter, the output of which is connected to the control input of the time recording unit, the first output of which is connected to the input of the arithmetic unit, and the second output is connected to the threshold zero inputs about the device and the arithmetic block, with the inputs of the zero setting of the threshold device and the arithmetic block, the output of which is connected to the output of the meter, the output of the clock generator is connected to the gate input of the analog-to-digital converter, the counting input of the time recording unit and the clock inputs of the threshold device and time recording unit wherein the filter contains an N-tap delay line, an N-input adder and an amplifier, the conclusions of the N-tap delay line from the first to (N - 1) th are connected to the corresponding input the N-input adder directly, and the N-th output of the N-output delay line is connected to the corresponding input of the N-input adder through an amplifier, the output of the N-input adder is connected to the filter output, the threshold device contains a comparison circuit, a register and a switch, the first the inputs of the comparison circuit and the switch are combined and connected to the input of the threshold device, the output of the switch is connected to the input of the register, the output of which is connected to the second inputs of the comparison circuit and the switch, the clock input and the zero setting input the trams are connected to the corresponding inputs of the threshold device, the output of the comparison circuit is connected to the control input of the switch and the output of the threshold device, the time recording unit contains a pulse shaper, counter, register and switch, and the output of the counter is connected to the first input of the switch and the input of the pulse shaper, the output of which is connected to the second output of the time recording unit and the input of setting the register to zero, the output of which is connected to the first output of the time recording unit and the second input of the switch RA, the control input of which is connected to the input of the time recording unit of the same name, and the output is connected to the register input, the clock input of which is connected to the clock input of the time recording unit, the arithmetic unit contains read-only memory, a subtraction circuit, a register and an adder, the second input of the adder and the inverse input of the subtraction circuit is combined and connected to the input of the arithmetic block, the input of the zero setting of which is connected to the same input of the register, the output of which is connected to the first input of the adder, and the input dklyuchen to the output of subtraction circuit whose input is connected to the output-only memory, the adder output being coupled to the output of the arithmetic unit.

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