SU936037A1 - Multichannel device for testing redundancy shift register - Google Patents

Description

(54) MULTI-CHANNEL DEVICE FOR CONTROL OF RESERVED SHIFT REGISTER

one

This invention relates to memory devices.

A multichannel device for monitoring a redundant shift register is known, which contains elements of a control circuit, NAND elements, a majority element designed to build reliable systems that retain their performance in the event of malfunction or failure in one or two channels of system 1.

A disadvantage of this device is its low speed and reliability.

Closest to the technical solution proposed is a multichannel device for monitoring a redundant shift register, comprising a convolution unit, a parity unit having connections with the convolution unit and the control unit, a trigger connected to the control unit and the comparator unit connected to the convolution unit, and delay elements 2.

A disadvantage of this device is its low reliability when monitoring redundant shift registers, since in this case the result of the monitoring is output by the comparison unit with a delay after

shifting information in the register and issuing it to an external device.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that

 into a multichannel device for monitoring a redundant shift register containing a modulo two convolution unit, whose inputs are the information inputs of the first channel of the device, the first

10 trigger, the first and second inputs of which are respectively the first clock and control inputs of the device, and the comparison circuit, the inputs of which are connected respectively to the outputs of the convolution unit modulo two and the first trigger, are entered second

 and the third triggers, modulo-two adders, majoritarian elements, decipher, code converter, AND elements, NOT element and switch, the first inputs of the first and second AND elements being connected

20 with the first input of the first trigger, the second input of the first element I is connected to the second input of the first trigger and the input of the element NO, the output of which is connected to the second input of the second element I, the output of the first

element I is connected to the first input of the first modulo-two adder and a single input of the second trigger, whose outputs are connected respectively to the first inputs of the third and fourth And elements, the second inputs of which are connected to the zero inputs of the second and third triggers and are the second clock input of the device, a single the input and output of the third trigger are connected respectively to the output of the comparison circuit and the first input of the decoder, the first input of the second modulo-2 adder is connected to the output of the second element And, the second inputs Modulators two modulators are connected respectively to the outputs of the fourth and third elements AND, the first inputs of the first and second major elements are connected respectively to the first and second inputs of the switch and are the information inputs of the second channel of the device, the second inputs of the majority elements are connected respectively to the third and fourth inputs the switch and are the information inputs of the third channel of the device, the third inputs of the majority elements are connected respectively to the outputs of the summator modulo two and the fifth and sixth inputs of the switch, and outputs to the seventh and eighth inputs of the switch, the ninth and tenth inputs and outputs of which are connected respectively to the outputs of the decoder and inputs of the code converter whose output is the output of the device, outputs of adders modulo two and third flip-flops are the outputs of the first channel, and the second and third inputs of the decoder are, respectively, the control inputs of the second and third channels of the device.

The drawing shows a functional diagram of the proposed device.

In the drawing, a controlled redundant shift register 1 is indicated.

The device contains a convolution unit 2 modulo two, the first trigger 3, the first 4 and the second 5 elements And the second trigger 6, the element NOT 7, the third 8 and the fourth 9 elements And, the first 10 and the second 11 modulo two modulators 12 code converter , the first 13 and second 14 majoritarian elements, the comparison circuit 15, the third trigger 16, the decoder 17 and the switch 18. In the drawing, the information inputs 19 of the first channel of the device, the first 20 and second 21 clock inputs, the information inputs 22 and 23 of the second channel, information inputs 24 and 25 of the third channel, outputs 26 and 27 the first- channel, the control input 28 of the second channel, the control input 29 of the third channel control output 30 of the first channel, the output device 31 and a control input 32 yush.y device.

The device works in the following way.

Depending on the value of the information at the output of the controlled register 1,

the input to the device 32, the output of one of the elements 4 or 5, a pulse is generated, gated by a clock pulse, is received by it on the input 20. If the information bit on the input 32 is one,

then, at the output of the element 4, a pulse is formed, which sets the trigger 6 into one state and enters the input of the adder 10. At the same time, this clock pulse gates information into the trigger 3, which operates in the mode of counting the unit bits of the output information. In the zero state at the input 32, a pulse is formed at the output of the And-5 element, which is fed to the adder .11.

5 On the trailing edge of the clock pulse at input 20, information in register 1 is shifted, the next bit of output information is generated at the output of register 1, and a sign of this information is formed at the output of block 2.

A clock pulse at the input 21 forms a pulse of the final phase, which, depending on the state of the trigger 6, is produced either at the output of the AND 8 element,

5 or at the output of an element 9. At the falling edge of this clock pulse, trigger 6 is zeroed. At the same time, this clock pulse gates in trigger 16 a comparison result at the output of circuit 15, where a comparison of the state of trigger 3 and

0 sign of information at the output of block 2. At the moment of formation of the pulse of the final phase of the current bit of information, the reliability of the next bit of information is monitored. In the event of a mismatch, the information at the outputs of trigger 3 and block 2 is fixed in a failure of trigger 16, from the output of which a pulse arrives at the decoder 17. When the failure of one channel of register 1 is fixed, the control pulses to restructure the structure

0 is not generated by the decimator 17, and the information from the adders 10 and 11 is fed to the switch 18 through the majority elements 13 and 14 on the principle of two out of three. If there are failures in the two channels of register 1, the decoder 17 produces

 the pulses controlling the switch 18 according to the following algorithm: failure in the first and third channels — selects the information of the second channel on inputs 22 and 23; the first and second - the third channel information is selected by inputs 24 and 25; the second and third are the first channel information selected.

Consequently, the information outputted in all three channels from switch 18 to the input of code converter 12 is always

55 will be reliable. Converter 12 converts binary information entering the device from register 1 into a bi-phase code, which improves the noise immunity of communication lines and also reduces the number of the latter due to the possibility of separating clock pulses from the information itself.

In addition, the device provides a combination in time of the process of control of information with the process of its transformation. This is achieved by the fact that the impulse of the initial phase of the biphasic code is formed depending on the bit of information output, and the impulse of the final phase is formed unconditionally. The final-phase pulse shaping cycle of the current bit of information is used to monitor the subsequent information bits and to adapt the structure of the redundant register 1 in the event of a failure. Thus, the decrease in the speed of register 1 due to control using the proposed device does not occur.

The technical and economic advantage of the proposed device is higher reliability and speed in comparison with the prototype.

Claims (2)

 1. USSR author's certificate No. 526822, cl. G 06 F 11/00, 1977. 2. USSR author's certificate No. 529489, cl. G 11 C 29/00, 1976 (prototype).