SU599359A1 - Redundancy counting-down circuit - Google Patents

Description

FIG. Figure 1 shows the structured diagram of the resected (a digital display device; Fig. A shows time diagrams.

The redundant scaler contains channels 1-1-1 3, in each of

There are NOT elements, counters, majority elements, carry elements, registers, shift. and descramblers

In each channel, the output of the decoder is connected to the input of the transfer element and the input of the decoder is connected to the outputs of the shift registers of all channels, the outputs of the transfer element 5 4 channels are connected to the installation inputs of the counter 3 J whose outputs are connected to the inputs of the transfer element of the same channel and the transfer element of the previous one i 1 channel, and the outputs of the counter of the first channel are connected to the inputs of the transfer element of the last channel, the control inputs of the shift register of the 6 channel are connected to the output of the HE element 2 of this channel and the shift input 8 j channel counting input of each channel is connected

with the input element NOT this channel, the inputs of the majority element 4. i channel 4 is connected to the outputs of the counters of all channels, and the counting input 9 i channel j is connected to the input element is NOT the same channel.

Redundant recalculation device operates as follows.

The counting inputs of the counters synchronously receive counting pulses.

(see Fig. 2a) from the source of counting pulses. The inverted counting pulses (see Fig. 26) from the outputs of the elements do NOT arrive respectively at the control inputs of the shift registers.

On the forward counting pulse, the state changes in the counters, and on the back (} counting pulse pulse, the code from the counter 3 i is written to the shift register 6 of channel I

After the arrival of the counting pulse, a stack of pulses is supplied to the shift inputs (see Fig. 2c). The number of pulses in a burst is not less than the number of binary bits in the counter. Tutu ends before arrival

the next counting pulse. At the outputs of the shift registers, sequential codes are formed, which are processed separately by the decoders. The decoder of each channel performs the logical operation of the PES, defined by a boolean expression

y-XjX2.V XjXjX ,, {ll

where X ,, Ho i signals respectively

at the outputs of the counters, and

y is the output signal of the neiuiiijiiiii ora.

The signals from the outputs of deshi ratir arrive at the inputs of the elements of the transfer. If all the bits of the successive codes at the outputs of the shift registers are the same, then, according to expression (1), logical O is maintained at the outputs of the decoder and the transfer elements are locked. If in any code bit in one of the channels, for example, in a channel, there is a signal different from signals in two channels, for example, in channels and that corresponds to a failure in the channel counter, then the logical 1 transfer element is formed at the output of the channel decoder the channel counter code is recorded in the channel counter, i.e. information is recovered in the counter of one of the channels.

Due to the fact that the pulses arriving at the shift inputs are located between the counting pulses, information is restored in a time shorter than T (where T is the period of the counting pulses).

The signal from the outputs of the last bits of the counters goes to the majority elements, therefore failures in one of the counters do not affect the output signals.

Thus you raise; the reliability of the operation of a redundant scaler.

Claims (1)

1. Authors sweep USSR N9 255990, class Q 00 11/00, 03/23/69. 2, CCCF Copyright Certificate No. 429536, cl. H 03 K 23/09, 10/14/70. ATR appl g it g Phie2