SU930217A1 - Time interval to digital code converter - Google Patents

Description

The invention relates to techniques for measuring time intervals, in particular to measuring time intervals specified by pulse signals, and can be used to convert time intervals. fishing in digital code.

A known converter of time intervals into a digital code that contains a control trigger, the first output of which is connected to the first inputs of the second and third valves, and the second output of this trigger is connected to the first input of the first 'valve, the second input of which is combined with the second input of the third valve and connected to entry count pulses with a period T _o, and the output of the first gate is connected to the input of the delay line at time T _of 0.5, the output of said delay line is coupled to the second input of the second gate, whose output Port nen a trigger input for setting accuracy indication, the third gate output is connected to the counting input of the first L1) of the counter latch.

A disadvantage of the known device is the low accuracy.

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Closest to the proposed technical essence is a converter 'containing a generator of a quantizing pulse sequence, the output of which is connected to the first input of the valve, the second input of which is connected to the first output of the trigger, and the output of the valve is connected to the input of the first section of the delay line, consisting of η connected in series sections, and the counter input, the second trigger output is connected to the first inputs η matching circuits, the second inputs of which are connected to the outputs of the corresponding sections of the delay line , Output matching circuits are connected to inputs of decoding and display unit t2].

_ _{n The} known converter has low conversion accuracy when operating in a wide temperature range due to changes in the delay line parameters. In addition, the known Converter does not provide the conversion of the initial portion of the time interval due to the non-synchronization of the start pulse in relation to the Ampulses of the quantizing generator followed by the pulse duration.

The purpose of the invention is to convert the development of the initial time shaft.

The goal: • increase of accuracy due to pre-stage of the inter, η η AND-NOT elements, connected to the AND-NOT over-element, and indication, up to 15 two blocks are highlighted - η element 20 is achieved by the fact that [into the time interval converter is 5 times a digital code containing a trigger, the inputs of which are connected to the start and stop pulse buses, a pulse generator, the output of which is connected to the first input of the valve, the output of which is connected to the input of the counter of delay elements, the output of the i-ro element by the input (i + l) -ro decryption unit for complementary introductions, η delay elements, Comrade NAND, inverter and b-trigger, and the output of the pulse generator through the inverter is connected to the C input of the D-trigger, the first output of which is connected to the second input of the valve and the first input of the first allocation unit, the second input of which is connected to the first output of the trigger, the second whose output is connected to the D input of the D-flip-flop and the first input of the second allocation unit, the second input of which is connected to the second output of the D-flip-flop, and the output is connected to the combined first inputs of the additional AND-NOT elements, the i-ro output of the additional AND-NOT element i-th an additional delay element is connected to the i-th input of the first group of inputs of the decryption and indication unit and the second input (i + D-th additional element

AND-NOT, the output of the first selection block is connected to the combined second inputs of all AND-NOT elements, the output of the i-ro AND-NOT element through the i-th delay element 40 is connected to the i-th input of the second • group of inputs of the decryption unit and indications.

In addition, delay elements are made in the form of RS-triggers, S inputs of which are inputs of delay elements, R inputs are combined, and outputs are outputs of delay elements.

Figure 1 shows the block diagram of npe ~ 5Q of the educator of time intervals in a digital code; figure 2 is a diagram of the operation of the Converter; in Fig.3 an example of the execution of the selection block and delay elements; figure 4 is a diagram of the conversion process of the initial portion of the time interval.

The converter contains a trigger 1, an inverter 2, a D-trigger 3, a pulse generator 4, a valve 5, a counter 6, allocation blocks 7 and 8, AND elements NOT 9-1-9-p, delay elements 10-1-10-p , additional elements AND NOT ll-1-ll-n, additional delay elements 12-1-12-p, decryption and indication unit 13.

Pa fig. 2 designations are accepted: and impulses at the output of the generator of 4 impulses; b - pulses at the output of the inverter 2; in - the signal at the second output of trigger 1; g is the signal at the first output of trigger 1; d - signal · at the first output of the D-trigger 3; e signal at the second output of the D-tr'igger 3; g - pulse at the output of block 7 allocation; h -. pulses at the output of block 8 allocation; and - pulses at the output of the valve 5; t _x - the duration of the converted time interval; - the initial portion of the converted time interval; - the final section of the converted time interval; ΐ ₀ is the pulse repetition period at the output of the generator 4.

Fig. 3 shows an example of a specific implementation of the allocation unit 7 and the delay elements ΙΟ-ΐΉΟ-η, where the allocation unit 7 is made on the OR-NOT element 14, 9-1-9-p - these are the NAND elements, and the delay elements 10 -1-10-p are 'RS-flip-flops made on the elements AND-NOT 15-1-15-2P.

Figure 4 marked: K is the signal at the output of block 7 allocation; L signal at the output of the delay element 10-1; M is the signal at the output of the I-PE 9-2 element; H is the signal at the output of the delay element 10-2; O - 'at the output of the last of the triggered elements AND-NOT 9-1, 9-2 ... 9-p; Cp is the minimum duration at the output of the AND-NOT element at which the RS-trigger, which is a delay element, is triggered.

The closest synchronizing differential input to the synchronization input of the D-trigger (Fig. 2 b), after the appearance of the pulse front (Fig. 2 c), transfers the D-trigger to a single state, and the nearest synchronizing differential received after the decay of the pulse (Fig. 2 c) ), puts the D-trigger in a state of logical zero. In figure 2, such differences are differences from the level of logical zero (low level) to the state of the logical unit (high level). At the time of switching the D-trigger 3 to the state of the logical unit (Fig.2 d) at the second input of the valve 5 there is a logic zero level (Fig.2 a), prohibiting a change in its output voltage (Fig.2 and). This achieves the supply to the input of the counter 6 when you turn on only whole pulses (figure 2 and). Similarly, _t closes the valve 5 on the decline of the signal (Fig.2 d). At the same time, only integer pulses are formed at the input of the counter 6 (Fig. 2 and). This ensures the operation of the counter 6 in a stable mode without failures.

From the diagrams in Fig. 2, one can write the following relation for the size of the converted interval t * (Fig. 2 c)

ΔΪ _α = Ν> С _{0 (} (1) where N is the number of integer periods located 5 within the signal (Fig.2 e) at the second input of the valve and fixed counter 6 in the form of the number of pulses (Fig.2 and).

From expression (1), after 10 permutations, the expression for t _x

Cl)

IE expression (2) shows the transformation algorithm t _x . The first term '5 NC _{0 is} obtained in counter 6. The second and third terms are obtained using the block Ί highlighting, NAND elements 9-1-9-p, 10-1-10-n delay elements 20, and block, respectively 8 allocation, elements AND 11-11-1-11, elements 12-1-12-p delay.

The operation of subtracting from the value is carried out in block 13 25 decryption and indication, Block 13 decryption and indication can be implemented, for example, in the form of a computer-based microprocessor.

The transformation Δΐί, and dF ^ 30 occurs identically to each other, therefore, we consider only the process of converting the quantity (Fig. 2 g). Over the signals (figure 2 guide) is a logical operation OR-HE for direct 35 logic, or, which is the same thing, logs. A NANDIC operation for negative LOGIC. '

An example of a device that implements the specified logical operation for dd direct logic in the form of a standard logic element is shown in Fig.Z. .

A pulse of dT _l duration (Fig.

g) enters the combined inputs of the elements 45 and — NOT 9-1-9-p and, passing through these elements sets the previously reset to zero state, the corresponding RS-triggers that perform the function of the delay elements 10-1-10-p in single state. From figure 4 it is seen that with the passage of the elements AND 9-1-9-p, and elements 10-1-10-p the signal duration at the outputs of the elements AND with large numbers gradually decreases, compared with the original the value of dT _l (figure 4 KO). At a certain value. duration (fig.4o) At the output of one of the elements 9-1-

9- p, the last 60 of RS-triggers, elements are triggered

10—1—10 — η delays. The conversion process ends here, the number of | Triggers set to a single state displays a value with 65 resolution, determined by the sum of the delays in two series-connected logic elements of the same type. The error ', the conversion consists of the error of blocks 7 and 8 highlighting the conversion error with the help of AND elements and delay elements. Component due to the second and third terms in the expression (2) (3)

In a first approximation, we can assume that the signals generated at the first and second outputs of trigger 1 have the same duration t _x , and the pulse fronts (Fig.2 c, d) coincide. Then, taking into account the signal delays in D-flip-flop 3 and allocation blocks 7 and 8, the absolute error value can be written in the form

Act - absolute error of the increment;

% _op ~ delay of the D-trigger during the transition from a logical zero state to a logical unit state;

“Delays of the allocation block 7 during the transition of the output level, respectively, from the state of the logical unit to the state of logical zero and vice versa;

* ι \ ₀₈ Лр - delays of the block 8 of division, during the transition of the output level, respectively, from the state of the logical unit to the state of logical zero and vice versa,

From the expression (4) it is seen that the absolute error of the increment due to the allocation block is close to zero provided that the equal delays of the allocation blocks 7 and 8 are equal. The last condition is fulfilled, for example, when using as elements of blocks 7 and 8 the allocation of logical elements from the composition of one integrated circuit.

Since the discreteness of the used * delay elements in the proposed converter is determined by the serial connection of two of the same logical elements, there is a mutual compensation of the temperature instability of each of the logical elements. Consequently, introducing errors into the transformation with a change in temperature

Ί labeled due to the mutual compensation of changes in the delays of the NAND 9-1-9-p elements and the 15-1-15-2p elements included in the RS-triggers.

The proposed converter is implemented completely on 5 integrated circuits, which significantly increases the accuracy and reliability of the conversion, both by eliminating the possibility of a meter failure, and due to the increased reliability of the element 10. PS.

Claims (2)

The invention relates to a technique for measuring time intervals, in particular, to measuring time intervals specified by pulse signals, and can be used to convert time intervals to a digital code. The known time interval converter is a digital code that contains a control trigger, the first output of which is connected to the first inputs of the second and third valves and the second output of the specified trigger is connected to the first input of the first valve, the second input of which is combined with the second input of the third valve and connected to the input of the counting pulses with the period TO, and the output of the first valve is connected to the input of the delay line at a time of 0.5 Td, the output of the specified delay line is connected to the second input of the second valve, the output of which nen a trigger input for setting accuracy indication, the third gate output is connected to the counting input of the first flip-flop til counter. A disadvantage of the known device is low accuracy. The closest to the proposed technical entity is a converter containing a quantizing pulse sequence generator, the output of which is connected to the first input of the valve, the second input of which is connected to the first output of the trigger, and the output of the valve is connected to the input of the first section of the delay line the connected sections, and the counter input, the second trigger output is connected to the first inputs n of the coincidence circuits, the second INPUT 91 of which are connected to the outputs of the corresponding sections of the delay line, the outputs of the coincidence circuits are connected to the inputs of the diversification module and the indices (2. The known converter has a low conversion accuracy when operating in a wide range of temperatures, due to changes in the parameters of the delay line. In addition, the known converter does not provide the conversion of the initial portion of the time interval due to the non-synchronic arrival Old; Tovogo pulse relative to the pulses of the generator quantizing pulse sequence. The purpose of the invention is to improve the accuracy of the conversion by converting the initial portion of the time interval. The goal is achieved by the fact that in the time interval converter into a digital code containing a trigger, the inputs of which are connected to the start and stop buses, a generation of pulses, the output of which is connected to the first input of the valve, the output of which is connected to the counter input, n delay elements, n I-NOT elements, the output of the i-ro element is connected to the nej input of the (1 + 1) -th element and the NID, the decryption and display unit, two additional selection blocks are added, n delay elements, n elements AND-NOT, the inverter and the L-trigger, and the output of the generator the torus through the inverter is connected to the C input of the D-flip-flop, the first output of which is connected to the second input of the valve and the first input of the first selection unit, the second input of which is connected to the first output of the trigger, the second output of which is connected to the D input of the D-flip-flop and the first input of the second block selection, the second input of which is connected to the second output of the D-flip-flop, and the output is connected to the combined first inputs of additional elements AND-H output of the 1st additional element AND NOT through the i-th additional delay element connected to the 1st the input of the first group of inputs of the decryption and display unit and the second input of the (1 + 1) -th additional element I-PE, the output of the first selection block, is connected to the combined, second inputs of all I-I elements, the output of the i-ro I-NE through the i-th delay element it is connected to the i-th input of the second group of inputs of the interpretation and and diction block. In addition, the delay elements are made in the form of RS-trigger, the S inputs of which are the inputs of the delay elements, the R inputs are combined, and the outputs are the outputs of the delay elements. Figure 1 shows the block diagram of the conversion of time intervals into a digital code; figure 2 is a diagram of the operation of the Converter; in FIG. 3 an example of the execution of the allocation unit and the delay elements; Fig. 4 is a diagram of the process of converting the initial portion of the time interval. The converter contains a trigger 1, an inverter 2, a D-trigger 3, a generator of 4 pulses, a valve 5, a counter 6, blocks 7 and 8 of the extraction, elements AND-NO 9-1-9-n, elements lO-1-lO-n , additional elements AND-NOT 11-1-11-p, additional elements 12-1g12-p of the delay, block 13 interpretation and indication. FIG. 2 accepted designations: a -, the pulses at the output of the generator 4 pulses; b - pulses at the output of the inverter 2; in - the signal at the second output of the trigger 1; g - signal at the first output of the trigger 1; d - signal at the first output of D-flip-flop 3; e signal at the second output of D-flip-flop 3; W is the pulse at the output of the extraction unit 7; 3 - Dpl pulses at the output of block 8 discharge; and - the pulses at the outlet of the valve 5; tx is the duration of the time interval to be converted; il - the initial part of the converted time interval; - the final portion of the time interval to be converted; CQ is the period of the following pulses at the output of the generator 4. FIG. 3 shows an example of a specific implementation of the allocation unit 7 and delay elements lO-1-MO-n, where the allocation unit 7 is performed on the element OR-HE 14, 9-1-9- n are the IS-NOT elements, and the delay elements 10-1-10-n are RS-flip-flops made on the AND-NE elements 15-1-15-2P. In Fig. 4, the following is marked: K - signal at the output of the extraction unit 7; L signal at the output of the element 10-1 delay; M - the signal at the output of the element. AND-NOT 9-2; H - signal at the output of the delay element 10-2; About - at the output of the last of the triggered elements AND-NOT 9-1, 9-2 ... 9-p; Tr is the minimum duration at the output of the NAND element, at which the RS-flip-flop is triggered, which is a delay element. The nearest synchronizing edge, which arrives at the synchronization input of the D-flip-flop (figure 2b), after the appearance of the pulse front (figure 2c) translates the D-flip-flop to one state, and the nearest synchronizing differential that arrives after the impulse decays (FIG. 2 c) puts the D-flip-flop in the logical zero state. In Figure 2, such differences are differences from a logical zero level (low level) to a state of a logical unit (high level). At the moment of switching the D-flip-flop 3 to the state of a logical unit (Fig. 2 d), at the second input of the valve 5 there is a logic zero level (Fig. 2 a) prohibiting a change in its output voltage (Fig. 2 and 2). This achieves the feed to the input of the counter 6 when only whole pulses are turned on (Fig. 2 and). Similarly, the closing of the valve 5 on the decline of the signal (figure 2 d). Nr this at the input of the counter b also form; from the beginning only whole ig pulses (figure 2 and). Thus, the operation of the counter 6 in a steady mode without failures is ensured. From the diagrams in Fig. 2, the following relation can be written for the value of the interval t to be converted (Fig. 2c), -. .tro ,, (1) where N is the number of integer periods that fit within the signal (Fig. 2 at the second input of the valve and recorded by counters 6 as the number of pulses (Fig. 2 and). From expression (1), it is obtained after permutation the expression for t .C (j + 4c; - 4- From the expression (2) we see the algorithm for the conversion of t. The first term NCp is obtained in counter 6. The second third term is obtained and obtained using, respectively, block 7 of the allocation, the elements AND-NOT 9-1 -9-p, lO-1-lO-n delay elements and allocation block 8, 11-1-11-I AND-elements, 12-1-12-p delay elements, subtract from dG values and carried out in the unit 13 of twofreezing and indication. The unit 13 of interpretation and indication can be implemented, for example, in the form of calculating bodies based on a microprocessor. The conversion of u and uCij is identical to each other, therefore, we consider only the process of transforming the value (Fig. g) Signal (FIG. 2) is a logical OR operation NOT for direct logic, or, equivalently, a logical NAND operation for negative logic. . An example of a device that implements the specified logical operation for direct logic as a standard logic element is shown in FIG. The impulse with duration ds (Fig. 2 g) enters the combined inputs of the elements AND-HI 9-1-9-n and, passing through these elements, sets the previously reset to the zero state corresponding RS-flip-flops, performing the function of elements 10 -1-10-p delay in one state. It can be seen from Fig. 4 that as the AND-HES 9-1-9-n elements pass through, and the lO-l-10-n elements pass, the signal duration at the outputs of the NAND elements with large numbers gradually decreases, as compared to the initial value dT (figure 4 to-o). For some value. Chr duration (Fig. 4o) At the output of one of the elements 9-19-p, the last of the RS-flip-flops, lO-1-lO-n delay elements, is triggered. At this the conversion process ends, the number of | Triggers set to one indicates the value Af with a discreteness determined by the sum of the delays in two consecutively connected logical elements of the same type. Error: the conversion consists of the error of blocks 7 and 8 of the conversion error using the NAND elements and the delay elements. t of the second and third terms in expression (2) to the first approximation, we can assume that the signals generated at the first and second outputs of trigger 1 have the same duration tf, and the edges of the pulses (Fig. 2c, d) are the same. Then, taking into account the signal delays in O -trigger 3 and blocks 7 and 8 of the highlighted value of the absolute error, can be written as W). C4) whereAd. - absolute increment error; Cp - - D-flip-flop 3 delay when transitioning from a state of logical zero to a state of logical one; delays of the allocation unit 7 at the transition of the output level, respectively, from the state of logical unity to the state of logical zero and vice versa; delays of block 8 - division, at the transition of the output level, respectively, from the state of a logical one to the state of a logical zero and vice versa. From expression (4) it is clear that the absolute error of the increment due to the allocation unit is close to zero provided that the delays of the same name are equal to the allocation units 7 and 8. The latter condition is fulfilled, for example, when using blocks 7 and 8 of separating logical elements from the composition of one integrated microcircuit as elements. Since the discreteness of the delay elements used in the proposed converter is determined by the successive combination of two similar types of logic, the elements occur compensation of the temperature stability of each of the logical elements. Consequently, the introduction of an error into the transformation at a change in temperature is significantly weakened due to the mutual compensation of the measurements of the delays of the AND-HE elements 9-1-9-n and the 15-1-15-2p elements included in the CB-triggers. The proposed converter is implemented completely on integrated circuits, which significantly improves the accuracy and reliability of the conversion, both by eliminating the possibility of a meter counter, and due to the increased reliability of the element ba. Shl. Claim 1. Transducer of time intervals into a digital code containing a trigger, whose inputs are connected to start and stop buses, a pulse generator, the output of which is connected to the first input of the valve, whose output is connected to the counter input, n elements delays, n I-NOT elements, output of i-th delay element is connected to the first input (i + D-ro element of NAND, decryption and display unit, characterized in that, in order to increase the conversion accuracy by converting the initial portion of the time interval meni About additionally there are two allocation units, n delay elements, n I-N elements, an inverter and a D-flip-flop, with the output of the pulse generator through the inverter connected to the C input of the D-flip-flop, the first output of which is connected to the second input; the input of the first i allocation unit, the second input of which is connected to the first output of the trigger, the second output of which is connected to the D input of the D flip-flop and the first input of the second selection unit, the second input of which is connected to the second output of the D flip-flop, and the output connected to the combined first inputs and additional elements AND-HB, the output of the 1st additional element AND-NOT through the 1st additional delay element is connected to the i-th input of the first group of inputs of the interpretation and display unit and the second input (i + l) -ro of the additional element I- NOT, the output of the first block of the division is connected to the combined second inputs of all AND-NES elements, the output of the i-ro element of the NAND is connected via the i-th delay element to the i-th input of the second group of inputs of the interpretation and display unit. 2. The converter according to claim 1, characterized in that the delay elements are in the form of RS triggers, the S inputs of which are the inputs of the delay elements, the R inputs are combined, and the outputs are the outputs of the delay elements. Sources of information taken into account in the examination 1. The author's certificate of the USSR 613500, cl. H 03 13/20, 1976. 2.Balashev V.P. Automation of radio measurements, 1966, p. 288, fig.5. i25 (prototype) yg for