SU764114A1 - Device for converting pulse recurrence frequency - Google Patents

Description

The invention relates to a pulse technique and can be used in automatic control systems, in frequency meters, in synchronizers and other devices where frequency grids are required that can be changed in a wide range with any resolution.

To convert the pulse repetition rate in a wide range, multipliers and frequency dividers with different division factors are used. ₁₀

A device for multiplying and dividing signals, containing a calibration frequency source, a counter for entering the frequency change coefficient, counters for determining the value of the filling period of the input 'counter- _{] 5} ka and valve, and the coefficient of change of the input frequency variable is entered as a parallel code [1] .

This device operates with low accuracy _Μ NOSTA due to the use therein of the adder with s-amosbrosom at which overflow of the information is lost. In addition, in the transition from the operation of multiplication to operation deed2

Frequency change requires a wide variation of the capacitance of the adder.

The closest in technical essence to the invention is a device containing two sources of calibration frequencies f ^, f, the first code converter in the time interval, a pulse counter, register, and also the second code converter in the time interval, several triggers, valves and delay lines [2 ].

However, during the reset of the pulse counter and during code entry into the second converter, the pulse of the calibration frequencies is not counted, which reduces the accuracy of the device. The ratio of the calibration frequencies f _R > can spontaneously change over time, for example, when the ambient temperature changes, which also reduces the accuracy of the device. Maintaining a constant ratio when using tunable calibration frequency generators is quite difficult.

............................. '3 ^J - - 764114

The code in the second converter can be weighted ... .. - _tis £ distortion if the input takes place in the moment of change of information in the register. This leads to a malfunction of the entire device, i.e. reduce its reliability.

The aim of the invention is to improve the accuracy and reliability of the device.

The goal is achieved by the fact that in the device for converting the pulse repetition rate, comprising a pulse counter and sequentially connected register and code converter in a time interval, a discrete code generator, a multipole switch and a control unit are introduced, the first three inputs of which are connected to the buses | ₁₅ input and calibration signals and with the installation bus '' 0 ”, the first two outputs - with the counting and installation inputs of the pulse counter, whose CODE is connected via a serial generator of a discrete set of codes and a ₂ θ multi-pole switch to the information input of the register, the third Output the control unit is connected to the control input of the register, and the remaining outputs are connected to the inputs of the code converter in a time interval, the ₂₅ output of which is connected to the fourth input of the control unit.

The code converter in the time interval contains a counter of calibration pulses and a series-connected register, a comparison element, and a prohibition element, while the outputs of the control unit are connected to the installation input of the register, which allows the input of the prohibition element and to the installation and counting inputs of the calibration pulse counter, the output of which is connected to the input of the comparison element.

In FIG. 1 is a structural electrical diagram of a device for converting a pulse rate; in FIG. 2 diagram of the control unit.

The device comprises a pulse counter 1, a shaper 2 of a discrete set of codes, a multi-pole switch 3, a register 4, a code converter 5 in a time interval consisting of a register 6, a comparison element 7, a counter 8 of calibration pulses and a prohibition element 9. The device also includes a control unit 10 , which contains a counter 11 for two digits, a decoder 12, RS-triggers

1.3-16, elements AND 17-20, element OR 21, element NOT 22, 23. single pulse generator ⁰ ow, counter 24 for two digits, decoder 25, RS triggers 26-30, elements 31-34, elements OR 35, 36, 37, calibration signal bus 38, input signal bus 39, setting bus 40 “0”. _______. The device operates as follows.

The calibration frequency f _R from the bus 38 through the element And 19 is fed to the input of the counter 1.

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......... ..c ₄

The code removed from the counter I is sent to the shaper 2, which generates a set of codes that differ from the input one Nj times (N! Is the conversion coefficient).

_m 'J1 2 2 h ⁴ 1 <4. 2.. '2 / m h where is the current value of the conversion coefficient;

transformation parameters, m, η

Shaper 2 is based on the shift schemes of the code supplied to the input of the converter, to the right by 1,2, 3, ---, η bits (dividing the code into 2, 4, 8, ..., 2 ^П times) and to the left by 1, 2, 3, .... m digits (multiplying the code by 2.4.8, ... 2 times).

Shear schemes allow one to obtain codes with conversion coefficients:

) 21i 22.1 ^ 11,2,2 ^, 2 ^ .... 2 ^^

To obtain codes with intermediate conversion coefficients, previously obtained (by shifting) codes are added in various combinations. So, for example, the code ^ _n 4,1 5?

obtained by adding ⁺ jK-i> ^K ° D ~ 1.4, 1 by adding + ^ _t +, etc.

When m = η = 3, at the outputs of the shaper there is a set of chips with coefficients m, η = 1. 2, 3, ..

1v'a * v 'Bia -8>₃; ^ D4.5D7}. .

^ Thus, in ^ shaper 2, multiple codes are generated simultaneously. These codes go to the multi-pole switch 3, which consists of switches and adders. The number of switches is equal to the number of codes at the output of the transform node, i.e. 2 ^P + 2 ^t - 2. The same category of outputs from the switches go to the assembly. At the output of the assemblies, the selected code passes. Management of the switches (permission to pass the code) is carried out automatically or manually from two switches of integer and fractional parts of the conversion coefficient, and each switch has its own group of switches. The selected codes corresponding to the integer and fractional conversion coefficient enter the adder, where they are added.

Upon the arrival of a pulse of the input frequency, the code from the output of the multi-pole switch 3 is received at the input of register 4, from where it is copied to register 6 of converter 5. From the output of register 6, the code is sent to comparison element 7, to the other input of which the code comes from counter 8. At the time of comparison codes, a pulse of the output frequency is generated to the parts on ^f BX / _B1X - The _{operation of the} entire device is organized by the control unit 10. With the arrival of the setting signal “0”, the counters 11, 24 are set to the initial position, the outputs “00” of the decoders 12, 25 appear by false potentials 5, triggers 15 and 26 are set to a single state, triggers 13, 16, 27 - 30 are in the zero state, and trigger 14 remains in an arbitrary position. This state of the control unit is maintained until the first input pulse f arrives. At the moment of the pulse arrival f, the single pulse generator 23 is triggered, the positive pulse from the output of which sets the trigger 13 to a single state, 15 inhibit is applied to the element And 19, and the impulses f to the counting input are stopped counter 1, resolution 18 is applied to element And 18 and calibration pulses f go to the counter input of counter 11. After four clock pulses jq have passed, the operation of these elements stops until the next uyuschego input pulse frequency.

The purpose of the signals removed from the outputs of the decoder 12 is as follows; The signal from the output) ”01” through the open element I. 20 sets the trigger 14 to a single position, thereby granting permission to write the code from the output of the multipole switch 3 to the control input of register 4. The signal from the output “10” resets trigger 14 to the zero jq state, thereby 'writing to register 4 is stopped. The signal from the output “11” sets counter 1 to its initial state, writing · the code “4” into it. This is necessary so that there is no loss of information about the interval of the input pulses during the operation of the counter

11. This improves the accuracy of the proposed device. In addition, this signal sets the trigger 16 in a single state, thereby preparing part of the control unit 12 to turn off the counter 11 after the arrival of the fourth clock pulse. The signal from the output ”00” is supplied to the element And 17.

At the moment of coincidence of the positive signal taken from the unit arm of trigger 16 and the positive signal from the output of element NOT 22, element 17 is activated and, through element OR 21, throws trigger 13 to the zero state. Element And 18 closes and turns off the counting input of counter 11, and clock pulses through the open element And 19 begin to flow to the counting input of counter 1. The positive potential taken from the zero shoulder of trigger 13 goes to the input of trigger $$ 16 and sets it to zero .

The output frequency pulse f _RbIX , passing through the OR element 37, sets the trigger 28 to a single state, the I 33 element is inhibited and the calibration pulses are stopped at the counter input of the counter 8, the resolution and calibration pulses are fed to the And 32 element, _t starts to arrive to the counting input of the counter 24 After four clock pulses pass, the operation of the other part of the control unit stops until the next output pulse arrives.

The purpose of the signals taken from the outputs of the decoder 25 is as follows. The signal from the output ”01” sets the counter 8 to its original state, writing the code “4” into it. This is necessary to avoid loss of information about the interval of the output pulses during operation of the counter 24. This increases the accuracy of the device. The signal from the output “10” of the control unit serves as a permission to rewrite the code in register 6 from register 4. In addition, this signal sets trigger 27 to a single state. The output signal ”00” passing through the element And 31 and the element OR 35, sets the trigger 28 to zero. Element And 32 closes and turns off the counting input of counter 24, Element And 33 opens and calibration pulses begin to flow to the counting input of counter 8. A positive potential from the zero arm of trigger 28 transfers the trigger 27 to zero.

In order to prevent accidental ejection at the output of the device when changing the code in register 6 and when setting the initial state of counter 8, trigger 29 is provided. Pulse f _{Bb | X} through element OR 36 sets trigger 29 to zero, inhibit element 9 is blocked and a false pulse with the output of the comparison element 7 does not pass to the output of the device. The prohibition element 9 opens only after the trigger 29 is set to a single state, i.e. after the signal appears at the output “00” of the decoder 25 and, therefore, after the code in the register 6 is changed and the counter 7 is set to its original state.

To eliminate malfunctions in the device, it is necessary that when overwriting the code from register 4 to register 6, the code in register 4 does not change. This is achieved by applying a circuit consisting of an RS-flip-flop 15 and an And 20 element. One clock cycle before the code is overwritten, the Trigger 15 is set to zero by the signal from the “01” output of the decoder 25 and locks the And 20 element. This prohibits the passage of the signal from the output “01” of the decoder 12 and, therefore, to change the code in register 4. If the code change in register 4 already occurs, then it has time to finish by the time of overwriting in register 6. At the end ₍

764114 8 rewriting trigger ^ 15 is set to a single state by the signal from the output “00” of the decoder 25. The use of a circuit consisting of a trigger 15 and an element And 20 increases the reliability of the proposed device. ₅ The first output pulse must be generated no earlier than the time interval between the first and second input pulses is measured. This is achieved by applying a circuit that consists of RS-flip-flops 26, to 30 and element And 34. After the setting signal “0”, trigger 26 is set to a single state and gives permission to element And 34. After the arrival of the first pulse f, counter 11 starts working and the decoder 12. and the signal appearing at the output “00” of the decoder 12, through the element And 17 sets the trigger 30 to a single state and the second resolution is supplied to the element And 34. The third resolution for the And 34 element comes from the output jo ”10” of the decoder 12 after the arrival of the second impulse f _Βχ. At the same time, the positive potential appears at the output of the And 34 element, which sets the trigger 28 to the single state through the OR 37 element. 25

The positive potential that appears at the output “01” of the decoder 25 resets the trigger 26 to the zero state, the AND element 34 closes.

The described device, depending _on which factor Ν ^ is set, can work both for division and for frequency multiplication. For> 1, it performs division; for N, ^ <1 is the multiplication.

Using the device allows you to get the frequency variation coefficients in a wide range without restructuring the calibration generator, while in the prototype of the two available calibration generators one needs to be rebuilt all the time. The adjustment of the frequency change coefficient in a wide range (from 0 to 7) is carried out only by setting the multi-pole switch in the desired position. Further \ extension of the range of 'frequency variation coefficients is made by changing the number of adders, which is not difficult when using standardized nodes.

Claims (2)

The invention relates to a pulse technique and can be used in automatic control systems, in frequency meters, synchronizers and other devices where frequency grids varying in a wide range with any discreteness are required. Multipliers and frequency dividers with different division factors are used to convert the pulse frequency in a wide range. A device for multiplying and dividing signals, containing a source of calibration frequency, a counter for inputting a frequency variation factor, counters for determining the value of the filling period of an input counter and a valve, and the variable variation rate of an input variable frequency is entered in the form of a parallel code 1. This device works with low accuracy because of the use in it of an adder with a c-outlier, with overflow of which some of the information is lost. In addition, during the transition from the multiply operation to the operation of the frequency, it is necessary to change the capacity of the adder over a wide range. The closest in technical essence to the invention is a device containing two sources of calibration frequencies f, f, a first code converter in a time interval, an ipulse counter, a register, and also a second code converter in a time interval, several triggers, gates and delay lines 2. However, during the reset of the pulsewave counter and during the code entry into the second converter, the calibration pulses are not counted, which reduces the accuracy of the device. The ratio of calibration frequencies to k can spontaneously change during time, for example, when the ambient temperature changes, which also reduces the accuracy of the device. Maintaining the ratio of k. To a constant when using tunable oscillators of the calibration frequency is quite difficult. The code in the second converter can be attributed to WCCb. With distortions, if input occurs at the moment of changing information in the register. This leads to a failure of the entire device, i.e. reduce its reliability. The aim of the invention is to improve the accuracy and reliability of the device. The goal is achieved in that the device for converting the pulse frequency, containing a pulse counter and a serially connected register and a code converter to the time interval, is entered into the form of a g) discrete set of codes, a multi-pole switch and a control unit, the first three inputs of which are connected to tires | input and calibration signals and with the installation bus O, the first two outputs are from the counting and setting inputs of the pulse counter, you Xopfkotoporo through a serially connected discrete code generator and a multi-pole switch connected to the information input of the register, the third control unit is connected to the control input of the register , and the remaining outputs - with the inputs of the code converter in the time interval, the output of which is connected to the fourth input of the control unit. The code converter in the time interval contains a counter of calibration pulses and a serially connected register, a comparison element, and a prohibition element, while the outputs of the control unit are connected to the register setup input, the enable input of the prohibition element, and the calibration counter counters, the output of which is connected to input element comparison. FIG. 1 shows a structural electrical circuit of a device for converting a pulse frequency; on fi1. 2 is a control block diagram. The device contains a pulse counter 1, a shaper 2 of a discrete set of codes a multi-pole switch 3, a register 4, a code converter 5 in a time interval consisting of a register 6, a comparison element 7 of a counter 8 of calibration pulses and a prohibition element 9. The device also contains a control unit 10, which contains a counter for two bits, a decoder 12, RS-flip-flops 1.3-16, elements AND 17-20, an element of OR 21, an element of HE 22, a generator of 23 single pulses, a counter of 24 for two bits, a decoder of 25 RS- triggers 26-30, elements AND 31-34, elements OR 35, 36, 37, the calibration signal bus 38, the input signal bus 39, the O. installation bus 40,. The device works as follows. The calibration frequency f from the bus 38 through the AND 19 element is fed to the input of counter 1. The code taken from counter 1 is fed to the imaging unit 2, which generates a set of codes from) received from the input N, times (N, is the conversion factor). N, Hi-l --- i4-4i4 ti i-: 2 ° -2%; -2- l where N - is the current 3 transformation of the conversion factor; t, n - transformation parameters, t, n 1, 2, 3, ... Shaper 2 is built on the code shift schemes, which enter the converter input, to the right by 1,2, 3, ---, n bits (code division 2, 4, 8, ..., 2 times) and to the left by 1, 2, 3, ..., m bits (code multiplication by 2,4,8, ... 2 times). The shift schemes allow to obtain codes with transformation coefficients: | M - (.1 J-. J-. ± .j о n2rjb l ПИП1 l2. () 2.12г2 /., 2, ... /;. 2. J For obtaining codes with intermediate conversion coefficients, previously obtained (by shifting) codes are put in different combinations. So, for example, kodg, 2R - 1 is obtained by adding 1 1 by adding gf ofFr 5tvi; etc. When m n 3, at the output of the imaging unit there is a set of arrays with the coefficients N; lsii; B; af-f.iji..M ... Thus, in the imaging unit 2, many codes are generated simultaneously. These codes are fed to a multi-pole transducer lyuchatel 3, which consists of comm) pgatorov and adders. The number of switches is equal to the number of codes at the output of the conversion node, i.e. 2 + 2 - 2. Similar bits of outputs from switches go to assemblies. At the output of the assembly passes the selected code. Switching is enabled by the switches (permission to pass the code) automatically or manually from two switches of the integer and fractional parts of the conversion coefficient, each switch has its own group of switches. The selected codes, corresponding to the integer and fractional parts of the conversion coefficient, go to the adder, where they are added together. Upon arrival of the input frequency pulse f, the code from the video drive of the multi-pole switch 3 is received at the input of register 4, from where it is written to register 6 of the converter 5. From the output of register 6, the code is fed to the comparison element 7, to another input of which the code comes from counter 8. At the moment code comparison, a pulse of the output frequency of the output of the entire device is generated by the control unit 10. With the arrival of the installation signal O, the counters 11, 24 are set to the initial position, the positive potentials appear on the outputs 00 of the decoders 12, 25 , Triggers 15 and 26 are mounted in a single state, flip-flops 13, 16, 27 - 30 - in the null state, and the flip-flop 14 remains at an arbitrary position. This state of the control unit is maintained until the arrival of the first input pulse f. At the moment of arrival of the pulse fg, the generator 23 of single pulses is triggered, the positive pulse from whose output sets the trigger 13 to one state, the element 19 is inhibited and the pulses fj are stopped at the counting input of the counter 1, the element 18 is applied to the resolution and calibration impulses i are fed to the counting input of counter 11. After the passage of four clock pulses, the operation of these elements stops before the next input frequency pulse arrives. The assignment of signals taken from the decoder outputs 12, the following; Sigal from the output) Exhaust gas through the open element I 20 sets the trigger 14 to the single position, thereby sending the control input of the register 4 with permission to write the code from the output of the multi-pole switch 3. The signal from the output 10 resets the trigger 14 to the Zero state , thus, the recording into register 4 is stopped. The signal from the output of AND sets the counter 1 to the initial state by writing code 4 into it. This is necessary so that there is no loss of information about the interval of the input pulses during the operation of the counter 11. Thus, that The operation of the proposed device. In addition, this signal sets the trigger 16 to a single state, thereby preparing part of the control unit 12 to turn off the counter 11 after the fourth clock pulse arrives at it. The signal from the output 00 enters the element And 17 .. At the time of the coincidence of the positive signal taken from the single arm of the trigger 16 and the positive signal; and from the output of the element is NOT 22, the element AND 17 is triggered, and through the element OR 21, it flips trigger 13 to the zero state. Element And 18 closes and turns off the counting input of counter 11, and clock pulses through the open element And 19 begin to flow into the counting input of counter 1. Positive potential, taken from the zero arm of the trigger 13, enters the input of the trigger 16 and sets it to zero the Pulse output frequency f d,. having passed through the element OR 37, sets the trigger 28 to one state, the element 33 is banned and the calibration pulses are stopped at the counting input of the counter 8, the resolution is simultaneously applied to the element 32 And the calibration pulses begin to flow to the counting input of the counter 24 After the passage of four clock pulses, the operation of another part of the control unit is stopped until the next output pulse arrives. The purpose of the signals taken from the outputs of the decoder 25, the following. The signal from output 01 sets the counter 8 to the initial state by writing code 4 to it. This is necessary to eliminate the loss of information about the output pulse interval during the operation of the counter 24. Thus, the accuracy of the device is improved. The signal from the output 10 of the control unit serves as a permission to overwrite the code in register 6 from register 4. In addition, this signal sets the trigger 27 to one state. The signal from the output 00 passes through the element AND 31 and the element OR 35, sets trigger 28 to the zero state. Element And 32 closes and turns off the counting input of counter 24, And element 33 opens and the calibration pulses begin to flow into the counting input of counter 8. Positive potential from the zero arm of the trigger 28 flips trigger 27 to the zero state. In order to prevent the device from accidental release when changing the code in register 6 and setting the initial state of counter 8, a trigger 29 is provided. Pulse through the OR element 36 sets trigger 29 to the zero state, prohibition element 9 is locked and a false pulse from the output of the element Comparison 7 does not pass to the output of the device. The prohibition element 9 is opened only after the trigger 29 is set to one, i.e. after the signal appears at the output 00 of decipheror 25 and, therefore, already after the code in register 6 is changed and the counter 7 is reset. To eliminate failures in the device, it is necessary that when the code is rewritten from register 4 to register 6, the code in register 4 does not change. This is achieved by using a circuit consisting of the RS flip-flop 15 and the And 20 element. One cycle before the code is rewritten, the trigger 15 is set to the zero state by the output from the 01 of the decoder 25 and locks the And 20 element. from output 01 of decoder 12 and, therefore, to code change in register 4. If code change in register 4 is already in progress, then it has time to finish by the time of rewriting in register 6. At the end of 7764 rewriting, trigger 15 is set to one state by the output signal00 decoder 25. The use of a circuit consisting of a trigger 15 and an element And 20, increases the reliability of the proposed device. The first output pulse must be generated no earlier than the time interval between the first and second input pulses will be measured. This is achieved by using a circuit that consists of RS flip-flops 26, 30 and element 34. After the set signal O, trigger 26 is set to one and grants permission for element 34. After the arrival of the first pulse f. the counter 11 and the decoder 12 begin to work. The signal appearing at the output 00 of the decoder 12, through the element 17 sets the trigger 30 in one state and the second resolution is applied to the element 34. The third resolution on the AND 34 element comes from the output 10 of the decoder 12 after the arrival of the second impulse f. At the output of the AND 34 element, a positive potential appears, which through the OR 37 element sets the trigger 28 to the one state. The positive potential, which appears at the output 01 of the decoder 25, resets the trigger 26 to the zero state, and the element 34 is closed. The selected device, depending on which N coefficient is set, can work both on division and on frequency multiplication. With N-j 1, it performs division; With N. (1 - multiplication. Using the device allows obtaining coefficients of frequency changes in a wide range without rebuilding the calibration generator, while in the prototype of two existing calibration generators, one needs to be rebuilt all the time. Reorganization of the frequency change factor in a wide range ( from O to 7) is done only by setting the multi-pole switch to the desired position. Further j) acnmpeEiHe of the range of frequency change coefficients is produced by changing the number of adders, wh is not difficulties in the use of standardized components. . Claim 1. A device for converting pulse frequency, containing a pulse counter and serially connected register and a code converter in a time interval, characterized in that, in order to increase its accuracy and reliability of operation, in it a discrete set shaper, a multi-pole switch and a control unit, the first three inputs of which are connected to the input and calibration signals buses and to the installation bus O, the first two outputs to the counting and installation inputs of the counter The pulses, the output of which through a serially connected shaper of a discrete set of codes and a multi-pole switch are connected to the information input of the register, the third output of the control unit is connected to the control input of the register, and the remaining outputs to the inputs of the code converter in the time interval whose output is connected to the fourth input control unit. 2. The device according to claim 1, such that the code converter in the time interval contains a counter of calibrated Hbix pulses and a serially connected register, comparison element and prohibition element, with the outputs of the control unit connected to the setup input of the recorder , allowing the input of the prohibition element and to the installation and counting inputs of the counter of calibration pulses, the output of which is connected to the input of the comparison element. Sources of information taken into account during the Examination 1. USSR author's certificate No. 168533, cl. H 03 K 5/156, 1963. 2. USSR author's certificate number 268011, cl. H 03 K 23/00, 1968.