SU924868A1 - Rate scaler with controllable duration pulses - Google Patents

Description

The invention relates to pulsed and computational technology, in particular to frequency dividers, and can be used to obtain timing series.

Known frequency divider trace. ⁵ pulses containing a pulse counter, decoder, trigger, AND element and NOT Γ и].

A disadvantage of this divider ¹⁰ yavlya- etsya impossibility of obtaining a wide range of output pulse duration.

The closest in technical essence to the proposed one is a pulse frequency divider containing a binary pulse counter. outputs are connected to first inputs of the first and second comparison element cops _Λ, whose second inputs are connected respectively to the first and second input bus and outputs connected respectively che2 Res first and second elements overlap to S-inputs of the first and second flip-flops, in which inverse ^ sub-; are connected to the RS inputs of the third trigger and to the installation inputs of the binary counter, the direct outputs through inverters, the first and second, are connected , with the R-input of the first trigger and through the third inverter with the R-input of the second trigger, the outputs of the third trigger are connected to the second inputs of the first and second matching elements, the third input of the second matching element is connected to the inverse output ode of the first trigger [2].

This device makes it possible to adjust the duration of the output pulses. However, its disadvantage is the complexity of the device.

924 868 4

The purpose of the invention is to simplify the device.

This goal is achieved by the fact that in the pulse repetition rate divider containing a binary counter of 5 pulses, the outputs of which are connected to the first groups of inputs of the first and second comparison elements, the second groups of inputs of which are connected respectively to the first and second code W buses, and two triggers , the first input of the first of which is connected to the input bus, and the output with the installation input of the binary pulse counter and the input of the second trigger, 15 counting input of the binary pulse counter is connected to the first input of the first t iggera, second and third inputs connected to the outputs of the first and second comparison elements 20, control inputs of which are respectively connected to the direct and inverse outputs of the second flip-flop.

In FIG. 1 shows a structural diagram of a device; in FIG. 2 timelines explaining his work.

I

The device contains a binary counter — ₃₀ counts of 1 pulses, comparison elements 2 and 3, triggers 4 and 5, input bus 6, first 7 and second 8 code buses, first 9 and second 10 output buses.

Binary counter 1 is designed for counting pulse repetitions that follow ³⁵ on bus 6. During the formation of the output pulse period, the binary counter double-counts the pulses. The number of pulses calculated for the first time is proportional to the value of the code specified on the bus 8, and the number of pulses calculated for the second time is proportional to the code on the bus 7.

Comparison element 2 is used to set trigger 4 when comparing the codes ia the output of counter 1 and on bus 7 in a state in which a high level appears on the inverse output. ^fifty

The purpose of the comparison element 3 is similar to the comparison element 2, but element 3 is triggered when comparing the codes at the output of counter 1 and on bus 8. 55

Trigger 4 generates a low to high level difference for triggering of trigger 5 and a high level for initial setting of counter I. ^ Trigger 5 generates output pulses on buses 9 and 10 and controls the operation of comparison elements 2 and 3.

The pulse frequency divider with adjustable pulse duration works as follows.

In the initial state, counter 1 is reset, at the outputs of the elements 2 and 3 of comparison, high levels, on the bus 6 'low level, at the inverse output of trigger 4 and at the inverse output of trigger 5 (output bus 10) high levels, and at the direct output of the trigger 5 (output bus 9) ~ low, which blocks the operation of element 3.

A high level of the inverse output of trigger 5 unlocks element 2. On bus 7, a binary code is set corresponding to the value of the pause period of the output pulses. On bus 8, a binary code corresponding to the value of the additional duration of the output pulse. When clock pulses arrive on bus 6 (Fig. 2q), counter 1 calculates them (Fig. 2δ) to the value of the binary code on bus 7. If the codes match, the comparison element 2 produces a low level (Fig. 2t), according to which trigger 4 sets at its inverse output, high potential (Fig. 28). At the moment of transition from low to high, trigger 5 fires, forming a leading edge of the output pulse on the output buses 9 and 10 (Fig. 2e,%). A high level of inverse output of trigger 4 (Fig. 28) resets the contents of counter 1 (Fig. 2B), as a result of which the output of element 2 is again set to a high level (Fig. 2d). A change of state at the outputs of trigger 5 'leads to blocking the operation of element 2 (low level at the inverted output of trigger 5) (fig. 2 *) and to enable operation by element 3 · At the end of the input pulse, at which the code was compared, trigger 4 returns in the initial position (Fig. 2d, c) and from the installation input, the installation potential is removed, thereby allowing the counter 1 to again count to the value of the binary code on the bus 8. At the time of code comparison, the comparison element 3 (Fig. 2E) gives a low level three times heger 4 goes into a state in which a high level is set at its inverse output (Fig. 2c). A high level of trigger 4 returns the counter 1 s and element 3 to the initial state (Fig. 25.3), and a drop from low to a high level (Fig. 2c) triggers trigger 5. As a result, the output buses 9 and 10 form - 10, the trailing edge of the output pulse (Fig. 2e, *) is reset and the comparison elements are re-locked. The termination of the input pulse, at which the comparison of 15 codes takes place, returns trigger 4 to its original state (Fig. 2d, ®). The process is then repeated.

Thus, trace pulses are formed on the output buses 9 and 10.

Claims (3)

The invention relates to a pulsed and computing technique, in particular to frequency dividers, and can be used to obtain a clock series. The known frequency impulse tracer includes a pulse counter, a decoder, a trigger, an NAND element and a NOT element D. The disadvantage of this divider is the impossibility of obtaining a wide range of output pulse durations. The closest to the technical essence of the present invention is a pulse frequency follower comprising a binary pulse counter, whose outputs are connected to the first inputs of the first and second comparison elements, in which the second inputs are connected to the first and second input buses, respectively, and the outputs are connected respectively, through the first and second elements match to the S-inputs of the first and second triggers, whose inverse outputs are connected to the RS-inputs of the third trigger and to the installation inputs of the binary counter The direct outputs through inverters, the first and second, are connected to the inputs of the third coincidence element, whose output is connected to the counting input of a binary pulse counter, and the third input is connected to the third input bus, to the R input of the first trigger and through the third inverter to R by the input of the second trigger, the outputs of the third trigger are connected to the second inputs of the first and second match elements, the third input of the second match element is connected to the inverse output of the first trigger 2. This device allows you to adjust the duration awn output pulses. However, its disadvantage is the complexity of the device. The purpose of the invention is to simplify the device. The goal is achieved by the fact that in the pulse frequency divider containing a binary pulse counter, the outputs of which are connected to the first groups of inputs of the first and second comparison elements, the second groups of inputs of which are connected respectively to the first and second code buses, and two triggers, the first input of the first of which is connected to the input bus and the output to the installation input of the binary pulse counter and the input of the second trigger, the counting input of the binary pulse counter is connected to the first input of the first three ger, second and third inputs connected to the outputs of the first and second comparing elements controlling guides WMOs rows which are connected respectively to direct and inverted outputs of the second of the flip-flop. FIG. 1 shows a block diagram of the device; in fig. 2 time diagrams for his work. The device contains a binary counter of 1 pulses, elements 2 and 3 of the test, triggers 4 and 5, input bus 6, first 7 and second 8 code buses, first 9 and second 10 output buses. The binary counter 1 is designed to count the pulse of the pulse coming through the bus 6. During the generation of the output pulse period, the binary counter calculates the pulses twice. The number of pulses read the first time is proportional to the size of the code specified by the bus and the number of pulses read the second time. Prop. | In this case, the code on bus 7. Comparison element 2 serves to set trigger k when comparing the output codes of counter 1 and on bus 7 in a state where a high level appears at the inverse output. The assignment of the comparison element 3 is similar to the comparison element 2, but element 3 is triggered when comparing the codes at the output of counter 1 and bus 8. Trigger 4 forms a level difference from low to high to trigger trigger 5 and high level for initial setting of counter 1. Trigger 5 generates output pulses on tires 9 and 10 and prevents the operation of elements 2 and 3 of the comparison. A pulse frequency divider with adjustable pulse duration works as follows. In the initial state, the counter 1 is reset, at the outputs of elements 2 and 3 are high levels, on bus 6 a low level, on the inverse output of trigger 4 and on the inverse output there are three: —Gera 5 (output bus 10) are high; trigger output 5 (output bus 9) is a low level that blocks the operation of element 3. A high level of the inverse output of trigger 5 unlocks the element 2. On bus 7 a binary code is set corresponding to the pause value of the period of the output pulses. On bus 8, the binary code corresponding to the value of the additional duration of the output pulse. Upon receipt of clock pulses on bus 6 (Fig. 2c |), counter 1 calculates them (Fig. 25) to the value of the binary code value on bus 7. When the codes coincide, comparison element 2 produces a low level (Fig. 2d), on which trigger 4 establishes a high potential at its inverse output (Fig. 28). At the moment of transition from low level to high, trigger 5 is triggered by forming the leading edge of the output pulse on the output tires 9 and 10 (Fig. 2e). The high level of the inverted trigger trigger (Fig. 26) resets the contents of counter 1 (Fig. 25), with the result that a high level is again set at the output of element 2 (Fig. 2d). The change of state at the outputs of trigger 5 leads to the blocking of the operation of element 2 (low level at the inverse output of trigger 5) (fig 2.) and to the resolution of the operation of the element 3. Upon completion of the input pulse at which the codes were compared, the trigger returns to its original position (Fig. 2 (3, c)) and the potential of the installation is removed from the installation input, thereby allowing counter 1 to re-generate the count to the value of the binary code on bus 8. At the time of comparing the codes, the comparison element 3 (Fig. 23) gives a low level, according to which the trigger "4 transitions to a state where its inverse output is set to a high level (Fig. 2b). A high level of trigger k returns the counter and the element nt 3 to the initial state (figo 26, E), and a drop from low to high level (fig. 2e) triggers trigger 5. As a result, on the output tires 9 and 10, the trailing edge of the output pulse is formed (fig. 2e, hp and the comparison elements are reblocked. The end of the input pulse, at which the codes are compared, returns the trigger k to the initial state (Fig. 20, f). Then the process repeats. Thus, the following pulses are generated on the output buses and 10. , period, pause and duration of which is determined by and E of the binary code input buses 7 and 8. Compared to prior art proposed use of the frequency divider with adjustable pulse duration allows to simplify the device, i.e., reduce the number of elements and connections and, at the same time, increase the reliability of the device while maintaining its functionality. 8 Claims of the Pulse Frequency Divider with an adjustable pulse duration, containing a binary pulse counter, the outputs of which are connected to the first groups of inputs of the first and second comparison elements, the second groups of inputs of which are connected respectively to the first and second code buses, and two triggers, the first input of the first of which is connected to the input bus, and the output - with the installation input of a binary pulse counter and the input of the second trigger, characterized in that, in order to simplify the device, the account A binary pulse counter is connected to the first input of the first trigger, the second and third inputs of which are connected to the outputs of the first and second comparison elements, respectively, the control inputs of which are connected to the inverse and forward outputs of the second trigger, respectively. Sources of information taken into account in the examination 1, USSR Copyright Certificate 675603, cl, H 03 K 23/02, 1977, 2, USSR Author's Certificate of application (f 2911556, cl, H 03 K 23/02. 3, 03.80. Str ten 1 a 2. -