SU1018103A1 - Pulse time parameter digital meter - Google Patents

Abstract

DIGITAL MEASURER OF TIME-NK PULSE PARAMETERS containing the first and second comparison blocks, the first inputs of which are connected to the input bus, the reference voltage driver, the first and second outputs of which are connected to the second inputs of the first and second comparison blocks, the frequency generator, characterized in that, in order to extend the functionality when measuring single and rarely repeating time intervals, three matching elements, four AND-NOT elements and an inverter, And the output of the reference frequency generator is connected to the first inputs of the matching elements, the output of the first comparison unit is connected to the first inputs of the first and second elements AND-NOT, the output of the second comparison unit through the inverter is connected to the first inputs of the third and fourth elements AND-NOT and to the second inputs the first element AND-NOT and the first element match, the third input of the first element AND-NOT is connected to the code of the second element AND-NOT and the second input of the third element AND-NOT, the output of which is connected to. the second inputs of the second and fourth 5 V ko elements are NAND, the third input of the second element NAND is connected to the first output of the first element NAND, the second inputs of the second and third matching elements are connected respectively to the second output of the first element S NAND and to the output of the fourth element AND-NOT. oo with

Description

The invention relates to a pulse and measuring technique and can be used in digital control devices for various purposes, as well as in measuring devices and systems for determining the temporal parameters of signals. A device dp of measuring the temporal parameters of pulses is known, containing two low and high comparison circuits, a delay line generator, a pulse expander, a reference generator, a coincidence circuit, and a pulse counter. The inputs of the pulse body, whose duration is proportional to the duration of the measured time interval, are connected to the output of the comparison circuit at a low level and through the delay line to the output of the comparison circuit at a high level tlj. The disadvantages of this device are the possibility of forming a time interval only on one of the fronts of the signal under investigation, the complexity of the circuit caused by the need for an additional device to start and attach the trigger pulse to the input signal. The closest to the technical essence of the invention is a digital pulse front length meter that contains the first and second comparison blocks, the first inputs of which are connected to the pulse source bus, and the outputs to the block, forming time intervals, which forms the reference voltage. They are connected to the inputs of the comparison units, a mode switch, a reference frequency generator, a counter and a digital indicator 2. However, the specified meter can measure only one pair per measurement cycle The pulse pulse, since the time interval shaping unit forms only one time interval of choice with the help of a mode switch. This limits the functionality of the device in the analysis of rarely repetitive pulses, when all the information about the parameters of the pulse must be obtained in one measurement cycle, and leads to an increase in the time of signal investigation. The purpose of the invention is to expand the functionality when measuring single and rarely repetitive input signals. The goal is achieved by the fact that in a digital pulse time meter, containing the first and second comparison blocks, the first inputs of which are connected to the input row, the voltage driver, the first and second outputs of which are connected to the second inputs of the first and second comparison blocks , the reference frequency generator, three elements of the match are introduced, the chip of the NAND element and the inverter, with the output of the reference frequency generator connected to the first. the inputs of the matching elements, the output of the first comparison unit is connected to the first inputs of the first and second elements AND-NOT, the output of the second comparison unit through the inverter is connected to the first inputs of the third and fourth elements AND-NOT and to the second inputs of the first AND elements and the first match , the third input of the first NAND element is connected to the output of the second NAND element and the second input of the third NAND element, the output of which is connected to the second inputs of the second and fourth NAND elements, the third input of the second NAND element is connected to the first To the output of the first NAND element, the second inputs of the second and third coincidence elements are connected respectively to the second output of the first NAND element and to the output of the fourth NAND element. FIG. 1 shows a structural diagram of the proposed digital pulse time analyzer; figure 2 - timing charts of his work. The circuit contains comparison units 1 and 2, respectively, for low and high levels, a reference voltage generation unit 3, an inverter 4, AND-NOT elements 5-8, coincidence elements 9, 10 and 11, a reference frequency generator 12. The meter works as follows. In the absence of an input signal to the input of the comparison unit 1, a reference voltage is applied corresponding to a low signal level (, l 0,) / and the input of the comparison unit 2 is a reference voltage corresponding to a high input signal level (U2.-0/9 Um) At the outputs of blocks 1 and 2 of the comparison, there are low potentials (logic level O). From the output of the comparison unit 1, this potential enters the inputs of elements 7 and 8 AND-NOT and locks them. From the output of the comparison unit 2, the low potential turns out through the inverter 4 and the element 5 AND-NOT arrives at the input of the element 6 AND-NOT and blocks it. Thus, high potentials are present at the outputs of the block for forming time intervals, which block the elements. 9, 10 and 11 matches. When the voltage of the low-level reference voltage is exceeded and the output of the comparison unit 1 appears, a high potential (logic level, Fig. 2 a, b), which unlocks element 7 I-NB. At the output of the latter, a voltage drop from a high level to a low (fig. 2d) f is formed, which is the beginning of the formation of a time interval equal to the length of the leading edge of the signal (4oi) RI, the voltage of the input signal of the high level reference voltage (J / i , - on the output of the comparator unit 2, a high potential appears (logical level 1, fig. 2b), which is the beginning of the foholing of the time interval equal to the duration of the input signal at the level of the high reference voltage UQ (Fig. 26). THIS by The potential through the inverter 4 blocks element 7 I-NB / at the output of which a voltage drop from low to high is formed (Fig. 2d), which is the end of the formation of a time interval equal to the length of the leading edge of the pulse -fcij. the output of the comparator unit 2 through the inverter 4 prohibits the operation of element 6 NAND and does not unlock element 8 NAND, at the output of which a low potential appears. This potential is & element 5 AND-NOT prepares for operation element 6 AND-NOT. When the voltage of the input signal decreases to a value below. At the output of the comparison unit 2, a voltage differential from a high level to a low is formed (Fig. 2c), which is the end of the formation of a time interval equal to the pulse duration T (Fig. 26). Through the inverter 4, a signal is received from the output of the comparison unit 2, which unlocks the previously prepared element 6 AND-NOT. At the output of this element 4, the voltage drop from the high ri level is low, which is the beginning of the shaping of the time interval equal to the length of the falling front (Fig. 2f. When the input signal voltage decreases to a value less than and, at the output of the comparison unit 2 voltage drop from high level to H1 is gzky, which locks I-NB element 8. At the output of this element, a high potential appears, which through element 5 I-NB loses element 6. At the output of this element a voltage drop occurs out low about .urovn in HIGH

(Fig. 2 (), Which is the end of the formation of a time interval equal to the length of the trailing edge of the input signal.

From the outputs of the elements 6 and 7 AND-NOT and the inverter 4, the formed time intervals arrive at the elements 9,

0 10 and 11 matches and allow the passage of pulses from the generator 12 of the reference frequency. At the outputs of the elements of coincidence 9, 10, and 11, pulses appear, the number of which is proportional to the duration

5 anterior trailing edges of the pulse and a THz pulse duration.

The proposed invention has wider functionality as compared to limestone, since with a large range, it is possible to simultaneously measure rise time, fall time and duration (pulse during the time it takes one pulse to change the input signal, which;: - makes it possible to significantly reduce time spent in the study of single and re; f {about repeated impulses. The reduction in scrutiny of research occurs due to the lack of waiting time for the arrival of single and rarely repeated signals.

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Claims (1)

DIGITAL TIME METER OF THEIR PULSE PARAMETERS, containing the first and second comparison blocks, the first inputs of which are connected to the input bus, a voltage driver, the first and second outputs of which are connected to the second inputs of the first and second comparison blocks, respectively, a reference frequency generator, from moreover, in order to expand the functionality when measuring single and rarely repeated time intervals, there are three elements of coincidence, four elements of NAND and an inverter, and the output the reference frequency ator is connected to the first inputs of the matching elements, the output of the first comparison unit is connected to the first inputs of the first and second AND elements, the output of the second comparison unit through an inverter is connected to the first inputs of the third and fourth AND elements and to the second inputs of the first AND element -NOT and the first element of coincidence, the third ^λ ; the third input of the first AND-NOT element is connected to the output of the second AND-NOT element and the second input of the third AND-NOT element, the output of which is connected to the _ second'inputs of the second and fourth® AND elements NOT tre the second input of the second AND-NOT element is connected to the first output of the first AND-NOT element, the second inputs of the second and third coincidence elements are connected respectively to the second output of the first AND-NOT element and to the output of the fourth element