SU917336A1 - Multichannel voltage-to-number converter - Google Patents

Description

The invention relates to computing. It can be used in devices for precision switching and conversion of analog signals, as well as in systems for collecting and processing information. ⁵

Known multi-channel voltage-code converter containing a channel switcher, an analog-to-digital converter of parallel-serial type, two reference current stabilizers, an additional switch with a decoder and a block of matching amplifiers, registers of the lower and upper digits of the result C]. fifteen

The disadvantage of this device is the high hardware costs for controlling the input switch due to the presence of an additional key in each channel of the switch, additional units not used in typical structures of analog-to-digital converters (high and low order registers, additional switch with decoder, matching 'amplifiers).

In addition, to determine the malfunction of the switch channel, a repeated conversion cycle is performed, which reduces the efficiency of the control of the switch channels.

The closest in technical essence to the proposed one is a multichannel voltage-code converter containing a switch, a bit shift register, controlling a bit-balancing register, a comparator, a source of positive and negative polarity reference voltages, a code-voltage converter, the analog inputs of which are connected to sources of positive and negative polarity, bit inputs - with outputs of the register of bitwise balancing, and the output with the first input the comparator's interface, the second input of which is connected to the output of the switch, and the Output - with the input of the bitwise balancing register [2),

A disadvantage of the known device is the lack of operational monitoring of the operability of the switch channels, which leads to a decrease in the reliability of the conversion, i.e. There is no information about the health of the switch as a result of the conversion of the input voltage of the channel.

The purpose of the invention is to increase the reliability of the conversion by providing operational control of the switch channels,

This goal is achieved by the fact that 'into a multi-channel voltage-to-code converter containing a switch, a bit shift register, a bit balancing register, a comparator, a positive and negative polarization reference voltage source, a code-voltage converter, the analog inputs of which are connected to the outputs of positive voltage reference sources and negative polarity, bit inputs - with outputs of the register of bitwise balancing, output - with the first input of the comparator, the second input cerned connected to the output switch, and an output - to the input of the register successive balancing, two keys are introduced restrictive resistors at the inputs and fault recorder, and bitwise shift registers and equilibration contain two additional discharge outlets. additional bits of the bitwise balancing register are connected to the fault recorder, and the outputs of the additional bits of the bitwise shift register are connected to the corresponding inputs of the bitwise balancing register, to the inputs of the converter installation, the voltage code is in the unit and zero state and to the control inputs of the keys, the outputs of which are connected to the second input of the comparator, and the key inputs through the limiting resistors are connected to the outputs of the reference voltage sources, positive and negative Flax polarity.

The drawing schematically shows the device "

The device contains a switch 1, a bit shift register 2, a bit balancing register, a code-voltage converter (PCN) 4, a comparator 5, reference voltage sources of positive 6 and negative 7 polarity, keys 8 and 9, restrictive. resistors 1O and 11, malfunction recorder 12 ”At the same time, the bit shift register 2 and balancing register 3 contain two additional bits, respectively 13 and 14. The outputs of the additional bits 14 of the register 3 of the bitwise balancing are connected to the registrar 12 malfunction, Yu The outputs of the additional bits 13 of the register 2 of the bitwise shift are connected to the corresponding inputs of the additional bits 14 of the register 3 of the bitwise balancing, with the inputs of the installation PKN 4 in a single and zero state AND with the control inputs of the additional keys 8 and 9. The outputs of the keys 8 and 9 are connected to the second input of the comparator 5. The inputs of the keys 8 and 9 through the limiting resistors 10 and 11 are connected to the sources of this pubic voltages of positive 6 and negative 7 polarity.

IS

The device operates as follows.

1 switch voltage detector connects to the second input of the comparator 5. In the first conversion cycle 4 PKN signal output from the register 13 of the first additional discharge 2 bitwise shift is set in one state, ^and forming a voltage gts4n ^thrust fl * "'· θ ^{ΤΗΜ same} signal to the second input comparator 5 via the switch 8 and a resistor 10 connects the voltage + U _fl source 6 the reference voltage of a positive polarity 6 with proper channel 1 switch voltage + ^ 9, supplied through a resistor 10 and a key 8 _(summed with the input sensor voltage. If not switch channel connects the voltage sensor, the voltage is only +1) * is input to comparator 5. In the first conversion step, the comparator 5 also carries out a _PCB with an output torus, which is equal to the switch. ^{+ g} k) voltage comparison with switching voltage at a working channel

R. Y _OgR + g _KA where

- sensor voltage}

- internal resistance of the sensor;

- channel resistance switch in}

key resistance; resistance of the limiting resistor.

switchboard

In the absence of inclusion

When the switch canapon is good, <ϋ ' _v mv the first replenishing ** l Л bit 14 of register 3 of the bitwise balancing from the output of the comparator 5 in the first clock cycle, a zero signal (О) is recorded. In the case when the switch channel does not connect the sensor voltage (J ^,

> and η KN and the comparator 5 writes to the first additional bit 14 of register 3 of the bitwise balancing unit signal 1. · ²⁰

Thus, the presence of 1 in register 3 characterizes the presence of a malfunction of the switch channel.

To prevent ambiguity when voltage! sensor U ^,> (which, in the general case, characterizes a violation of the PIK operating conditions when the input voltages should not exceed the reference voltage U _iT ) a second additional conversion clock is introduced _{This is} compared with voltage. ³⁵

To do this, PKN 4 signal from the second additional discharge 13 of the register 2 bit shift is set to zero and generates a voltage. The same signal to the second input of the comparator 5 through the resistor 11 connects the voltage of the reference source 7 _eG , at.

this voltage - 'Jj _{T is} summed through the resistor 11 and the key 9 with a voltage ^<5 sensor ID. With a working channel com! mutator ΐυ ^ 'Ο ^ κΗ and a single signal (1) is recorded in the second additional bit 14 of register 3 of bitwise balancing. In the absence of ^. ^50, the channel is switched on U ' _t = -V _{? T,} ^{and in} 9 the second digit 14 of the register of bitwise balancing 3 records a zero signal (O).

Thus, when defective Ka Nala switch ⁵⁵ for additional 14 bits of register 3 formed of successive balancing code * 10, and is at a proper channel code 01 *. If, however, the voltage of the sensor is a> U _{et or} Id ^ -i ^, then with a working channel of the switch in additional bits 14 codes 11 or 00 are formed, which also differ from the fault code * 10 and characterize violations of the input voltage of the switch.

In subsequent cycles, PNA works in the usual way.

Claims (2)

(54) MULTI-CHANNEL VOLTAGE CONVERTER-CODE The invention relates to computing technology. It can be used in precision switching and analog signal conversion devices, as well as in data acquisition and processing systems. Known multichannel converter nag-fusion-code, rocer-holding channel switch, analog-to-digital converter of parallel-post-stage type, two reference current stabilizers, additional switch with decoder and block of matching amplifiers, registers of low and high bits of the result tH. The disadvantage of this device is the presence of large hardware costs to ensure control of the input switch due to the presence of an additional key in each channel of the switch, to full-lockable blocks not used in typical structures of analog-to-digital converters (upper and lower order registers, additional com, mutator with decoder, matching amplifiers). In addition, a conversion cycle is repeated to determine the failure of the switch channel, which reduces the efficiency of monitoring the switch channels. The closest in technical essence to the present invention is a multichannel voltage converter containing a switch, a bit shift register controlling a bit balance register, a comparator, a source of reference voltages of positive and negative polarity, a code-voltage converter whose analog inputs connected to the sources of the reference voltages of positive and negative polarity, the bit inputs are connected to the outputs of the bit counterbalancing register, and the output from the first The input of the comparator, the second input of which is connected to the switch output, and the output to the input of the register of equivalent balancing 2. The non-aagus device of the known device is a Vogue) | 1- operative congruence of the health of the commutator channels, which will reduce the aurover conversions, i.e. There is no information about the health of the switch as a result of converting the input to the channel scale. The purpose of the invention is to increase the reliability of the formation due to the provision of operational control of the channels of the commutators (. The specified del is achieved by the fact that the multichannel converter has a voltage of soda, a social switchboard, a bit shifter of bitwise distribution, a register of bitwise restraint, comparator, The reference point of the reference voltages of positive and negative polarity, the transducer to the april, the analog inputs of which are connected to the outputs of the sources of the reference voltages of positive and negative polarity and, the bit inputs - with the outputs of the bitwise balance register, the output - with the first input of the comparator, the second input of the cottage is connected to the output of the switch, and the output - with the input of the register ps azr dny equilibration, two Keys with limiting resistors on the inputs and a recorder are entered malfunctions, with the bit shift and balance registers each containing two additional bits, the outputs, the additional bits of the bit memory register are connected to the fault recorder, and the outputs The bits of the bit shift register are connected to the corresponding inputs of the bit balance register, to the transducer installation inputs, the code to the single and zero states and to the control inputs of the keys, the outputs of which are connected to the second input of the comparator, and the key inputs through the limiting resistors connected to the outputs of the sources of the reference voltage, positive and negative polarity. The drawing schematically shows the device. The device contains a switch I, a bit shift register 2, a bit balance register 3, a code-voltage converter (PCN) 4, a comparator 5, sources of reference voltages positive 6 and negative 7 gaelo, keys 8 and 9, restrictive, resist W II, recorder 12 faults. At the same time, the regrings of the n phase shift 2 and ZfavSveshvescheniya 3 contain by it additional discharges, respectively, 13 and 14. The outputs are additional: 14 registers of 3 equal balances connected to the fault recorder 12. The outputs of the additional bits 13 of the register 2 of the bit shift are connected to the corresponding inputs of the additional bits 14 of the register 3 of the bit balance, with the inputs of the PCN 4 installation in the single and zero state AND with the control inputs of the additional keys 8 and 9. The outputs of the keys 8 and 9 are connected to the second input of the comparator 5, the inputs of the keys 8 and 9 through the limiting resistors 10 and 11 are connected to the sources of the reference voltages of positive 6 and negative 7 polarities. The device works as follows. Switch I connects the sensor voltage to the second input of the comparator 5. In the first step of converting PKN 4 with a signal from the output of the first additional bit 13 of register 2 of the bit shift, it is set to one state, forming a voltage (With the same signal to the second I / O of the comparator 5 through the key 8 and the resistor 10 is connected to the source 6 of the reference voltage of the positive voltage polarity 6. When the switch I channel is intact, the voltage + supplied through the resistor 10 and the key 8 is summed with the input voltage If the switch channel does not connect the sensor voltage, only voltage U is fed to the input of comparator 5. Comparator 5 in the first conversion cycle compares voltage with output voltage of switch Oj (,, which is equal to the correct switch Canada). A where U, - sensor voltage; - internal sensor resistance; - switch channel resistance HN key resistance; R resistance of the limiting resistor. In the absence of switching on the switch, when the switch channel is in good condition .. and in the first additional bit 14 of register 3 of bit rate from the output of comparator 5, a zero signal (O) is recorded in the first clock cycle. In the case when the switch channel does not connect the sensor voltage Od and the comparator 5 writes a single signal to the first additional bit 14 of the register 3 of the bit counterbalancing. Thus, the presence of I in register 3 indicates the presence of a malfunction of the switch channel. To prevent ambiguity when the sensor voltage is and. and .. (which, in general, characterizes the violation of the working conditions of the NCP, when the input voltages should not exceed the reference voltage UJT.) the second additional conversion cycle is introduced. In this cycle, the voltage of the sensor and coming through the switch channel is summed with the source voltage Uj and compared to the voltage. For this VCP, the signal from the second additional bit 13 of the bit-shifted register 2 is set to zero and forms the voltage Wfit The same signal to the second input of the comparator 5, through the resistor 11, connects the voltage of the reference source T-Ug, at. This voltage - Uj is summed up through a resistor 11 and a switch 9 with a voltage sensor U. With a healthy switch channel and the second additional bit 14 of the 3 pphasal load balance register, a single signal () is recorded. Without. switching on the channel () pc. "second bit 14 of the bit balance register 3" is recorded zero signal (O). Thus, in the case of a faulty switch channel, in additional bits 14 of register 3 of bitwise equalization, the code 1O is formed, and if the channel is intact, the cots O. If, however, the dat ux U j is applied. then, when the switch channel is in good order, in additional bits 14, codes 11 or OO are formed, which also differ from DTC 10 and characterize disturbances in the values of the input voltages of the switch, In subsequent cycles, the NCP operates in the usual way. Claims of Invention A multi-channel voltage-to-code converter comprising a switch, a bit shift register, a bit balance register, a comparator, sources of reference voltages of positive and negative polarity, a code-voltage converter, the analog inputs of which are connected to. the outputs of the sources of reference voltages of positive and negative polarity, the bit inputs are with the outputs of the bit balancing register, and the output is c. the first input of the comparator, the second input of which is connected to the output of the switch, and the output to the input of the register of the equilibrium balance, which also means that, with the aim of increasing the reliability of the conversion by switch channels, it introduced two keys with limiting resistors on; inputs and fault recorder, while the bit shift and balance registers each contain two additional bits, the outputs of the additional bits of the balance register are connected to the fault recorder, and the outputs of the additional bits of the bit shift register are connected to the corresponding bits of the bit balance register , to the inputs of the converter installation, the voltage to the single and zero state and to the control inputs of the keys, the outputs of which are connected to the second in ode comparator, and inputs the key through limiting resistors connected to the outputs of sources of reference voltages of positive and negative polarities. Sources of information taken into account in the examination 1, USSR Author's Certificate N 413615, cl. NOZ K 13/17, 01.30.74. 2. Gitis, E. I. Information Converters for ECVU, 1975, p. 298, fig. 7.7 (prototype). , t five f ezucmp, equals another € and Register piraraydn, shift