SU1270774A2 - Device for separating residue with respect to variable modulus - Google Patents

Abstract

The invention relates to the field of computing and can be used in control computers and instrumentation. The aim of the invention is to increase the testability of the device. The goal is achieved by the fact that the device controls the operation of all the main nodes and by analyzing the state of the group of device malfunctions the failed node is determined. The operation of the number decoder and module is controlled by means of threshold elements determining the presence of a signal more than on one output of the decoder, or the absence of signals on all its outputs. The code at the output of the encoder is subjected to the inverse transformation using a control decoder and compared with the code received at its input. When uncomplicated, a signal of t e-response is generated. The operation of the device is monitored by parallel formation of a residue equal to one. If at this time the code is different from one at the information outputs of the device, then a malfunction signal is generated. The correctness of the recording is monitored (LS of information on the input register of the module by comparing information on the input and output of the register. The presence of identical signals on the forward and inverse outputs of each register bit is also monitored. Inventory to auth. 928359. 2 Il.

Description

The invention relates to computing and can be used in control computers and instrumentation.

The aim of the invention is to improve the testability of the device.

Figure 1 shows the functional diagram of the proposed device for

selection of the remainder in the variable mode-Yu torus.

Liu figure 2 is a functional diagram of the THRESHOLD element.

A device for allocating a residual in a variable module contains the first group of 1 device inputs, input register 2 numbers, decoder 3 numbers, switch 4, second group 5 device inputs, module input register 6, module decoder 7, encoder 8, device output group 9, threshold elements 10 and 11, the first element AND 12, the group 13 of the decoders, the element OR 14, the comparison node 15, the group 16 of device fault outputs, the first group of elements NOT 17 the residual decoder 18, the element NOT 19, the second element AND 20, the second group of elements NOT 21, first group elements And 22, a group of elements OR 23, a group of 24 modulo-two adders, an AND-NOT element 25, a third group of elements NOT 26, a second group of elements AND 27.

The threshold element (figure 2) contains the element And 28, the group of elements And 29, the element OR 30 and the group of elements is NOT 31.

The device for isolating the remainder in a variable module operates as follows.

The monitored number and code of the monitoring module are written respectively to registers 2 and 6 of the number and module. Decoders 3 and the numbers and the module convert the contents of the input registers 2 and 6. Switch 4, the inputs of which are connected to the outputs of the decoders 3 and 7 of the number and module, and the encoder 8 form the remainder of the controlled number for a given module on the group 9 of the device outputs.

The device monitors the operation of the decoder 3 numbers and the decoder 7 module, controls the encoder 8, controls the write to the input register 6 of the module and controls the operation of the entire device when forming a balance equal to one.

With the help of threshold elements 10 and 11, the operation of the decoder of the 3 numbers and the decoder of the 7 modules is controlled. The fault signal at the output of the threshold elements 10 and 11 is generated in the absence of signals at the output of the monitored decoder or in the presence of a signal on more than one output of the monitored descriptor. The decoder 8 is controlled by the residual decoder 18 and the comparison node 15. The residual decoder 18 converts the output5 of the signals of the encoder 8 so that the signals at the output of the remainder 18 decoder must be equal to the signals at the input of the encoder 8 (decoder 1B performs the conversion

the opposite of that produced by the encoder 8). When the signals at the output of the residual decoder 18 and at the input of the encoder 8 are unequal, the comparison node 15 generates a fault signal.

The control of the correct operation of the device in the formation of a residue equal to one is carried out using a group of 13 decoders, the element OR 14, the elements AND 12 and 20, the group of elements. NOT 17 and the element NOT 19. With the help of group 13 decoders, controlled numbers having a remainder equal to one are extracted.

5 for each modulus value. The corresponding outputs of the decoders of group 13 are combined with the element OR 14. The element of group 17 is NOT and the first element AND 12 allocates a single code at the output

0 encoder 8. In the case when the output of the element And 14 there is a single signal, and the output of the encoder 8 code is different from the unit, the second element And 20 generates a signal

5 faults.

The control of writing to the input register 6 of the module is carried out as follows.

When writing information (mod0l code) to the input register 6 of the module, there is a single signal (synchronization signal) at its recording input. If the write to register 6 in any way is done correctly,

Claims (1)

5 then at the inputs of the corresponding adder group 24 modulo two there will be different signals. When writing a single signal to the first 31 inputs of the corresponding adder of the group 24 for the motor, the hive two will receive a single signal from the output of the corresponding element of the OR group 23, and the second input of the adder of group 24 modulo two will receive the zero code from the inverse output of the corresponding bit of the input register 6 modules When writing a zero signal to the first input of the corresponding adder of group 24 modulo two, there will be a zero signal, and a single signal at the second input. In both cases, a single signal will be generated at the output of the corresponding adder of group 24 modulo two. In the case when the record for all the bits of the input register 6 module is made correctly, the output of the element AND-25 will be a zero signal. If the recording is incorrect, then a zero signal is generated at the output of the corresponding adder of module 24 modulo two, and a fault signal is generated at the output of the NE-25 element. A fault is also checked that the input register 6 of the module is healthy, after writing the module code to it (this time on all inputs of the second group of the device 5, there are zero signals). At the same time on the direct and inverse outputs of any bit of the input register 6 of the module of zero or single signals, the corresponding adder of group 24 modulo two will form a zero signal and at the output of the IS-NE 25 element a fault signal will appear. An analysis of the status of the fault outputs of device group 16 allows the location of the fault in the device to be clarified. Claims of the invention A device for allocating a residue with a variable module according to the author. St. No. 928359, characterized in that, for the purpose of a test target of a device, two threshold elements, two AND elements, an OR element, a NOT element, an AND-NOT element, a comparison node, a residual decoder, a group of adders modulo two, a group are entered into it. decoders, a group of OR elements, two groups of AND7 elements and three groups of NOT elements, the outputs of the number decoder and module decoder are connected respectively to the inputs of the first and second threshold elements, the information inputs of the group decoders are combined with information inputs The input register numbers, gating inputs of the group decoders are connected to the corresponding outputs of the module decoder, the outputs of the decoder are connected to the information inputs of the residue decoder, the first and second groups of information inputs of the comparison node are connected respectively to the output groups of the switch and the decoder of the remainder, the decoder outputs, except , through the corresponding elements of the NOT of the first group are connected to the corresponding inputs of the first element AND, the output of the low-order encoder is connected the corresponding input of the first element AND whose output is NOT connected to the first input of the second element AND whose second input is connected to the output of the OR element, the inputs of the NOT elements of the second group are combined with the corresponding information inputs of the input register of the module, the outputs of each element are NOT the second and third groups connected respectively to the first and second inputs of the corresponding element AND of the first group, the output of which is connected to the first input of the corresponding element OR of the group, the output of which is connected to the first input of the corresponding modulo adder is two groups, the outputs of all modulo adders are two groups connected to the corresponding inputs of the NAND element, the direct output of each bit of the input register is connected to the third input of the corresponding AND element of the first group and the first input of the corresponding And second element the group, the output of which is connected to the second input of the corresponding element OR of the group, the inverse you: o of each bit of the input register of the module is connected to the second input of the corresponding adder by m modulo two groups, the second input of each AND gate of the second group is combined with the third input of the respective OR gate groups and the corresponding input of the NOR second group, the third inputs of the second AND element