SU855925A1 - Discrete phase-shifting device - Google Patents

Description

(54) DISCRETE. BACKGROUND DEVICE

one

The invention relates to power converter technology and can be used in control systems for AC converter-operated converter units using discrete information processing techniques.

The discrete phase shift of its device is known, which contains a null-organ, a clock generator, a clock counter, a converter, a control signal - a code. The command of the null organ fills the counter with pulses from the clock, the code recorded in the counter with the code compares the control signal to the converter, and when the codes match, the output pulse of the phase shift 1 is generated at the output of the coincidence circuit.

The disadvantage of this device is the complexity, since for each channel of the control system a multi-digit digital code matching circuit is required.

The closest in technical essence to the present invention is a discrete phase-shifting device for controlling a valve converter containing a null-organ connected to the control trigger input, a clock pulse generator, a code recording resolution block, a code addition resolution block, one input of which is connected to the trigger single output control, and the output is to the counting input of the clock counter 2.

The disadvantage of this device is the complexity, since it is necessary to additionally dial the coincidence circuit code and rewrite the phase shift code from the memory counter to the read counter, as well as enter a delay unit to avoid the command to write the code to the read counter and transient in the memory counter.

The purpose of the invention is to simplify a discrete phase shifter.

20 The goal is achieved by the fact that

Claims (1)

the device is equipped with a frequency divider, a reset unit, a control signal converter in the time interval, the zero-organ is connected to the synchronization input of the control signal converter in the time interval, the clock generator is connected to the input of the code recording resolution block and the frequency divider input, the output of which is connected to ; j: pygim input of the resolution block up to;: 1ol) enn code, the output of the control signal converter in the time interval is connected to another input of the code recording resolution circuit, the output of which ene with a counting input of the clock counter, the output of which is connected to the zero input of the control latch, a single outlet through which the reset unit is connected to the reset input of the clock counter. FIG. 1 shows a functional diagram of the device; in fig. 2 - time diagrams of work. The device contains a null-organ, 2 clock pulse generator, code writing resolution block 3, code addition resolution block 4, control trigger 5, clock pulse counter 6, time signal control converter 7, frequency divider 8, reset block 9 is connected to the output of three gage 5, and the output is connected to the reset input of the counter 6. The input of the null organ 1 is connected with the corresponding phase of the mains supply (voltage U i). The control signal is fed to the input of the converter 7, and the output of the device is the output of the counter 6. After the code defining the value of the phase shift is written to the counter 6, the zero-body 1 when the corresponding voltage is reached and its supply voltage produces a zero pulse Ui 7 to the initial position (voltage Uj), in addition, the pulse of the nullorgan 1, arriving at the single input of the control trigger 5, sets a high potential at its output, thereby allowing the supply of pulses U e from the frequency divider 8 to the counting input of the counter 6, through the circuit 4 permit code addition. When the counter 6 is filled, a command signal is issued and 7 to turn on the corresponding valve. At the same time, this signal, arriving at the zero input of control trigger 5, prohibits the passage of pulses from frequency divider 4 to the input of counter 6. In addition, the low potential from the single output of trigger 5 is fed to the input of the reset pulse shaping unit 9, which generates a pulse arriving at the reset input counter b and set it to its original state. Converter 7 analog control signal - time interval 7 converts the control signal Uy into a sequence of square pulses Ui | synchronized with the mains and whose width is proportional to the control signal. At the same time, the output impulse of the converter 7 goes to the input of the block for writing the code and allows the passage of the pulses Us of the generator 2 to the counting input of the counter 6 for a time that is proportional to the control signal. The number of pulses recorded by the counter (code) is a discrete equivalent of the control signal U- and determines the magnitude of the switching angle of the valves pt. With the arrival of the next synchronization pulse, the cycle repeats. The frequency of the pulses of the frequency divider is selected from the condition of filling the counter during the time corresponding to the maximum angle of twisting. The time of conversion of the control signal into a code depends on the speed and the number of bits of the counter and is 25-100 microseconds for an 8-10-bit counter, i.e., the maximum range of switching angle does not affect practically. The use of one counter eliminates the need for an additional census of the phase shift code from the memory counter to the clock counter and compares the code recorded by it with the code dialed by the comparison circuit, i.e., it allows to simplify the circuitry of the device. The error in counting the switching angle, related to the discreteness of the meter operation, depends on the meter capacity and can be set small. When building a multichannel control system of a valve converter, the M pulse-clock generator and the control pulse converter — code — time interval are common to all channels that the control system lacks. DETAILED DESCRIPTION A disc) phase-shifting device for controlling a valve converter containing a zero-body is connected; 1Y to the control trigger input, a clock generator, a code recording resolution unit, a code addition permission block, one input of which is connected to a single control trigger output, and The output is connected to a counter input of a clock counter, characterized in that, for the sake of simplicity, it is provided with a frequency divide, a block of reset, and a control signal to time converter. erval, wherein the zero-body connected to the input transducer synchronization control signal during the time interval clock pulse generator is connected to the input of block code zanisi tim gap and to the input of the frequency divider, whose output is connected to another input of the padding code authorization unit, an output transducer signa