SU1651217A1 - Device for recording monopulse signal instantaneous valves - Google Patents

Abstract

The invention relates to electrical measuring equipment and can be used in the development of analyzers of single pulses of complex shape. The purpose of the invention is to increase the information content due to uneven sampling, reducing the sampling interval and increasing the number of independent input signals. To do this, a device containing n channels, each of which contains a source 1 of the reference Voltage, a comparison device 2, a block 3 of memory, a driver of 4 pulses, an address counter 5, a counter of 6 cycles, a generator 7 of reference pulses, a block 8 of control and t-1 comparison devices with the respective connections. The introduction of new elements has made it possible to significantly increase the information content of signal registration, both by increasing the bandwidth and by increasing the amount of data being recorded. 1 il. s s c /)

Description

The invention relates to electrical measuring equipment and can be used in the development of a single pulse analyzer of complex form.

The purpose of the invention is to increase the in-rate by introducing the possibility of recording instantaneous values at any part of the pulse signal, reducing the sampling interval, increasing the time during which the input signal can be recorded, and increasing the number of independent input signals.

The drawing shows a block diagram of the device.

The device for recording instantaneous values of monopulse signals contains a generator of reference pulses 1, the output of which is connected to the first input of each of the m channels 2, the control unit 3 'whose outputs are connected to the inputs of the Initial setting and the Resolution of each of the m channels 7, each Channel 2 contains a block 4 specifying the mode of operation, n comparing blocks 5, the first element OR 6, a register 7, a memory block 8, a reversible counter 9, a digit

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ro-analogue converter 10, second element OR 11, element AND 12 shaper 13 pulses 9 counter 14 cycles, address counter 1 5} with each channel 2 having the first inputs of comparing blocks 5 having the same sequence number in each of the channels are combined and connected to one of the device inputs having the same sequence number, the second inputs of the matching blocks 5 of each channel are combined and connected to the digital-to-analogue output of the tel 10 of this channel, the output of the reference pulses repeater re inputs Cross-connect counters 9 of all channels 2, output Resolution of control unit 4 is connected to the resolution inputs of reversible counters 9 of all channels and the first inputs of elements AND 12 of all channels- {output f) Initial setting of control block 4 is connected to resolution enable inputs of reversible counters - H of all channels and reset inputs of the address counters of 15 all channels, in addition, the outputs of the operation mode set unit 4 are connected to the preset code inputs of the reversing counter 9, the count mode output of the mode set operation unit 4 is connected to the input ode of the counting mode of the reversible counter 9, and the outputs of the reversible counter 9 with the inputs of the digital-to-analog converter 10 and the second group of information inputs of the memory block 8, the outputs of the comparison blocks 5 are connected to the corresponding inputs of the OR element 6 and the corresponding information inputs of the register 7, the output of the first element OR 6 connected to the input of the record of register 7 and the first input of the element OR 11; the output of the register 7 is connected to the first group of informational inputs of the memory block 8; the output of the overflow of the reversible counter 9 connects En with the clock input of the counter 14 cycles, the output of the imaging unit 13 pulses is connected to the zero register input 7, the clock input of the address counter 15, the zero input of the counter 34 cycles and the recording input of the memory block 8, the outputs of the counter 14 cycles combined with the third group information inputs of the block 8 p-amti, the counter overflow output of 14 cycles is connected to the second input of the element OR 11, and the outputs ad

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national counter 15 - with address inputs of memory block 8, output overflow of address counter 15 - with a second input of an AND 12 element, the output of which is combined with the enable input of the pulse former 33, the output of the OR element 11 is connected to the trigger input of the former of 13 pulse,

The device works as follows.

Before the operation of the device, the initialization of the channels 2 sweep and registration is carried out. During this stage, the installation of the reference voltage generated by the channel in the initial state occurs. Initialization is performed as follows. At the outputs of the preset code of the mode setting unit 4, code8 is set corresponding to the reference voltage value at zero time, the code is determined by the type of the Formed reference voltage L (increasing or decreasing) and the channel number. This code is fed to the inputs of the preset reversible counter 9, at the output of the% direction. The accounts of block 4 of the mode setting are set to logical O or 1, in dependence on the generated reference voltage (decreasing or increasing). These logical clocks 1 are permanently located at the input of the counting mode of the reversible counter 9 in view of the entire operation of the device. The same logical signal is fed to the zero-address input of the address counter 5. At this, the initialization stage ends,

Ethane measurement and recording begins after the installation of a logical signal. Permission at the output of control unit 3. In this case, reversible counters 9 are simultaneously launched in all channels of the device. Simultaneous formation of a grid of reference voltages by all channels begins.

From the inputs of the reversible counter 9, the codes are fed to the inputs of the h analogue of the converter 10, the output of which produces a variable exemplary voltage, which is fed to the second inputs of the matching blocks 5-i. Input signals are fed to the first inputs of the matching blocks. With the coincidence of the instantaneous values of the model stress, h

neither the output of the digital-to-analog converter O and any input signal at the output of the corresponding comparing unit b-i forms a pulse. This pulse arrives at one of the inputs of the element OR o, as well as at the i-th input of the register 7f and with

its outputs to the first group of inlayable inputs of the memory unit 8 is supplied with a positional unit code. In the second group of information inputs of the memory block 8, a code of the coordinates of the fixed instantaneous value of the input signal is formed.

The peculiarity of measuring the time coordinate for a recorded instantaneous value is that the time segments (increments) from the previously recorded instantaneous value are recorded, and not the absolute value of time.

Code writing to memory block 8 occurs in two cases: when the instantaneous values of the reference voltage and the input signal coincide, and if there is no coincidence of the instantaneous values, but when overflow occurs in the counter of 1A cycles. When zappsk in the first case, the pulse at the output of any comparing device 5-h h, the cut element OR 6 is fed to the first input of the element OR II, then to the input of the generator of 13 pulses, the output of which generates a write pulse in memory block 8 , On the falling edge of the write pulse, the counter of 14 cycles is reset, which counts the reference voltage sweep cycles, and also registers 7, which stores the code of the channel number in which the instantaneous values coincide.

Thus, the codes from the outputs of the reversible counter 9 carry information both on the instantaneous value and on the length of time from the start of the deployment of the reference voltage until the registration of the code for this value

The end of the measurement and recording phase is carried out by installing the logical control unit 3 on the bus. Resolution. This will stop the counting in the reversible counter 9 and, therefore, the deployment of the reference voltage from 176 will stop.

In other words, the cyclic analogue pre-call 10 and the write to the memory block 8. LSU is the first option to stop the measurement and registration phase - the overflow of the ack counter J5. This happens after the entire block of memory 8 has been filled. In this case, the output of the overflow of the address counter 15 sets a logical O, which is fed to the second input of the element 12, from the output of which the logical O is fed to the input of the resolution of the driver 13 pulses, which leads

to prohibit writing to the memory block 8 and the counting of the address counter 15.

Ula Invention Form

A device for recording instantaneous values of monopulse signals, containing m channels, each of which contains a source of reference voltage, comparing the unit,

the inputs of which are connected to the input of the device and the output of the source of the reference voltage, respectively, as well as the memory block, the pulse shaper, the address counter and the counter

cycles, a generator of reference pulses and a two-element OR, distinguished by the fact that, in order to increase the information content, the control unit, m-I counters, are entered into it

cycles, m-I address counters, t-1 memory blocks, t-1 pulse shapers, 2 t-1 OR elements, and the source of reference voltage in each channel is made as a sequence

connected to the unit setting the operation mode, the reversible counter and the digital-analog converter, the output of the reference pulse generator is connected to the clock

the input of the reversible counters of all channels, in addition, in each channel, n-1 comparison blocks, a register, two OR elements, the AND element are added, the first

the inputs of the comparing blocks having the same sequence number in each of the channels are combined and connected to the corresponding input of the device, the second inputs of the comparing blocks of each channel are combined and connected to the output of the D / A converter of this channel, the output Resolution of the control unit is connected to the inputs resolution of the reversible counters of all channels and the first inputs of the elements AND of all channels, output Initial installation of the control glare - with the inputs of the resolution of recording the code of the reversible counters of all channels and the zeroing inputs of the address counters of all channels, in each channel, the outputs of the preset code of the operation mode setting block are connected to the inputs of the preset code of the reversible counter, the output of the counting mode of the operation mode setting block is with the output of counting mode; reverse counter, outputs of the reverse counter - with the second group of information inputs of the channel memory block, outputs of the matching blocks

each channel is connected with corresponding1

using the inputs of the first OR element and the corresponding information inputs of the register, the output of the first OR element is connected to the register write spacing input and the first input of the second OR element, the register outputs are connected to the first group of information inputs of the memory block,

. the overflow output of the reversible counter is connected to the clock input of the cycle counter, the output of the pulse shaper is connected to the register zero reset input, the clock input of the address

the counter, the loop counter zeroing input and the memory block write input, the cycle counter outputs are connected to the third group of information inputs of the memory block, and the loop counter reloading output is connected to the second input of the second OR element, the outputs of the address counter are connected to the address inputs of the memory block and the output of the address counter overflow is from

0 by the second input of the element AND, the output of which is connected to the input of the resolution of the pulse driver, the output of the second element OR -. with the trigger input of the pulse generator.

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Claims (1)

M o rmula and sampling A device for recording instantaneous values of monopulse signals, containing m channels, each of which contains a reference voltage source, a comparison unit, the inputs of which are connected to the input of the device and the output of the reference voltage source, respectively, as well as a memory block, Pulse generator, address counter and cycle counter, reference pulse generator: and two · OR elements, distinguishing with. I mean that, in order to increase information content, a control unit, w-1 cycle counters, ml address counters, t-1 memory blocks, sh-1 pulse shapers, 2m-1 OR elements, and a voltage reference source in each the channel is made in the form of series-connected operation mode setting unit, a reverse counter and a digital-to-analog converter, and the output of the reference pulse generator is connected to the clock input of the reverse counters of all channels, in addition, p-1 comparison blocks are additionally introduced into each channel c, a register, two OR elements, an AND element, the first · inputs of the comparison blocks having the same serial number in each channel being combined and connected to the corresponding device input, the second inputs of the comparison blocks of each channel combined and connected to the output, digital-to-analog converter of this channel, the output Resolution of the control unit is connected to the inputs of the reverse of the counters of all channels and the first inputs of the elements AND of all channels, output Initial installation of the control unit - with inputs enabled To write the code of the reversible counters of all channels and the zeroing inputs of the address counters of all channels, in each channel the outputs of the preset code of the operating mode setting unit are connected to the inputs of the preset code of the reversing counter, the output of the account mode block of the operating mode setting unit is with the output of the account mode; a reverse counter, the outputs of a reverse counter are the second group of information inputs of the channel memory block, the outputs of the comparison blocks of each channel are connected to the corresponding inputs of the first OR element and the corresponding information inputs of the register, the output of the first OR element is connected to the input of the register register and the first vhs · ds-m of the second element OR. the outputs of the register are connected to the first group of the input inputs of the memory block, the overflow output is a reversible counter of the cell. by the clock input of the cycle counter, the output of the pulse shaper is connected to the input of the register reset, the clock input of the address counter, the input of the cycle counter zeroing and the memory block recording input, the outputs of the color counter are connected to the third group of information inputs of the memory card, and the overflow output of the cycle counter - with the second input of the second OR element, the outputs of the address counter are connected to the address inputs of the memory block, and the overflow output of the address counter is connected to the second input at the bottom?: ents I, whose output is connected to the user: permission the formation of the pulse shaper, the output of the second element OR -.with the input to the start of the pulse shaper.