SU851492A1 - Buffer storage device - Google Patents

Description

(54) BUFFER STORAGE DEVICE

This invention relates to memory devices.

A buffer memory device is known which contains a priority block, a write decoder, a read decoder, an information block, write enable blocks, a time delay block, a block of drives, a read enable block 1.

However, in the event of an information block or priority block failure, the device does not return to the initial state, and a false signal about the accumulator accumulation, i.e. The device has insufficient noise immunity.

Closest to the proposed is a buffer memory, a device containing a block of adders modulo two, the inputs of which are connected to the outputs of the write address sensor, and the outputs to one of the inputs of the accumulator occupant forming unit, the other inputs of which are connected to the outputs of the readout address sensor. In this case, the write and read address sensors can be performed as

counters or registers with linear feedback 2.

However, the device has insufficient noise immunity and reliability, since when the write and read address sensors fail, the device does not return to its original state, and a false signal about filling the drive may be generated.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that

10 into a buffer memory containing a drive, a control unit, a write address counter and a read address counter, with one of the drive inputs connected to the outputs of the write and read address counters, and the other input and output are the input and output of the device, respectively; and a synchronization unit, with one input of the comparison circuit connected to the output of the write address counter, the other input

Claims (2)

20 to the output of the read address counter, and the output is connected to the first input of the control unit and the first input of the synchronization unit, the second input of which is connected to the output of the control unit, the third input is connected to the device input, the first output of the synchronization unit is connected to the second input of the control unit, and the second and the third outputs are connected to the write and read address counters. FIG. 1 shows a buffer memory device, a functional diagram; in fig. 2 - synchronization unit; in fig. 3 - time diagrams. The device contains a drive 1, read address and 2 and write address counters 3, control block 4, comparison circuit 5 and synchronization block 6. The inputs 7 and 8 of the comparison circuit 5 are connected to the outputs of the counters 2 and 3. The output 9 of the comparison circuit 5 is connected to the first inputs of the control unit 4 and the synchronization unit 6. The second input 10 of the synchronization unit 6 is connected to the output of the control unit 4, and the third input is connected to the input of the device. The first output of the synchronization unit 6 is connected to the second input of the control unit 4, and the second and third outputs are connected to the inputs of counters 3 and 2. The synchronization unit 6 contains delay elements 11 and 12, elements AND-NO 13-18, element 2I-OR-NOT 19, triggers 20-22, a single pulse generator 23, a capacitor 24 and a diode 25. The device operates as follows. After switching on the device, counters 3 and 2 are set to an arbitrary state. If no information arrives at the device input, counter 3 does not change its state. In case of inequality, the counter codes 3 and 2 from the control unit 4 through the synchronization unit 6 to the counter 2 receive pulses. Counter 2 begins to sequentially change its state until the codes of both counters are matched, and the comparison circuit 5 produces a sign of equality (Fig. 3 Sv) after the arrival of a read pulse (Fig. 3 b). The sign of equality of codes from the output of the comparison circuit 5 goes to the control unit 4 and stops the flow of pulses to the counter 2. Thus, the device is ready for operation. When information arrives at the device input, the sync pulses of the input information (Fig. 3 a) through the synchronization unit 6 are fed to the input of the counter 3, sequentially increasing its content by one. The codes of counters 3 and 2 will become unequal, and from the control unit 4 to the counter 2, information read pulses will begin to arrive at the counter 2 through the synchronization block b (Fig. 3 b). The reading continues until the counter code 2 becomes equal to the counter code 3. There may be cases when the amount of information received at the input of the device. exceeds the volume of accumulator 1 and the code of counter 3 becomes equal to the code of counter 2, and the equality sign (Fig. 3c) is generated by the comparison circuit 5 after the arrival of the recording pulse (Fig. 3a). In this case, the recording of information into the accumulator 1 is stopped, as the control unit 4 blocks the pulses received at the input of the counter 3 through the synchronization unit b, and a signal (Fig. 3 g) of the accumulator 1 is generated, which is indicated or transmitted to the subscriber. After reading at least one word from accumulator 1, the counter codes 2 and 3 will become unequal and the device will be prepared for writing. When counters 3 and 2 fail, counter code 2 tends to become equal to counter code 3 and the device returns to its original state on its own. No additional signals setting the device to its original state are required. The synchronization unit 6 prevents the supply of shortened pulses to the counters 3 and 2, which occur when the input information and the read pulses generated by the control unit 4 are fully or partially coincident. The use of the proposed device allows reducing information losses in faulty situations. Since the device returns to its initial state on its own, the time taken by the operator to maintain it is significantly reduced. Claims A buffer storage device comprising a drive, a control unit, a write address counter and a read address counter, one of the drive inputs connected to the outputs of the write and read address counters, and the other input and output are respectively input and output of the device, that, in order to increase the reliability of the device, it contains a comparison circuit and a synchronization unit, with one input of the comparison circuit connected to the output of the write address counter, the other input to the output of the counter a readout addresses, and the output is connected to the first input of the control unit and the first input of the synchronization unit, the second input of which is connected to the output of the control unit, the third input is connected to the device input, the first output of the synchronization unit is connected to the second input of the control unit, and the second and third outputs are connected with write and read address counters. Sources of information taken into account during the examination 1. USSR author's certificate No. 551695, cl. G 11 C 11/00, 1975. 2. USSR author's certificate number 553679, cl. G 11 C 11/00, 1976 (prototype). (rig. 1 gsh P pn P IT lp iv L (rig. 3