SU553679A1 - Buffer storage device - Google Patents

Description

(54) BUFFER STORAGE

UZ, U4 - output of the block signals adders.

The device contains (see Fig. 1) a drive I, sensors of the address of the link 2 and records W. in the form of shift registers with linear feedback (not shown in Fig. 1, see Fig. 2), the control unit 4, block of adders modulo two 5 and block 6 of formation of a sigal of occupancy of the accumulator. The inputs of block 5 are connected to the sensor outputs of the address 3, and its outputs are connected to one input of block 6, the other inputs of which are connected to the outputs of the sensor 2, and sensors 2 and 3 contain shift registers 7 and an adder 8 modulo two.

The wiring diagram in the block of adders 5 (see FIG. 3), which provides the necessary shift of addresses, is determined by a square matrix, the rows of which are a sequence of a shift-shift register, the first row of the matrix being a register corresponding to the offset value (in the example under consideration, the offset value is chosen to be 3) from the initial state of the register, which has the form: 0001

The columns of this matrix (in the address code table this matrix is squared) determine the wiring diagram of the output circuits of block 5 with its input circuits through adders 9 (see Fig. 3) according to

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It is easy to see that the one shown in FIG. 3, the block of block 5 adders provides an offset of three cycles ahead of the code at its input. With this construction of the device, block 6 generates a signal of an anost of accumulator 1 when, at its inputs, the signals from the output of sensor 2 match the addresses of the link and the code from sensor 3 of the write addresses shifted three times ahead of the input, which corresponds to the presence in the plug 1 two free to write information addresses.

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The device works as follows.

Information is stored in the drive 1 at the address corresponding to the contents (code) of the write address sensor 3. At the same time, code 3 is changed as a result of its shift by one clock cycle under the action of a control signal from the control unit 4.

The reading of the next information from the accumulator G is performed at the address corresponding to the content (code) of the read through sensor 2,

After reading the next information, the code in sensor 2 changes as a result of its shift by one cycle under the action of the control signal coming from control unit 4. The signals from block 4 and sensors 2 and 3 change their states in sequence.

The alternation of the modes of recording and viewing may occur at random. In this case, a case is possible when the recording mode is predominant in time as compared with the transfer mode. This leads to the filling of accumulator 1 and the need to stop recording. Usually, the signal about filling up the accumulator 1 is generated when it contains several more free addresses that are not occupied by the input information in order to take into account the possible delay from the moment of issuance of the busy signal until the moment of input of information. In this device, the fill signal is generated by comparing the code in sensor 2 with the code generated at the output of the block of adders 5 connected to sensor 3. When the codes coincide, block 6 generates a fill signal to stop the recording of information. The appropriate choice of the connection circuit of adders 9 modulo two between the input and output circuits of block 5 provides, as it were, the transfer (shift) of the code to the input of block 5 from the c-shift register with linear feedback to the desired number of cycles

forward, within the period of states of the specified shift register.

Claims (2)

1. A buffer memory device containing sensors for writing and reading addresses, the inputs of which are connected to the outputs of the control unit, and the output to the accumulator inputs, the accumulator signal generation unit, which, in order to increase the device’s reliability, modulo two adders, the inputs of which are connected to the outputs of the write address sensor, and the outputs to one of the inputs of the accumulator signal generation unit, the other inputs of which are connected to the outputs of the connectors address sensor. 2. A popl device, characterized in that the address sensors of the entry and the shift are made in the form of shift registers with linear feedback. Sources of information taken into consideration during the examination: 1. Author's certificate М 371613, М.Кл G 11 С 9/00, 1971. 2. Author's certificate ff 427379, M.C. G 11 C 11/00, 1973. P /, - / fuz.S