SU771659A1 - Binary-to-binary-decimal code converter - Google Patents

Description

The invention relates to the field of automation and computer technology and can be used in the construction of devices for information conversion. A known converter of a double code into a binary-decimal, containing two serially connected adders modulo ten, with the outputs of adders pc modular ten each rus connected to the inputs of adders modulo ten neighboring rus, and the outputs of adders modulo ten younger rus are connected with converter inputs 1. A disadvantage of the known converter is a large amount of equipment and its rapid growth with an increase in the size of the code being converted. The closest in terms of circuit design and technical essence to the invention is a binary-to-binary binary code converter, containing binary sum-: tori and modular ten modulators connected in series, forming two rus, with the first group of binary inputs of the 5mators connected to the converter 2 inputs The disadvantage of this converter is the large amount of hardware and low reliability. The purpose of the inventive device is to reduce the cost of the equipment and increase the reliability of the converter. This is achieved by dividing the converter into a series of cells and by special switching of the inputs and outputs of the adders. The proposed binary-to-decimal binary code converter containing the binary converters combined into a step and successively connected summators of. the module consists of ten, forming two Russ, the first group of inputs of binary adders connected to the information inputs of the converter, additionally contains the element OR and 1 p / 10 conversion stages, where n is the number of bits of the binary code, in each of which the transfer former is entered In this case, the outputs of bits of binary adders, except the binary adder of the last stage, whose weight is multiple (), i7ic and the number of the stage (a 1 - |), are connected to the second group of inputs of the adder adder (a 1) -th stage, all the outputs of the bits binary an adder, with the exception of two high-order bits, having a weight of 2 10 (k 1 - 10), are connected to the first inputs of the corresponding adders modulo ten first rus of the a-th stage, and two high-end outputs having a weight of 2-10, connected, respectively, with the second and third inputs of the adder modulo ten most significant bit of the first tier a-th stage; the first outputs of all adders modulo ten of the first tier of each stage, except for modulators ten and two most significant bits, are connected to the first inputs of the corresponding summator modulo ten second Russian, the first outputs of three adders modulo ten second Russian a-th stage connected to the inputs of the transfer generator corresponding to the stage, the first outputs of adders modulo ten two senior bits of the first Russian connected to the second and third inputs of the adder modulo ten of the highest bit of the second rus, the first output of the a-th stage transfer former is connected to the input of the binary adder (a + 1) -th stage, the first and second inputs of the OR element are connected to the outputs of the transfer former and two respectively, the output of the OR element, the outputs of the adders modulo the ten least significant bits of both Rus, and also the second, third, and fourth outputs of the transfer drivers of all stages of the converter are outputs of the converter. FIG. 1 shows a block diagram of a binary-to-binary converter; in fig. 2 is a block diagram of a transfer driver. The transducer consists of n / th conversion steps, where n is the number of bits of the binary number to be converted. Each stage of conversion contains binary adders 1, as well as modulo ten adders and a shaper, transfer 3, combined into a matrix adder 4. Matrix adder contains seven consecutively connected modulators of ten first Russian and four modulo ten of the second Russian . At the outputs of the first rusa, six summation results are obtained, multiples of 10, which arrive at the input of the second rus, and four lower digits; 111oichmo-dss tichnn1 o number (2, 2 2-), 2 ° -10, arriving at the output of the converter . The younger bit of the binary number 2 is not involved in the conversion. At the outputs of the second rusa, three summation results are formed, multiples of which are fed to the inputs of the transfer generator, and four subsequent bits of the binary number (2, 2 2), that arrive at the output of the converter. At the output of the transfer former, bits of a binary-decimal number (2, 2, 2) are formed, arriving at the output of the transducer, and transfer arriving at the binary 1-higher-level adders. The output of binary adders, a multiple of 2 ° 10, and one output of the transfer driver of the last stage through the element OR 5 are connected to the outputs of the converter. The transfer form factor 3 contains (see Fig. 2) five elements AND-BU 6-10 analyzing the input signals and two elements OR-11, 12 that form the output signals. Moreover, the direct inputs of the NAND elements are the inputs of the transfer form, the output of the NAND element 6 is connected to the inverse inputs of the NAND elements 8, 10 and OR NII, 12, the output of the NAND element 7 is connected to the inverse the inputs of the elements AND-NO 6, 9, 10 and OR-NOT 11, the output of the element AND-NO 9 is connected to the second input of the element OR-NO 12, the outputs of the elements AND-NO 8, 10 and OR-NO AND 12 are outputs transfer driver. The conversion of a binary code to a binary one is carried out as follows. The weights of the input bits entering the converter can be expressed as follows: P 2 -10 (1-10 bits); Р-10 + К gIyuz + ((11-20 bits); PIO-.K .10 Н -. (. W × + (2 kNC-3) +. 10 ° (21-30 bits), where 1 10. Consider the operation of the converter, provided that the number of bits of the number to be converted is n 20. The weights of 20 binary bits and their decomposition are given in Table 1.

The 1-st conversion stage contains the following binary adders: a weight adder equal to 8 (2 8), performing the summation of the fourth bit of the binary code and the decomposition part of the eleventh bit of the binary code having weight 8; B16, which performs summation of the fifth bit of the binary code, parts of the decomposition of the eleventh and twelfth bits of the binary code, having a weight of 16, and the transfer of 28; weight adders 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, performing summation of the corresponding bits of the binary number and the corresponding parts of the decomposition of the bits. As a result of the summation, weights of 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192 and weight of 16384 are obtained. The numbers 1024, 2048, 4096, 8192, 16384 are laid out in accordance with the table. 1. In this case, multiples of 10-1000, 2000, 4000, 8000, 16000 are fed to the inputs of the binary second-stage conversion adders, and the numbers 8, 16, 32, 64, 128, 256 are again added to the previously obtained results. The largest number that can be obtained as a result of this summation is 1024. It is expanded by 1000 + 16 t 8. The number 1000 is fed to the input of the second-stage binary adder, and the numbers 16, 8 are again added to the previously obtained results. As a result of the latter

summations are weights of 8, 16, 32, 64,. 128, 256, 512, which together with the younger ones. binary digits having a weight of 2.4,

arrive at adders 2 modulo ten of the first rus of the matrix adder 4. Modulo ten adders 2; 2 converts the resulting binary sum of the weights of the binary bits 2,

4, 8, 16, 32, 64, 128, 256, 512 in binary-decimal code. The least significant bit of a binary number having a weight of 1 does not participate in the conversion.

The transformation is as follows.

way .... j

The modulo ten 2i receives trn high-order convertible binary code, namely 512, 256, 128. The following combinations may occur at its inputs

convertible bits; 512, 256, 128; 512, 256; 512, 128; 256, 128; 128; 256; 512.

Modulo ten 2i converts the bits of a binary number arriving at its input into a multiple of

10, where m is the number of the rus in which the adder is located. The resulting residues have values equal to the weights of the next binary bits.

The adder 2i performs the following transformations, presented in Table. 2

Combination bits at the inputs of the adder 2J

512, 256,

512, 256

512, 128

256, 128

128

256

512

Table

Output Combinations

adder 2j

640+ 256 + 2

640+ 128 10 - 2

640 10

256+ 128 2

128 2

256 2

256+ 128+ 128 2 + 2 +

The output of the modulo ten ad 2), a multiple of 10, the modulo ten 2 adder of the second rus, and the resulting residues are fed to the inputs of the adder jj

; pa 22 of the first rus. The input of the adder 22 also receives the subsequent seventh bit of the converted number. At the output of the last adder 2-J of the first rus, signals are generated

 2-10 10, 2. 10 ° and 2 ° 10, which are output from the converter signals. Six output modulator mode

Any ten first Russian multiples of 10, (640, 320, 160, 80, 40, 20) go to the modulo ten second Russian adder. Transform

 The second rune is implemented in the same way as the first run transform. At the yields of adders modulo ten of the second p) sa, the results of summation, edges 10. and ost, mk, a multiple of Yu, are formed.

So adder 2 performs the following transformations, presented in Table. 3

Table 3 The output signals of the adder 2i, multiples of AND), are fed to the inputs of the adder 2 of the same rus. The next bit from the adder 2 of the first rus also arrives at the input of the adder 2i. At the output of the last adder 24 of the second Rus, signals of 2 "10, 2 0 2-10 and 2 ° -10 are formed, which are the output signals of the converter. Three output signals of adders of the second Russian, multiples of 10, (200,

Combinations of the input bits of the transfer mapper

800, 400, 200

800, 400

800, 200

400, 200

200

400

800

Thus, the transfer signal is generated if the sum of the weights arriving at the input of the bits of the device is greater than or equal to 10.

In the form regulator, the 3-element AND-HE 7 analyzes the presence of the first () and third (2. input signals. If these signals of the output of the AND-7 element are simultaneously present, the inhibitory potential is fed to the inverse inputs of the AND-NE elements 6, 9, 10 and the resolving potential on the element .OR-NOT 11. To the output, the transfer former, from the output of the element OR-NOT 11, receives a signal having a weight of 2 10.

The element AND-NOT 6 analyzes the presence of the first (2-10) and second () input signals. With the simultaneous presence of these signals and the absence of a prohibiting potential from the output of the element AND-NOT 7 (the third input signal is absent) from the output of the element AND-NOT 6, the prohibiting potential arrives at the inverse inputs of the elements AND-НЁ 8, 10 and the resolving potentials of the elements OR-NOT 11, 12 Signals that have a weight of 2 ° .10 and 2-10 are received at the output of the transfer shaper from the outputs of the elements OR-NOT II; 12

Shaper output signals

1000 + 400 2 ° 10

1000 + 200 2 ° - 10 + 2 -10

1000 2. 10

400 + 200 + 210

200 2-10

400 2. ten

800 2 10

If there is only the first bit of the input signal () from the outputs of the AND-NE 6, 7 elements, the resolving potentials are fed to the inverse inputs of the AND-10 element. The output of the transfer former from the output of the AND-10 element is a signal having a weight of 2, - ten. If there is only a second input signal (10), the invert potential of the IS-HE element 8 is output from the AND-HE element 6 input. From the output of the element AND-NE 8, the output of the transfer former receives a signal having a weight of 210. If there is only a third input signal (2. 10), the inverse input of the element IS-NOT 9 receives the resolving potential from the output of the element IS-NOT 7. The signal having a weight of 2 to 10 from the output of the element AND-NO 9 is fed to the input of the element OR-NOT 12, and from its output to the output of the transfer former.

Claims (2)

With the simultaneous presence of the second (2 10) and third () input signals, output signals having a weight of 10 and 10 are formed in a manner similar to the cases discussed above with only one second or one third input signal. With the simultaneous presence of all three inputs400, 800), they are fed to the transfer conditioner 3, which forms an output signal, p 2 10 10, arriving at the input of a second-stage binary adder, and three output signals, multiples of 10 (200, 400, 800), to the output of the converter. The operation of the transfer agent is characterized by the table. 4. Table 4 of the signal signals, the inhibitory potential from the element AND-NOT 7 is fed to the inverse inputs of the elements AND-NOT 6, 9, 10. The resolving potential from the output of the element AND-NOT 7 goes to the input of the element OR-NOT 11, and the resolving potential potential from the output of the element AND-NOT 6 - to the inverse input of the element AND-NOT 8. The output of the transfer former receives signals from the outputs of the elements OR-HE 11 and AND-NE 8, having a weight of 2 ° 10 and 2.10, respectively. The second conversion step performs the automatic summation of parts of the decomposition of the bits of the converted binary number, multiples of 10. and the results of the summation of the first stage of multiples of 10. It contains binary adders for adding the following values: 1 thousand 2, 4, 8, 16, 32, 64 , 128, 256, 512 thousand. The largest number that can be obtained as a result of summation is 1024 thousand. It is decomposed by 1024 thousand TYS. -1MLN. + 16 thousand + 8 thousand. The number 1 million arrives at the element OR 5, and the numbers 16 TB, 8 thousand are added to the previously obtained results of the summation. As a result of this summing, the weights are 1 thousand, 2, 8. 16, 32, 64, 128, 256, 512 thousand, which are fed to the second-stage matrix adder 4 of the second stage, which converts the weights of binary digits to Volume code. Conversion is similar to that described for the first stage, only the weights of the converted bits are increased 10-fold (512, 256, 1 128 thousand instead of 512, 256, 128, respectively). At the output of the second-stage matrix adder 4, signals (2, 2, 2) 10 (2 ", 2, 22) 10 (2 °, 2S 2) are formed. 10 In the prototype converter, for n 30 you need 9 transform levels containing (p-3) + (p - 6) + (p-9) + + () + (p-15) + (p-18) + (p-21) + + (p-24) - (- (p-27) 135 adders mod ten. The proposed converter requires three conversion stages containing 45 four-bit binary adders and 12x3 36 modulo ten adders. Since it is decimal; adder: on 133 series microcircuits contains 2.5 cases, and a dual four-bit adder - 1 case The proposed converter allows you to reduce hardware costs by approximately 2.5 times. The formula of the invention and the binary-to-binary converter, containing combined binary converters in the conversion stage, and modulo ten consecutively adders, forming two rus, the first group of binary inputs adders connected to the information inputs of the Converter, characterized in that, in order to reduce the cost of equipment, it contains the element OR and p / 10 (conversion stages, g de n is the number of bits of the binary code, into each of which the transfer driver is entered, the outputs of the bits of binary adders, except the binary adder of the last stage, whose weight is a multiple of 10, where a is the number of the stage and 1; connected to the second group of inputs of the binary adder (a + 1) -th stage, all the outputs of the bits of the binary adder, with the exception of two star bits, having a weight of 2 (k 1-10), are connected to the first inputs of the corresponding adders modulo dec The first rusa of the a-th stage, and the two outputs of the higher bits, having a weight of 2-10, are connected respectively to the second and third inputs of the adder at the mol ten of the most significant discharge of the first rus of the a-th stage, the first outputs of all adders modulo dec the first russa of each step, except for the sum modulators of ten high-order bits are connected to the first inputs of the corresponding adders modulo ten of the second rus, the first outputs of the three adders modulo ten of the second russa a-th stage are connected to the inputs of the transfer former of the corresponding level, the first outputs of the adders modulo ten two leading bits of the first rus are connected respectively to the second and third inputs of the adder modulo ten most significant bits of the second rus, the first 1 output of the a-o stage transfer driver is connected to the binary input the adder (a + 1) -th stage, the first and second inputs of the OR element are connected to the outputs of the transfer former and the final adder of the 1st CTjoieHH respectively, the output of the OR element and the outputs of the adders modulo ten least significant bits of both rus, and also the second, third and fourth outputs of the transfer drivers of all stages are the outputs of the converter. Sources of information taken into account in examination 1, US Patent No. 3638001, cl. 235-155, published. 1975. 2. For backing H ° 2505621 / 18-24, cl. G 06 F 5/02, 1977, ° on which a positive decision is made. ; hi h- -d r fbsMwfi-M-W jMf / I -one iz . (ЖЖПда «// jH Sv -.y r« i.A. / .. л1 |.. Л (fff.lS-fiM-t (f, r.P.l) -4.; ./