JPH03214233A - Multiplier - Google Patents

Abstract

PURPOSE:To obtain (8 X n) types of sets of input vectors for detection of the faults of a Wallace tree conversion part consisting of the 1st - n-th conversion parts by using a test mechanism which applies an optional input pattern at every full adder or half adder of each conversion part in accordane with the types of input vectors. CONSTITUTION:In a test mode, the input vectors A and B are secured to equalize the inputs of all full adders of an m-th conversion part (1<=m<=n) 3m with a test mechanism. Then the input patterns are inputted to all full adders of the part 3m with the change of both vectors A and B. These input patterns of all full adders are available in eight ways and therefore eight types of sets of vectors A and B are obtained for the detection of the faults of all full adders of the part 3m. Thus, (8 X n) types of sets of vectors A and B are obtained for the detection of faults of the Wallace tree conversion part 3 consisting of the 1st - n-th conversion parts 31-3n.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplier used in a digital signal Sy processing LSI, particularly a Wallace tree (Wallace-tree) system which is designed to simplify fault test vectors. It concerns multipliers.

[Conventional technology]

In general, the configuration of a digital parallel multiplier consists of a partial product generator, a partial product converter that converts a multistage partial product group generated by the partial product generator into a two-stage partial product group, and a partial product converter that converts the multistage partial product group generated by the partial product generator into a two-stage partial product group. It is divided into two manual addition sections that add the two-stage partial products Rr generated by the conversion section.

Among these, the configuration of the partial product converter is generally a carry-save method or a Ume-save method.
One type of Resturi type is known.

The carry-save type partial product converter has three full adders with two outputs, and when the full adder performs an operation, the number of partial products decreases by one. The values are added using an adder and finally converted into a two-stage partial product. This carry-save method is easy to assemble because it uses an array, and while it is easy to create a fault test vector (an input vector that tests the switching of all gates in the circuit), There is an inconvenience that the number of gates increases in proportion to the number of multistage partial product stages generated by the first partial product generation section, and l:';J,
i! In terms of performance, it is inferior to the Tsuso-Retsuli method.

On the other hand, the Wallace Tree one-way type partial product conversion unit does not perform the carry-save type multi-stage partial product addition sequentially, but in a row such as 1)f;
Partial products of the same order of multi-stage partial products are added simultaneously using multiple full adders, and the resultant digit 1-off signals and multi-stage partial products of the sum signal are simultaneously added to history. The structure is such that a plurality of full adders are used to perform the addition operation until a two-stage partial product is finally obtained.

Similar to the carry-save method, this Wallace Sori one-sided method also uses the fact that the full adder has three inputs and two outputs, and that the partial product decreases by one each time it passes through the full adder. It is a method to convert to digit 1, digit number 1, sum 4;
The propagation of ;shi;, is not carried out sequentially as in the carry-save method, but is carried out in parallel, resulting in high-speed I
In terms of 'l, it's a good hit.

FIG. 2 shows an example of a method for converting an 8-bit x 8-bit multiplication into a two-stage partial product using the Wo-Restry method. In this figure, (I1) is the first converter of the Wallace tree one-way system of the standard partial product group that is generated by the partial product generator when performing 8-bit x 8-bit multiplication, and is indicated by a circle in the figure. (n1-1) to (++-5-8) are each an element of a partial product group, and (If-l-a) to (II-2-e) are each an adder, shown as a rectangular part in the figure. Of these, the shaded area represents a 1'4 adder, and the white area represents a full adder.

(12) is a conversion unit (second conversion unit) for a newly generated partial product group, which is a combination that performs operation p by the first conversion unit (n) for the partial product group. In the second conversion section (12) of this partial product group, those indicated by 0 are the first conversion section (addition of 1 "3 (
II-l-a) Newly generated summation as a result of the calculations by (II-2-e) - Those indicated by C are digits.
The Lt signal, indicated by O mark, is the element signal of the partial product group that was not calculated in the standard partial product group (l1) and is given as an element of the partial product group (12).

Also, (+2-1-1) to (+2-6-1) are each element of partial product group (12), (+2-1-a) to (+2-2-b
) are adders, and are shown as strip-shaped rectangles as in the case of the nη partial product group (n), and the hatched areas indicate half adders and the white areas indicate full adders.

(13) is the second of the same partial product group, similar to the partial product group (12).
As a result of the calculation performed by the conversion unit, the newly generated partial product #L (+4) is the respective partial product J! 1 (I 1 )
Similar to (+2), the transformation part of the partial product group (third transformation part')
As a result of the calculation using (+3), this is a new group of partial products.

(15) This is a group of partial products that is the final result of converting the multi-stage partial product ljr of the first converter (n) into a group of two-stage partial products by the t-Restorian partial product converter.

In the Wallace tree one-sided system, for example, for the partial products in the 8th place from d of the multistage partial product group of the first conversion unit (n), the full adder (I
I-1-gHIl-2-c) are added simultaneously, and the same rank Imaka 3? (+2i-8) of vessel (12-14)
(12-3-5) is combined with Washin-shi, and (12-2-7) (1
2-2-b) (12-4-4) without being carried as a digit 1-off signal.

Full adder (+2-1-
f) (+2-1-g) or)1': Adder (+2-2-b
), but in the same way, the calculation part of the first conversion part (n) of the same digit, the calculation part of the first conversion part (n), or the partial product calculation of the standard partial product group that is not calculated, is used for full addition or ゛1' An operation p of addition is performed. In such a single game operation, all orders are executed in the lrT sequence, and the final two-stage partial product J! Similar operations are repeated until it is converted to f (15).

8 bits x 8 bits, p is the delay time of the four-stage full adder (delay n.' of the conversion section of the partial product group (n) to (14)).
1) into the final two-stage partial product group (15).

This is a significant improvement in speed compared to the carry-save method, which required seven stages.

[Problem to be solved by the invention]

” - As mentioned above, the Wallace tree one-way system is considerably advantageous in terms of speed compared to the carry-save system, but
There is a problem in that it is difficult to always create failure test vectors.

However, as of now, no proposal has been made for a single test stage such as a test method for a Wallace Treeker multiplier or a test circuit that has sufficient practicality. The only methods available are to increase the fault detection rate by 1-j using the fault test vector, or to provide a test function that forces an external signal to the adder, which is difficult to detect internal faults, by 1-j. A test method that can increase the failure detection rate well has not been realized.

When constructing an I calculation Z+ of l 3 × 1.2 using the -Lestree force formula, even if 2000 test vectors are generated l-J by random numbers, the circuit fault detection rate is said to be less than 60%. Results are also reported.

・Generally, when considering a fault detection vector for a full adder or a half adder, one Imaka T＞” As an input to Ji, (
Low, low, low) (low, low, high) (low, high, low) (low, high, high) (high, low, low) (
100% fault detection was achieved for the first time by detecting eight input vectors: high, low, high) (high, high, low) (high, high, high). (low, low) (low, high) (high, low) (high,
IJ the four types of vectors (high), 100% for the first time.
failure detection is achieved.

Now, 8 bits × using the Wallace tree method described above
For example, even if all vectors (2 to the 16th power, that is, 65,536 vectors) are obtained as fault detection vectors for an 8-bit multiplier, all input patterns will be input to all 31 adders and ゛+' adders. Since it is not always possible to give the same amount of data, the failure detection rate may not be 100%.

However, as a practical matter, if all the vectors are counted, even if the failure detection rate becomes 100%, it will still be perfect as a non-defective product selection inspection.

However, it is impossible to actually obtain all vectors, and in reality, only vectors with a failure detection rate of about 90% are used for inspection to select non-defective products.

The present invention achieves 100% fault detection with a small number of fault detection vectors by adding a simple test mechanism to the fault coverage of the partial product conversion section in the multiplication section using the i, -Restreet equation. [1] The purpose is to provide a multiplier capable of lj.

[Means to solve the problem]

1-Note] In order to achieve the objective, the multiplier of the present invention has a Wallace-Tree one-way partial product conversion in the multiplier 37, and a Wallace-Tree conversion unit that converts a multi-stage partial product into a two-stage partial product. a first converting unit that converts the first multi-stage partial product generated by the partial product generating unit into a second multi-stage partial product by performing an operation p using a plurality of adders; a second conversion unit that performs arithmetic operations on the second multistage partial product generated by a plurality of adders to convert it into a third multistage partial product; 1 with the r1th conversion capital which performs a prefecture on the nth multistage partial product obtained by using a plurality of adders and converts it into a final two-stage partial product.
; When divided into l'r+ conversion units, the same amount of human power butter is added to all the full adders or ゛I' and adder nf for each conversion unit from the input vector of the multiplier main body. , and a test mechanism is provided for testing an arbitrary input pattern for each of the full adders or half adders of each of the conversion units according to the type of the human vector.

[For production]

According to the configuration described in -1-, in the test mode, the present invention calculates the input vector that makes the inputs of all the full adders of the m-th conversion section (1≦m≦n) the same, and converts the doujin vector By changing -, all the human cover turns are input to all the full adders of the m-th conversion section. Since there are eight types of input patterns for this full adder as described above, the test mechanism realizes eight types of input vector sets for detecting failures in all full adders of the m-th conversion section. As a result, the set of input vectors for detecting a failure in the A-less tree transformer consisting of the first to nth transformers can be realized in (8×n) types.

Therefore, it takes 1-1 effort to achieve 100% fault detection rate of the partial product transform section of the multiplier p section using the Wallace tree transform method with a small number of fault detection vectors.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Figure 1 (A) is - General A
- It is a block diagram of the To 31 device using the Les tree conversion method. In this figure, (1) is multiplied by 3'> the vessel body, and (2) is multiplied by '3? The main body (1) is an 819-minute integral part, (3) is a Wallace/Rieker converter, and (4) is a two-man power adder.

The Wallace-Lee transformation unit (3) has N number of transformation units (31).
~(3n). (31) is a combination of multiple additions 32 to the first multi-stage partial product generated by the partial product generator.
(32) converts the calculation by the device into a second multi-stage partial product by 91; This is a second conversion unit that performs operation p and converts it into a third multistage partial product. Similarly, (3m) is the (m-1)th converting section (3m-1).
(3n) is an m-th conversion unit (m: integer) that performs operation S1 using a plurality of adders on the n-th multi-stage partial product generated by 1) and converts it into a (mal)-th multi-stage partial product; n-1
) An n-th conversion unit (n: integer) performs calculations using a plurality of adders on the n-th multi-stage partial product generated by the conversion unit (3n-1) to convert it into a final two-stage one-part product.

(A) (B) is the input vector to multiplier (1), (C)
is the output vector.

(D) is a switching mode between the execution mode, which is a normal calculation mode, and the test mode, which is a calculation mode for failure detection.
It is 吋.

The present invention realizes failure detection of the A-less tree transform unit in a Wallace tree transform multiplier using a small number of input vectors (A) ([1]), and the following test method can be used. .

In the test mode, the m-th conversion unit (1≦In≦n)
A human vector (A
)(B) by 5 and changing the input vector (^)(B), all input patterns are manually input to all full adders of the rn-th conversion section.

As mentioned above, there are eight input patterns for the full adders, so if we have a test mechanism that implements the l-notation method, it will be possible to detect faults in all the full adders in the m-th conversion section. The set of input vectors (A) and (B) can be realized in eight types. In other words, the input vectors (A) and (B) for detecting a failure in the Wallace tree conversion unit consisting of the first to nth conversion units
This means that the set can be realized in (8Xn) types.

FIG. 1(B) shows an example of a specific configuration of a multiplier having the test mechanism described in -.
The present invention has a configuration in which the test mechanism of the present invention is added to a J-Less tree transform type multiplier.

In FIG. 1(B), (31) is the first conversion unit using the Wallace tree equation of the standard partial product group generated by the partial product generation unit when performing 8-bit x 8-pinto multiplication; The O and X marks in +-1-1) to (1-8-8) are recognitions of the partial product group of the first conversion unit (31). In the first conversion unit (31), (1-1-a) −(1-2-j
) is a full adder. (1-^) to (1-D) are partial product control circuits of the first converter (31) that also control switching between the test mode and the execution mode, and among these circuits, (+-A
)(1-C) is composed of a full adder and 1. Inputs to each partial product control circuit (LA) to (1-D) are controlled as described below.

That is, in the execution mode, the partial product control circuit (+-A
) to (1-D) are forcibly set to low-level signals lj.

In the test mode, the multistage partial product J of the first conversion section (31)
Any one on the same line of iT is input.

Here, <1-1-1> becomes (1-1), (+-2-
1) becomes (1-2), (1-3-2) becomes (1-3>,
(1-4-1) becomes (1-4), (1-5-n becomes (1-
5), (1-6-2) becomes (+-G), (■-73)
(1-7) and (1-8-1) are input to (+-8), respectively.

The X marks in the multi-stage partial products of the first conversion unit (31) indicate the inputs of the partial product control circuits in the same row ((I■) to (
18) is input. −・For example,
(1-1) is input to (1-1-9) and (1-1-10), and (+-6-1) and (+-6-10) are input (
+-6) is input.

(32) is a Wallace tree one-way second transform unit for a group of partial products newly generated as a result of the operation p performed by the first transform unit (31). In the second converter (32), the 0 mark is calculated by adding p pieces (1-1-a) to (+-2-j), and the result is a new /l, the sum (+rSJ') Yes.The circle mark indicates that the partial product group that was not calculated in the standard partial product 77r (31) is the partial product group (32) as it is.
It is assumed that Ij means "Kiki" which can be seen as an element of "Ij".

(2-1~1)~(2-G-n) are partial products/Fl:(3
2), and the parts surrounded by rectangles are shown as rectangles that are reduced by (2-Ia) - (2-2-k) and (2-^) (2-B). 'I am using the S94 device.

Of these, (2-A) (2-8) is the second converter (3
2), the partial product control circuit (2-
A) Human power is the sum of (+-A) 1. S no and digit 1-ge (
5 inches and (+-4)ノ(,i S,'cah soh(2-I
O2-202-3) To L Te'j Erareru. In addition, the input of the partial product control circuit (2-B) is connected to the partial product control circuit (+
The sum signal of -C), the digit 1 signal, and the a9 of (1-8); respectively, as (2-4), (2-5), and (2-G)! J
,available.

The inputs of (2-ha) to (2-1-i) have corresponding digits, respectively (lI-a) to the sum of (1-1-i) Ir5
3" and digit" 2, i, (+-4-1) ~ (+-4
-8) signal is input. -For example, full addition J
The inputs to T(2-1-c) are the sum signal of the full adder (1-1-d) and the digit 1-digit of the full adder (1-1-c) (1-4). -23 Shinjino.Similarly, the full adder (2
The sum and carry of full adders (1-2-a) to (L-2-j) whose digits also correspond to the inputs of 2-a) to (2-2-k) 3-: Bow and (1-8-1) ~ (1,9
-8) The signal is manually generated. The × marks in the multi-stage partial products of the second converting unit (32) are the same 1J (2-1) to (
2-G) elements are input.・For example, (2
-n1) has (2-1) input, and (2-6-1
) (2-6-2) (2-6) is input to (2-G-3).

(33) is also the same as the second converter (32).
As a result of the calculation in 2), the internal structure and the IJFJ are shown in the A-Restreet one-way third conversion section with the newly generated partial product Rr. The meaning of the second converter (32) is exactly the same as that of the second converter (32).

The input of the partial product control circuit (3-A) is the partial product control circuit (3-A).
The sum signal and carry borrow of the digit-1-digit of 2-A) and (2-B) are obtained as (3-2H3-3) and (3-4), respectively. Full adder (:l-1-a) ~ (3-1-
Full adders (2-1
-a) to (2-1-+) digit 1-off signals and the full adder (
2-2-a) to (2-2-k) are input. - For example, Imaka n', Z4 (3
-I-c) is input to digit 1. of the full adder (2-1-c).
When the number 1 is set, the total number 3' is the sum of the unit (2-2-b), and the digit 1 of the full adder (2-2-a). This is Geshinshi 3.

The X mark in the multi-stage partial product of the third converter (33) is the first and second
Similarly to the conversion parts (31) and (32), (3
1) ~ (3-4 "〃Elements are manually input. - To give an example, (3-3) is input to (3-3-n and (3-1-13), and (3-3) is input manually. 3-4-1 and (3-4-2) have (3-
4) is being input. (3-1) is the partial product control circuit (2
-A) is only entered as Washin XJ. In this embodiment, it has no particular meaning. However, 3-n) ~ (31
-n) row h″l is added by this third converter (33), and when conversion is performed by a transformer, (3-1) becomes
It is conveniently used for inputting information into the mark.

Similarly to the second conversion unit (32) and the third conversion unit (33), (34) is also the result of the calculation performed by the third conversion unit (33).
The fourth Wallacellian equation of the newly generated partial product group
In the conversion section, the internal structure and the meaning of notes 3 (0 marks, ・marks, ○ marks, and areas surrounded by rectangular strips) are exactly the same as the second and third conversion sections (32H33). .

The input of the partial product control circuit (4-A) is the signal S of (3-1).
Sum of depletion partial product control circuit (3-^) 4:';”J and digit]
-Gei, -: Bows are (4-1) (4-2) (4) respectively.
-3) Ij can be obtained. Full adder (4-1-a)
Each digit corresponds to the input of ~(4-1-m) (3
-1-1) to (3-n, 1S, full adder (3
-l-a) to (3-1-m), the sum A, ζ silla and digit 1 are input manually. For example, the full addition r(4-1
-c) input is (,1 of (:l-1-G), Imaka 37E:+(3-1-c) Nowa Shinyumi, and full adder (3
-1-b) digit l-ge (+4), the fourth conversion part (34
The X mark in the multi-stage partial product of ) also corresponds to the second and third conversion parts (32H3
Similarly to 3), elements (n) to (4 to 3) in the same row are entered manually.

(35) is the final partial product group obtained by converting the multistage partial product #Y(31) into a two-stage partial product group using the Wallace-Nolly force equation, and is the final result of the partial product group that is used by the two-man power adder in FIG. 1(A). (4)
This corresponds to

Next, each mobile mode (execution mode AST mode) of this embodiment will be explained.

In the execution mode, the input ° element ((+-1
)~(1-8)) to low level 6, (2-n~
(2-6), (31) to (3-4), (4-1)
All the inputs of the partial product control circuit of ~(4-:1) are at low level, so all the X marks are at low level L,
This means that all the partial product elements added in excess by the first to fourth conversion units (31) to (34) are not added. In other words, only the first standard partial product is the final result of the two-stage partial product #T(
35), and a +EL calculation result is output.

Next, the operation in test mode will be explained. In the test mode, as described above, the input elements ((1-1) to (
+-8) ) contains (1-nHl-2-n(1-3-2
)(l-4-1)(1-5-1)(1-G-2>(+-
7-3) (1-8-1) is input. Here, the power 3 to make each row 1t1 of the partial product group of the first conversion unit (31) equal to
Let's calculate the input vector of 7 devices. This vector can be calculated using the formula (all high) X (X)...■. X can also be a vector like . For example, the power p of 8 bits x 8 bits is (nnnn
) becomes.

■Given a vector like the formula, all 9-added Si devices (
1-I-a) to (1-1-i) have the same pattern, and therefore their outputs also have the same pattern. Imaka)'>, Z+(1-2-a)-(
The same applies to 1-2-k).

Also, in the second conversion section (32), the full adder (1-1-a
) to (+-1-1) output the same pattern, the same pattern is applied to the inputs of all full adders (2-1-a) to (21-i), and therefore their outputs will follow the same pattern.

The same thing is done in the fourth converter (34).

As shown in 1- below, if the input vector of the multiplier is set to a vector such as the formula , ■ Depending on the type of input vector in equation
I can do it.

Next, 8 bits x 8 using the Wallace tree conversion method
Let's find the number of vectors that are faulty in the partial product conversion section of the multiplication section of Via.

First, the number of test vectors for fault testing the full adder is 8, as mentioned in the section on the problem to be solved by the invention.
That's right. Therefore, the first converter (31) converts eight ways (
Full adders (+-1-a) to (1-1-+) and full adders (+-2-a) to (1-2-J) can be tested simultaneously), second converter (32 ) but 8 ways (Imaka 31 (2-1a) ~ (2 Kawagawa) and full addition Z4 (2-2-a
)-(2-2-k) are tested at the same time? 1), the third converter (33) has 8 ways, and the fourth converter (34) has 8 ways, that is, in total, 1t32 ways of multiplication vectors are l−r,
You can test all full adders just by

However, since there are variations in the input pattern of the full adder (for example, all JJII of the first converter (31)
In the input of calculation Z4, (low, low, low) or (high, high,
When the pattern of (high) is added, the inputs of all the full adders of the second converter (32) to the fourth converter (34) also become the pattern of (low, low, low) or (high, high, high). Become)
, which is actually 1-considerably less than 32 vectors.

〔Effect of the invention〕

2) As explained above, when using the multiplier of the present invention,
The multistage partial product of the multiplication part using the Wallace tree one-way system is 2
'J T>
Each of the above conversions from the input vector of the device body? The same input pattern is applied to all the full adders or every 14 adders of J's m, and the same input pattern is applied to every full adder or half adder of each conversion unit depending on the type of input vector. Since a test mechanism that provides an arbitrary input pattern is used, in the test mode, eight types of input vector sets can be used to detect failures in all full adders in each converter. The set of input vectors for fault detection of the Wallace tree transformer consisting of n transformers is (8Xn
) can be realized by types.

Therefore, the fault detection vector, which conventionally increases exponentially with respect to the bit width of the multiplier or multiplicand, is now on the order of several tens of fault detection vectors, and it has the excellent effect of achieving 100% fault detection. It became a thing.

In addition, even if this test mechanism is used, the number of gate delay stages does not change at all, and without sacrificing the speed of the circuit,
This has an excellent practical effect of being able to realize a test circuit.

Table 1 shows the number of delay stages of a full adder using the Wallace Tree one-way method when performing ri x n-bit multiplication, and
The number of failure test vectors of the partial product converter when using the test mechanism of the present invention is shown.

Table 1

[Brief explanation of drawings]

FIG. 1(A) is a block diagram of a multiplier using the A-less tree conversion power formula of the present invention, and FIG. ? A configuration diagram showing an example applied to a device, Fig. 2 shows a conventional 8-bit x
This is an 8-bit L-less tree conversion system. (1) Multiplier main body, (2) Partial product generation section,
(3)...Wallace tree conversion unit, (4)...2
Manual addition section, (31) to (3n)'-conversion section, (35
)・Two-stage partial product group, (1-11) to (1-8-81...
・Partial product simple of the first conversion partial product conversion part, (2-t1) ~
(2-6-n)... Partial shell element of the second transformation part, (+-
1-a) -(4-I-m)-9+37-4, (+-A
) ~(4-D)... Partial product control circuit, (1-1) ~
(4-3)...Input element of partial product control circuit, (A)
(B)...Input vector (C)...Output vector,
(D)...Switching signal between execution mode and test mode. No. 3 (,4)

Claims (1)

[Claims] In a multiplier having Wallace tree type partial product conversion, the Wallace tree conversion unit converts a multi-stage partial product into a two-stage partial product, and converts the first multi-stage partial product generated by the partial product generation unit into a plurality of a first conversion section that performs an operation using an adder to convert it into a second multistage partial product;
a second multi-stage partial product generated by the converter, which is converted into a third multi-stage partial product by performing calculations using a plurality of adders;
a conversion unit; and an n-th conversion unit that similarly performs an operation using a plurality of adders on the n-th multi-stage partial product generated by the (n-1)th conversion unit to convert it into a final two-stage partial product; When divided into a total of n conversion units, the same input pattern is given to all the full adders or half adders of each conversion unit from the input vector of the multiplier main body, and the input vector of the input vector is A multiplier characterized in that a test mechanism is provided for applying an arbitrary input pattern to all the full adders or half adders of each conversion unit depending on the type.